US20070267725A1 - Semiconductor chip, method of manufacturing the semiconductor chip and semiconductor chip package - Google Patents
Semiconductor chip, method of manufacturing the semiconductor chip and semiconductor chip package Download PDFInfo
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- US20070267725A1 US20070267725A1 US11/702,131 US70213107A US2007267725A1 US 20070267725 A1 US20070267725 A1 US 20070267725A1 US 70213107 A US70213107 A US 70213107A US 2007267725 A1 US2007267725 A1 US 2007267725A1
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- semiconductor chip
- top surface
- conductive film
- conductive
- substrate
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- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
- H01L23/045—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads having an insulating passage through the base
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Abstract
In a semiconductor chip, a body has a top surface where a pattern is formed, an underside surface opposing the top surface and a plurality of side surfaces. A plurality of electrode pads are formed on the top surface of the body to connect to an external terminal. A shielding conductive film is formed on the surfaces excluding the top surface of the body where the pattern is formed. A conductive via is extended through the body to connect one of the electrode pads with the conductive film.
Description
- This application claims the benefit of Korean Patent Application No. 2006-43946 filed on May 16, 2006 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to a semiconductor chip package, more particularly, in which a shielding conductive film is connected to a ground through a via hole, and a manufacturing method thereof.
- 2. Description of the Related Art
- A high frequency module for use in a mobile telecommunication device such as a mobile phone is constructed of a high frequency circuit including a high frequency semiconductor device and a periphery circuit that are formed on a substrate thereof.
- In general, current propagating in an electronic device induces electric field and magnetic field therearound, thereby generating a space due to electric potential difference. Here, the electric field changes with time and generates electric magnetic field therearound. That is, regardless of the induction of the device, current flows to create electromagnetic noise, which is an unnecessary energy.
- Such electromagnetic noise, if transferred to other devices through a path, leads to degradation in performance and malfunction thereof.
- To shield the electromagnetic noise and protect the semiconductor device, a shielding technique for forming a shielding film has been employed.
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FIGS. 1 a and 1 b illustrate a shielding structure according to the prior art. -
FIG. 1 a is a cross-sectional view illustrating a high frequency module having a highfrequency semiconductor device 12 on asubstrate 11 shielded via ametal cap 12. - In the conventional shielding structure of the high frequency module shown in
FIG. 1 a, themetal cap 13, if reduced in its thickness, cannot remain strong but is easily warped, potentially contacting the high frequency device. To prevent short-circuit caused by contact between themetal cap 13 and the high frequency device, a certain space should be preserved under themetal cap 13 to accommodate themetal cap 13 that may be warped. For example, the metal cap should be formed to a thickness of 100 μm, and an inner space thereof should be designed to a thickness of 80 μm. This physical volume stands in the way of miniaturization of the high frequency module. -
FIG. 1 b is a cross-sectional view illustrating the high frequency module in which the shielding film is formed via ametal film 15 after resin molding. - In
FIG. 1 b, the highfrequency semiconductor device 12 is mounted on thesubstrate 11 and resin molded to be hermetically sealed. Then the shielding film is formed on a surface of amold 14 using themetal film 15. - This leads to smaller physical volume compared to a case where the metal cap is adopted. Yet, the metal film formed on the mold is not connected to a ground of the substrate, thus insignificant in terms of shielding effects.
- The present invention has been made to solve the foregoing problems of the prior art and therefore an aspect of the present invention is to provide a semiconductor chip which has a shielding layer formed thereon to connect to a ground, when the semiconductor chip is mounted on a substrate, thereby to enhance shielding effects and ensure the chip to be mounted in a minimal volume, and a semiconductor package having the semiconductor chip.
- Another aspect of the present invention is to provide a method of manufacturing the semiconductor chip having the shielding layer formed on a wafer.
- According to an aspect of the invention, the invention provides a semiconductor chip including a body having a top surface where a pattern is formed, an underside surface opposing the top surface and a plurality of side surfaces; a plurality of electrode pads formed on the top surface of the body to connect to an external terminal; a shielding conductive film formed on the surfaces excluding the top surface of the body where the pattern is formed; and a conductive via extending through the body to connect one of the electrode pads with the conductive film.
- The electrode pad connected to the conductive via may be connected to an external ground and grounded.
- The conductive film is formed only on the underside surface of the body.
- According to another aspect of the invention, the invention provides a semiconductor chip package including the semiconductor chip as described above; a substrate where a ground lead pattern and a plurality of lead patterns are formed; and a plurality of bumps disposed between the respective electrode pads of the semiconductor chip and the respective lead patterns of the substrate to electrically connect the semiconductor chip with the substrate.
- The electrode pad connected to the via hole is connected to the ground lead pattern of the substrate.
- The conductive film is formed only on the underside surface of the semiconductor chip.
- According to further another aspect of the invention, the invention provides a method for manufacturing a semiconductor chip including:
- forming via holes in a wafer including unit chip areas to connect from an electrode pad on a top surface of a wafer where a pattern is formed to an underside surface of the wafer opposing the top surface so that at least one of the via holes is formed in each of the unit chip areas;
- filling the via hole with conductive material;
- forming a conductive film on the underside surface of the wafer to contact the conductive material filled in the via hole; and
- cutting the wafer into unit chips.
- The manufacturing method may further include forming a shielding conductive material on a side surface of the cut semiconductor chip.
- The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
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FIGS. 1 a and 1 b are cross-sectional views illustrating a shielding structure according to the prior art; -
FIG. 2 is a cross-sectional view illustrating a semiconductor chip package according to an embodiment of the invention; -
FIG. 3 a is a perspective view illustrating a semiconductor chip according to another embodiment of the invention, andFIG. 3 b is a cross-sectional view illustrating a semiconductor chip package; and -
FIG. 4 a to 4 d are perspective views illustrating a flow of a method for manufacturing a semiconductor chip ofFIG. 3 a. - Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
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FIG. 2 is a cross-sectional view illustrating a semiconductor chip package having a semiconductor chip mounted on a substrate according to an embodiment of the invention. - Referring to
FIG. 2 , thesemiconductor chip 20 is flip-bonded onto thesubstrate 21. - The
semiconductor chip 20 has abody 22 provided with a plurality ofelectrode pads 28 on atop surface 22 a thereof. - A
conductive film 25 is formed on anunderside surface 22 b and side surfaces of thebody 22 of the semiconductor chip where the electrode pads are not formed. Also, avia hole 27 is perforated through thetop surface 22 a and one of the side surfaces of thebody 22. - The
package substrate 21 is manufacturable by the same process as the one for fabricating a printed circuit board (PCB), or by High Temperature Chemical Cleaning (HTCC) or Low Temperature Co-fired Ceramics (LTCC). - A circuit pattern is disposed on the
package substrate 21 to input and output a signal, and vias are formed to be connected respectively with electrode pads on the circuit pattern to form a ground lead pattern. The ground lead pattern is configured to electrically connect the electrode pads on overlying and underlying layers together. - As shown in
FIG. 2 ,bumps 23 made of metal are formed on the lead patterns of the circuit pattern disposed on thepackage substrate 21, and the semiconductor chip is mounted on theelectrode pads 28 via thebumps 23. The flip-bonded semiconductor chip allows theelectrode pads 28 to be electrically connected to the lead patterns on thepackage substrate 21 by thebumps 23. - In the semiconductor chip, the electrode pads 28 on the
top surface 22 a of thebody 22 are connected to thesubstrate 21 by thebumps 23, some of which areground bumps 23 a connected to a ground of the substrate. Thebumps 23 formed between thelead patterns 29 of thesubstrate 21 and theelectrode pads 28 of the semiconductor chip are made of gold, copper, aluminum or alloys thereof and serve to connect wires of the substrate with the semiconductor chip. - The
ground bumps 23 a are in direct contact with a conductive via filled with a conductive material in thevia hole 27 and serve to electrically connect theconductive film 25 with the ground. Of course, although the conductive via 27 a is directly connected to thebumps 23, the conductive via 27 a, if electrically connected to theground bumps 23 a on the substrate, may realize this feature of the invention. - In this fashion, the
conductive film 25 formed on theunderside surface 22 b and the side surfaces of thebody 22 of the semiconductor chip is electrically connected to the ground. As a result, electromagnetic wave generated from the semiconductor chip is induced to flow toward the ground, and thus blocked. This accordingly inhibits occurrence of noises. Further, this shields electromagnetic wave induced to the semiconductor chip from outside, thereby suppressing interference from the electromagnetic wave. - To easily form the
conductive film 25 on theunderside surface 22 b and the side surfaces of the semiconductor chip, conductive paint is directly applied on the top surface and side surfaces of the semiconductor chip or sprayed thereonto. -
FIG. 3 a is a perspective view illustrating a semiconductor chip according to an embodiment of the invention. - Referring to
FIG. 3 a, the semiconductor chip has a body provided withelectrode pads 38 on atop surface 32 a thereof where patterns are formed, and ametal film 35 on anunderside surface 32 b thereof. Themetal film 35 has a viahole 37 perforated through thebody 32 of the semiconductor chip. Themetal film 35 is brought in contact with a conductive via 37 a filled with a conductive material in the viahole 37. The viahole 37 is connected to theelectrode pads 38 on thetop surface 32 a of thesemiconductor chip body 32. - The via
hole 37 can be formed by laser processing or dry etching such as reactive ion etch. The viahole 37 may feature various shapes such as a circle, a triangle and a polygon. The viahole 37 may have a uniform cross-section. Alternatively, the viahole 37 may have a cross-section that is greater or smaller in proportion to its proximity to thetop surface 32 a thereof. - The via
hole 37 is filled with a conductive material to form the conductive via 37 a and extended to the electrode pads on thetop surface 32 a of thesemiconductor chip body 32 to electrically connect theconductive film 35 with a ground on the substrate. - The conductive via 37 a can be formed by electroplating and the conductive material adopts all electroplatable metals such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), and tungsten (W).
- Alternatively, the conductive via 37 a may be formed by vacuum evaporation, sputtering, chemical vapor deposition and by filling-up and sintering of a conductive paste. The conductive material for filling the via
hole 37 is exemplified by gold (Au), silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), tungsten (W) and alloys thereof. - To easily form the
conductive film 35 on theunderside surface 32 b of thesemiconductor chip body 32, conductive paint is directly applied to the underside surface of the semiconductor chip body or sprayed thereonto. -
FIG. 3 b is a cross-sectional view illustrating a semiconductor chip package having a semiconductor chip mounted on a substrate. - Referring to
FIG. 3 b, the semiconductor chip is flip-bonded onto thesubstrate 31. - The semiconductor chip has a
body 32 provided with a plurality ofelectrode pads 38 on atop surface 32 a thereof. - A
conductive film 35 is formed on anunderside surface 32 b of thesemiconductor chip body 32 where electrode pads are not formed. Also, a viahole 37 is perforated through thetop surface 32 a and theunderside surface 32 b of thesemiconductor chip body 32. - Further, the
electrode pads 38 on thetop surface 32 a of thesemiconductor chip body 32 are connected to leadpatterns 39 on thesubstrate 31 viabumps 33, some of which are groundbumps 33 a connected to a ground on the substrate. The bumps formed between thelead patterns 39 of thesubstrate 31 and theelectrode pads 38 of the semiconductor chip are made of gold, copper, aluminum or alloys thereof, and serve to connect wires of the substrate with the chip. - The ground bumps 33 a are made in direct contact with the conductive via 37 a filled with a conductive material in the via
hole 37 and serve to electrically connect theconductive film 35 to the ground on the substrate. Of course, although the conductive via 37 a is directly connected to another one of thebumps 33, the conductive via 37 a, if electrically connected to the ground bumps 33 a on the substrate, may realize this feature of the invention. - Although not illustrated, a barrier metal film may be formed to facilitate bonding between the ground bumps 33 a and the conductive via 37 a and prevent cracks from heat accompanied by use of the chip, thereby ensuring reliability of the chip. The barrier metal film may be made of one selected from a group consisting of titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), Ti/TiN and Ta/TaN. The barrier metal film is preferably formed by chemical vapor deposition.
- The via
hole 37 is filled with a conductive material to form the conductive via 37 a and extended to the ground bumps 33 a formed on the electrode pads disposed on thetop surface 32 a of thesemiconductor chip body 32 to electrically connect theconductive film 35 with the ground on the substrate. - In this fashion, the
conductive film 35 formed on theunderside surface 32 b of thesemiconductor chip body 32 is electrically connected to the ground. As a result, electromagnetic wave generated from the semiconductor chip is induced to flow toward the ground, and thus blocked. This accordingly inhibits occurrence of noises. Also, this shields electromagnetic wave induced to the semiconductor chip from the outside, thereby suppressing interference from the electromagnetic wave. - The
conductive film 35 can be formed merely on theunderside surface 32 b of thesemiconductor chip body 32 when individual semiconductor chips are applied with a conductive film material separately from one another. - Here, at least one via hole is perforated through the top surface and underside surface of the
semiconductor chip body 32 and filled with a conductive material. Then a conductive film is formed on the underside surface of the semiconductor chip body to be brought in contact with the conductive material. Theconductive film 35 can be easily formed by directly applying or spraying conductive paint for shielding electromagnetic wave. - Alternatively, in a structure where the conductive film is formed on the underside surface of the semiconductor chip, the via hole and the conductive film are formed on a wafer before being cut into the unit chips, and then cut into the unit chips. This accordingly simplifies a manufacturing method.
-
FIGS. 4 a to 4 d illustrate a manufacturing method in which the semiconductor chip ofFIG. 3 a is fabricated on a wafer. - To fabricate the semiconductor chip having a conductive film therein on the wafer, the wafer is prepared, at least one via hole is formed in each of unit chip areas on the wafer, a conductive material is filled in the via hole, a conductive film is formed on an underside surface of the wafer and the wafer is cut into unit chips.
- Referring to
FIG. 4 a, a via hole is formed on each of the unit chip areas to connect from electrode pads on the top surface of the wafer where patterns and the electrode pads are formed to the underside surface of the wafer.FIG. 4 a is a perspective view in which the underside surface of the wafer faces upward. The viahole 47 is formed by mechanical polishing or laser processing. To realize an aspect of the invention, at least one via hole is necessarily formed on each of the unit chip areas. Here, the via hole is connected to one of the electrode pads disposed around patterns (not illustrated) formed on the top surface of the wafer. That is, the electrode pads are connected to a ground of the substrate. - Referring to
FIG. 4 b, the viahole 47 formed on each of the unit chip areas is filled with a conductive material to form a conductive via 47 a. This allows theconductive film 45 on the underside surface of thesemiconductor chip body 42 to electrically connect to the ground of the substrate. - Referring to
FIG. 4 c, the conductive film is formed on the underside surface of the wafer. Theconductive film 45 can be formed by directly applying or spraying conductive paint for shielding electromagnetic wave. This simplifies a process and saves material costs compared with a case where the conductive film is formed-on each of the unit chips. - Here, the
conductive film 45 is in direct contact with the conductive via 47 a filled with a conductive material in the viahole 47. Preferably, theconductive film 45 is made of the same conductive material filled in the viahole 47. - Referring to
FIG. 4 d, the wafer is cut into each of the unit chips to produce the semiconductor chip according to the invention. Theconductive film 45 is formed on the underside surface of thesemiconductor chip body 42 and brought in contact with the conductive material filled in the viahole 47. Accordingly, the conductive via 47 a connects theconductive film 45 with the ground of the substrate. - Furthermore, optionally a shielding conductive material may be formed on side surfaces of the cut semiconductor chip to boost shielding effects of the conductive film.
- Although not illustrated, the cut semiconductor chip is flip bonded onto the substrate to connect the conductive via to the ground of the substrate, thereby producing the semiconductor chip package according to the invention.
- The embodiments and the accompanying drawings are illustrative only but do not limit the invention. Thus, the conductive film and the via hole can be located variously.
- As set forth above, according to exemplary embodiments of the invention, when a semiconductor chip is mounted on a substrate, a shielding metal film is connected to a ground to boost shielding effects of electromagnetic wave and ensure the chip to be mounted in a minimal volume.
- In addition, the semiconductor chip can be fabricated on a wafer to simplify a manufacturing process.
- While the present invention has been shown and described in connection with the preferred embodiments, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (8)
1. A semiconductor chip comprising:
a body having a top surface where a pattern is formed, an underside surface opposing the top surface and a plurality of side surfaces;
a plurality of electrode pads formed on the top surface of the body to connect to an external terminal;
a shielding conductive film formed on the surfaces excluding the top surface of the body where the pattern is formed; and
a conductive via extending through the body to connect one of the electrode pads with the conductive film.
2. A semiconductor chip according to claim 1 , wherein the electrode pad connected to the conductive via is grounded.
3. A semiconductor chip according to claim 1 , wherein the conductive film is formed only on the underside surface of the body.
4. A semiconductor chip package comprising:
a semiconductor chip including:
a body having a top surface where a pattern is formed, an underside surface opposing the top surface and a plurality of side surfaces;
a plurality of electrode pads formed on the top surface of the body to connect to an external terminal;
a shielding conductive film formed on the surfaces excluding the top surface of the body where the pattern is formed; and
a conductive via extending through the body to connect one of the electrode pads with the conductive film,
a substrate where a ground lead pattern and a plurality of lead patterns are formed; and
a plurality of bumps disposed between the respective electrode pads of the semiconductor chip and the respective lead patterns of the substrate to electrically connect the semiconductor chip with the substrate.
5. The semiconductor chip package according to claim 4 , wherein the electrode pad connected to the via hole is connected to the ground lead pattern of the substrate.
6. The semiconductor chip package according to claim 4 , wherein the conductive film is formed only on the underside surface of the semiconductor chip.
7. A method for manufacturing a semiconductor chip comprising:
forming via holes in a wafer including unit chip areas to connect from an electrode pad on a top surface of a wafer where a pattern is formed to an underside surface of the wafer opposing the top surface so that at least one of the via holes is formed in each of the unit chip areas;
filling the via hole with conductive material;
forming a conductive film on the underside surface of the wafer to contact the conductive material filled in the via hole; and
cutting the wafer into unit chips.
8. The method according to claim 7 , further comprising:
forming a shielding conductive material on a side surface of the cut semiconductor chip.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US12/651,234 US8043896B2 (en) | 2006-05-16 | 2009-12-31 | Semiconductor chip, method of manufacturing the semiconductor chip and semiconductor chip package including an inclined via hole |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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KR10-2006-0043946 | 2006-05-16 | ||
KR1020060043946A KR100691632B1 (en) | 2006-05-16 | 2006-05-16 | Semiconductor chip, method of manufacturing the semiconductor chip and semiconductor chip package |
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US12/651,234 Division US8043896B2 (en) | 2006-05-16 | 2009-12-31 | Semiconductor chip, method of manufacturing the semiconductor chip and semiconductor chip package including an inclined via hole |
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US20070267725A1 true US20070267725A1 (en) | 2007-11-22 |
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US12/651,234 Expired - Fee Related US8043896B2 (en) | 2006-05-16 | 2009-12-31 | Semiconductor chip, method of manufacturing the semiconductor chip and semiconductor chip package including an inclined via hole |
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US12/651,234 Expired - Fee Related US8043896B2 (en) | 2006-05-16 | 2009-12-31 | Semiconductor chip, method of manufacturing the semiconductor chip and semiconductor chip package including an inclined via hole |
Country Status (4)
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US (2) | US20070267725A1 (en) |
JP (2) | JP4512101B2 (en) |
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US10741528B2 (en) | 2018-01-24 | 2020-08-11 | Micron Technology, Inc. | Semiconductor device with an electrically-coupled protection mechanism and associated systems, devices, and methods |
US11114415B2 (en) | 2018-01-24 | 2021-09-07 | Micron Technology, Inc. | Semiconductor device with a layered protection mechanism and associated systems, devices, and methods |
Also Published As
Publication number | Publication date |
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US8043896B2 (en) | 2011-10-25 |
JP5409423B2 (en) | 2014-02-05 |
CN101075594A (en) | 2007-11-21 |
US20100105171A1 (en) | 2010-04-29 |
CN100527399C (en) | 2009-08-12 |
JP2010103574A (en) | 2010-05-06 |
JP2007311754A (en) | 2007-11-29 |
KR100691632B1 (en) | 2007-03-12 |
JP4512101B2 (en) | 2010-07-28 |
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