US20070155076A1 - Method for fabricating saddle type fin transistor - Google Patents
Method for fabricating saddle type fin transistor Download PDFInfo
- Publication number
- US20070155076A1 US20070155076A1 US11/480,198 US48019806A US2007155076A1 US 20070155076 A1 US20070155076 A1 US 20070155076A1 US 48019806 A US48019806 A US 48019806A US 2007155076 A1 US2007155076 A1 US 2007155076A1
- Authority
- US
- United States
- Prior art keywords
- layer
- hard mask
- coating layer
- mask pattern
- saddle type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 title claims abstract description 44
- 239000010410 layer Substances 0.000 claims abstract description 96
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 230000008569 process Effects 0.000 claims abstract description 20
- 229910003481 amorphous carbon Inorganic materials 0.000 claims abstract description 19
- 238000002955 isolation Methods 0.000 claims abstract description 19
- 239000011247 coating layer Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000000576 coating method Methods 0.000 claims abstract description 7
- 239000006117 anti-reflective coating Substances 0.000 claims description 28
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 238000000206 photolithography Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- 230000000694 effects Effects 0.000 description 9
- 230000008859 change Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000001878 scanning electron micrograph Methods 0.000 description 4
- 230000009977 dual effect Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001588 bifunctional effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Definitions
- the present invention relates to a method for fabricating a semiconductor device; and more particularly, to a method for fabricating a saddle type fin transistor having characteristics of a fin transistor and a recess transistor.
- the minimization of such transistors becomes limited.
- the minimized horizontal channels of the transistors may have disadvantages such as a short channel effect and a drain induced barrier lower (DIBL) effect, usually caused by a shortened channel length. If the channel length is decreased to 50 nm or less, process variations increase, resulting in scattered device characteristics. If the channel length is decreased to 30 nm or less, the short channel effect and the DIBL effect become severe, often disabling a normal device operation. Therefore, a dual gate transistor is suggested to overcome the above mentioned disadvantages.
- the dual gate transistor has a structure including channels and gates that surround the channels or are disposed in both sides of the channels.
- the gate electrodes are formed on the horizontal channels.
- an electric field that has an upward/downward unbalance is more likely to be applied to the horizontal channels, and as a result, controlling an on/off operation of the transistors is generally difficult due to the gate electrodes.
- the channel size decreases, the short channel effect becomes pronounced.
- gate electrodes of dual gate transistors having vertical channels are commonly formed in both sides of the thin channels.
- the gate electrodes generally affect the entire channel regions.
- FIG. 1 illustrates a typical fin transistor 10 .
- the fin transistor 10 includes a fin structure where a fin 2 (i.e., an upper portion of a substrate 1 ) is formed between device isolation regions 3 .
- Reference numeral 4 denotes a gate electrode. Both sides of the fin 2 can serve as channels, thereby increasing the channel area. As a result, the short channel effect can be reduced.
- this fin structure is generally limited to increase an effective channel length despite the reduction in a body effect.
- the recess transistor 20 includes a substrate 11 , device isolation regions 13 , a gate insulation layer 12 , and a recess gate electrode 14 .
- the recess transistor 20 has a structure that determines a threshold voltage regardless of the gate length.
- the recess transistor 20 may have a limitation in that the threshold voltage may be lowered. Also, the recess transistor 20 may not be free from the short channel effect like the fin transistor 10 .
- FIG. 3 illustrates cross-sectional views of various types of typical transistors.
- a saddle type fin transistor has a combined structure of the fin transistor and the recess transistor.
- the saddle type fin transistor utilizes the advantages of the recess transistor, and is beneficial to the low threshold voltage and the shortened effective channel length, which often arise when using the fin transistor.
- DRAM dynamic random access memory
- FIG. 4 illustrates a top view of a typical saddle type fin transistor structure.
- FIG. 5 illustrates an enlarged perspective view of a portion ‘A’ illustrated in FIG. 4 .
- FIGS. 6A and 6B illustrate cross-sectional views of the typical saddle type fin transistor cut along lines I-I′ and II-II′ of FIG. 5 , respectively.
- FIGS. 7A to 7 F illustrate perspective views of the typical saddle type fin transistor illustrated in FIG. 5 to describe a method for fabricating the same. Since FIGS. 7A to 7 F show the typical saddle type fin transistor structure including the elements illustrated in FIGS. 4, 5 , 6 A and 6 B, detail description of the illustrated elements in FIGS. 4, 5 and 6 A and 6 B will be omitted for the simplicity.
- a pad oxide layer and a pad nitride layer are formed sequentially on a bulk substrate 110 , which is generally cheaper than a silicon-on-insulator (SOI) substrate.
- a shallow trench isolation (STI) process is performed to form trenches in the substrate 110 .
- a high density plasma layer having a good gap-filling property is formed to fill the trenches.
- a chemical mechanical polishing (CMP) process is performed thereon to planarize the high density layer.
- CMP chemical mechanical polishing
- a device isolation structure 111 defining an active region and a field region is formed.
- a wall oxide layer may be formed on the inner surface of the trenches where the device isolation structure 111 is formed.
- the wall oxide layer is formed using an oxidation treatment, which also rounds the inner surface of the trenches.
- An amorphous carbon layer 112 A, a silicon oxynitride (SiON) layer 112 B and an anti-reflective coating layer 113 are formed sequentially on the above resulting structure.
- a photoresist pattern 114 is formed on the anti-reflective coating layer 113 using a photolithography process.
- the anti-reflective coating layer 113 is a bottom anti-reflective coating layer and, is formed of an organic or inorganic material.
- the amorphous carbon layer 112 A and the SiON layer 112 B serve as a hard mask.
- the anti-reflective coating layer 113 , the SiON layer 112 B and the amorphous carbon layer 112 A are etched using the photoresist pattern 114 as an etch mask to obtain a hard mask pattern 112 including a patterned amorphous carbon layer 112 A′ and a patterned SiON layer 112 B′.
- the photoresist pattern 114 is stripped away.
- the anti-reflective coating layer 113 is also removed.
- the anti-reflective coating layer 113 may remain on the hard mask pattern 112 .
- Reference numeral 113 A denotes the remaining anti-reflective coating layer.
- an etching process is performed using the hard mask pattern 112 as an etch mask to form a saddle type fin 115 .
- the etching process is performed in a condition that an etch selectivity between the substrate 110 (e.g., the silicon substrate) and the device isolation structure 111 is maximum. Due to this condition, the device isolation structure 111 is etched, and the substrate 110 thereafter, or the substrate 110 is etched, and then the device isolation structure 111 .
- Reference numeral 111 A represents a patterned device isolation structure.
- Using the hard mask pattern 112 including the patterned amorphous carbon layer 112 A′ as a fin mask can reduce a critical dimension (CD) of the saddle type fin 115 . As a result, device characteristics can be improved.
- the CD of the saddle type fin 115 can be reduced because the amorphous carbon layer 112 A has a higher etch selectivity to a bottom structure than the photoresist pattern 114 due to material properties of the amorphous carbon layer 112 A.
- the hard mask pattern 112 is removed via an etching process.
- a gate oxidation process is performed to form a gate oxide layer 115 on an exposed portion of the substrate 110 .
- a polysilicon layer 116 and a conductive layer 117 are sequentially formed to cover the saddle type fin 115 .
- the polysilicon layer 116 and the conductive layer 117 function as a gate.
- the conductive layer 117 is formed of a material such as tungsten, tungsten silicide, or a combination thereof.
- the amorphous carbon layer 112 A is used as a hard mask material for forming the saddle type fin 115 .
- the field region and the active region i.e., the device isolation structure 111 and the substrate 110
- those layers for forming the hard mask pattern 112 are formed over the device isolation structure 111 and the substrate 110 with different heights.
- Detail description of this step coverage characteristic of the hard mask pattern 112 comprising amorphous carbon, will be provided in FIG. 8 .
- FIG. 8 illustrates a detail cross-sectional view of a typical saddle type fin transistor structure to describe the hard mask pattern formation.
- a pad nitride layer is removed, the height of a device isolation structure 111 (i.e., the field region) becomes different from that of the substrate 110 (i.e., the active region 103 ).
- an amorphous carbon layer 112 A and a SiON layer 112 B formed thereon also have different heights depending on the position on the active region 103 and the device isolation structure 111 .
- the anti-reflective coating layer 113 is also formed to have a different height because the anti-reflective coating layer 113 flows when a photolithography process is performed to form a photoresist pattern 114 .
- FICD final inspection critical dimension
- FIGS. 9A and 9B illustrate this limitation associated with the regionally different height of an anti-reflective coating layer.
- FIGS. 10A and 10B illustrate a change in FICD of a target structure depending on the height of an anti-reflective coating layer.
- FIG. 10A illustrates a micrographic scanning electron microscopy (SEM) image of a target structure after an etching process for forming a saddle type fin.
- FIG. 10B illustrates a micrographic SEM image of a target structure after an etching process for forming gates.
- Table 1 below provide the exemplary data supporting the change in the FICD of the target structure depending on the height of the anti-reflective coating layer illustrated in FIGS. 10A and 10B .
- the FICD thereof becomes increased.
- a device isolation structure Fox has an increased CD.
- an object of the present invention to provide a method for fabricating a saddle type fin transistor advantageous of improving a device characteristic by reducing an increase of a FICD of a target structure, usually caused by a height difference between an active region and a field region.
- a method for fabricating a saddle type fin transistor including: preparing a substrate where a device isolation structure is already formed; forming a hard mask pattern over the substrate, the hard mask pattern including a coating layer obtained through a coating method; and performing an etching process using the hard mask pattern as an etch mask to form a saddle type fin.
- FIG. 1 illustrates a simplified cross-sectional view of a typical fin transistor
- FIG. 2 illustrates a simplified cross-sectional view of a recess transistor
- FIG. 3 illustrates simplified cross-sectional views of various types of typical transistors
- FIG. 4 illustrates a top view of a typical saddle type fin transistor
- FIG. 5 illustrates an enlarged perspective view of a portion ‘A’ illustrated in FIG. 4 ;
- FIG. 6A illustrates a cross-sectional view of the typical saddle type fin transistor cut along a line I-I′ of FIG. 5 ;
- FIG. 6B illustrates a cross-sectional view of the typical saddle type fin transistor cut along II-II′ of FIG. 5 ;
- FIGS. 7A to 7 F illustrate simplified cross-sectional views of the saddle type fin transistor illustrated in FIG. 5 to describe a method for fabricating the same;
- FIG. 8 illustrates a cross-sectional view of a typical saddle type fin transistor
- FIGS. 9A and 9B are micrographic SEM images illustrating a change in FICD of a typical saddle type fin or gate obtained through the typical fabrication method of the saddle type fin transistor;
- FIGS. 10A and 10B illustrate respective micrographic SEM images of a typical saddle type fin and a gate after corresponding etching processes to show a change in FICD of a typical saddle type fin or gate;
- FIG. 11 illustrates a simplified cross-sectional view of a saddle type fin transistor in accordance with an embodiment of the present invention to illustrate a method for fabricating the same;
- FIGS. 12 and 13 illustrate cross-sectional views of exemplary multi-film hard masks (MFHMs) illustrated in FIG. 11 ;
- FIGS. 14A to 14 C illustrate cross-sectional views of various hard mask structures in accordance with another embodiment of the present invention.
- FIG. 11 illustrates a simplified cross-sectional view of a saddle type fin transistor in accordance with an embodiment of the present invention to illustrate a method for fabricating the same.
- the saddle type fin transistor of FIG. 11 corresponds to that of FIG. 8 .
- the saddle type fin transistor is fabricated using an MFHM layer 212 A as a hard mask according to the embodiment of the present invention.
- the MFHM layer 212 A includes all types of coating layers obtained via any coating method.
- the MFHM layer 212 A can be coated over a target structure, flowing evenly. As a result, the MFHM layer 212 A can be formed with the even height even though a bottom structure has different heights depending on the position.
- the MFHM layer 212 A is formed to a height larger than a height difference between an active region 203 and a field region (i.e., the device isolation structure 211 ).
- the MFHM layer 212 A may include a bifunctional hard mask (BFHM) layer or trifunctional hard mask (TFHM) layer.
- BFHM bifunctional hard mask
- TFHM trifunctional hard mask
- a SiON layer 203 B may also be used as a hard mask.
- the BFHM is formed in a stack structure including a spin on glass (SOG) layer and a hybrid anti-reflective coating (ARC) layer.
- the SOG layer may include a bottom anti-reflective coating (BARC) layer and a high-K dielectric layer.
- the hybrid ARC layer may include a low-K dielectric layer.
- the TFHM has a stack structure including triple hybrid ARC layers.
- a hard mask pattern can be formed in a single layer of MFHM or in a stack structure including an amorphous carbon layer a-C and an MFHM layer.
- the hard mask pattern is formed in the stack structure to obtain a desired level of etch selectivity to the bottom structure when the MFHM layer alone cannot provide a sufficient level of etch selectivity.
- the amorphous carbon layer may cause a height difference, and thus, the amorphous carbon layer is formed thinly.
- the saddle type fin transistor according to the embodied fabrication method can be obtained using substantially the same processes as the typical method illustrated in FIGS. 7A to 7 F, except for the hard mask including the MFHM layer 212 A illustrated in FIG. 11 . Thus, detailed description thereof will be omitted for simplicity.
- the fin etching process is performed using a coating material that can be easily planarized.
- a FICD of a target structure i.e., the saddle type fin or gate
- a short circuit effect or leakage current may not be induced during subsequent processes. Accordingly, a device characteristic can be improved.
Abstract
A method for fabricating a saddle type fin transistor includes: preparing a substrate where a device isolation structure is already formed; forming a hard mask pattern over the substrate, the hard mask pattern including a coating layer obtained through a coating method; and performing an etching process using the hard mask pattern as an etch mask to form a saddle type fin. The hard mask pattern may be formed in a stack structure including an amorphous carbon layer and the coating layer.
Description
- The present invention relates to a method for fabricating a semiconductor device; and more particularly, to a method for fabricating a saddle type fin transistor having characteristics of a fin transistor and a recess transistor.
- Generally, transistors having horizontal channels that are most widely used often have disadvantages associated with a current trend in the large-scale of device minimization and integration. Thus, the minimization of such transistors becomes limited. The minimized horizontal channels of the transistors may have disadvantages such as a short channel effect and a drain induced barrier lower (DIBL) effect, usually caused by a shortened channel length. If the channel length is decreased to 50 nm or less, process variations increase, resulting in scattered device characteristics. If the channel length is decreased to 30 nm or less, the short channel effect and the DIBL effect become severe, often disabling a normal device operation. Therefore, a dual gate transistor is suggested to overcome the above mentioned disadvantages. In general, the dual gate transistor has a structure including channels and gates that surround the channels or are disposed in both sides of the channels.
- For the transistors having the horizontal channels, the gate electrodes are formed on the horizontal channels. Thus, an electric field that has an upward/downward unbalance is more likely to be applied to the horizontal channels, and as a result, controlling an on/off operation of the transistors is generally difficult due to the gate electrodes. As the channel size decreases, the short channel effect becomes pronounced. On the contrary, gate electrodes of dual gate transistors having vertical channels are commonly formed in both sides of the thin channels. Thus, the gate electrodes generally affect the entire channel regions. When the transistors are turned off, a current flow can be controlled between a source and a drain. As a result, power consumption can be reduced, and the on/off operation can be controlled effectively.
- Fin transistors are one example of the transistors having the vertical channels.
FIG. 1 illustrates a typicalfin transistor 10. Thefin transistor 10 includes a fin structure where a fin 2 (i.e., an upper portion of a substrate 1) is formed betweendevice isolation regions 3.Reference numeral 4 denotes a gate electrode. Both sides of thefin 2 can serve as channels, thereby increasing the channel area. As a result, the short channel effect can be reduced. However, this fin structure is generally limited to increase an effective channel length despite the reduction in a body effect. - Another example of the transistors having the vertical channels is a recess transistor 20 (or a trench transistor) illustrated in
FIG. 2 . Therecess transistor 20 includes asubstrate 11,device isolation regions 13, agate insulation layer 12, and arecess gate electrode 14. Different from thefin transistor 10, therecess transistor 20 has a structure that determines a threshold voltage regardless of the gate length. Therecess transistor 20 may have a limitation in that the threshold voltage may be lowered. Also, therecess transistor 20 may not be free from the short channel effect like thefin transistor 10. -
FIG. 3 illustrates cross-sectional views of various types of typical transistors. A saddle type fin transistor has a combined structure of the fin transistor and the recess transistor. The saddle type fin transistor utilizes the advantages of the recess transistor, and is beneficial to the low threshold voltage and the shortened effective channel length, which often arise when using the fin transistor. Thus, in a dynamic random access memory (DRAM), using the saddle type fin transistor is much advantageous in respect of device operation characteristics than using the fin transistor. -
FIG. 4 illustrates a top view of a typical saddle type fin transistor structure.FIG. 5 illustrates an enlarged perspective view of a portion ‘A’ illustrated inFIG. 4 .FIGS. 6A and 6B illustrate cross-sectional views of the typical saddle type fin transistor cut along lines I-I′ and II-II′ ofFIG. 5 , respectively.FIGS. 7A to 7F illustrate perspective views of the typical saddle type fin transistor illustrated inFIG. 5 to describe a method for fabricating the same. SinceFIGS. 7A to 7F show the typical saddle type fin transistor structure including the elements illustrated inFIGS. 4, 5 , 6A and 6B, detail description of the illustrated elements inFIGS. 4, 5 and 6A and 6B will be omitted for the simplicity. - Referring to
FIG. 7A , although not illustrated, a pad oxide layer and a pad nitride layer are formed sequentially on abulk substrate 110, which is generally cheaper than a silicon-on-insulator (SOI) substrate. A shallow trench isolation (STI) process is performed to form trenches in thesubstrate 110. - A high density plasma layer having a good gap-filling property is formed to fill the trenches. A chemical mechanical polishing (CMP) process is performed thereon to planarize the high density layer. As a result, a
device isolation structure 111 defining an active region and a field region is formed. A wall oxide layer may be formed on the inner surface of the trenches where thedevice isolation structure 111 is formed. The wall oxide layer is formed using an oxidation treatment, which also rounds the inner surface of the trenches. - An
amorphous carbon layer 112A, a silicon oxynitride (SiON)layer 112B and ananti-reflective coating layer 113 are formed sequentially on the above resulting structure. Aphotoresist pattern 114 is formed on theanti-reflective coating layer 113 using a photolithography process. Theanti-reflective coating layer 113 is a bottom anti-reflective coating layer and, is formed of an organic or inorganic material. Theamorphous carbon layer 112A and theSiON layer 112B serve as a hard mask. - Referring to
FIG. 7B , theanti-reflective coating layer 113, theSiON layer 112B and theamorphous carbon layer 112A are etched using thephotoresist pattern 114 as an etch mask to obtain a hard mask pattern 112 including a patternedamorphous carbon layer 112A′ and a patternedSiON layer 112B′. Thephotoresist pattern 114 is stripped away. At this time, theanti-reflective coating layer 113 is also removed. However, as illustrated, theanti-reflective coating layer 113 may remain on the hard mask pattern 112.Reference numeral 113A denotes the remaining anti-reflective coating layer. The formation of the above described hard mask pattern 112 will be described inFIG. 8 in detail. - Referring to
FIG. 7C , an etching process is performed using the hard mask pattern 112 as an etch mask to form asaddle type fin 115. The etching process is performed in a condition that an etch selectivity between the substrate 110 (e.g., the silicon substrate) and thedevice isolation structure 111 is maximum. Due to this condition, thedevice isolation structure 111 is etched, and thesubstrate 110 thereafter, or thesubstrate 110 is etched, and then thedevice isolation structure 111.Reference numeral 111A represents a patterned device isolation structure. Using the hard mask pattern 112 including the patternedamorphous carbon layer 112A′ as a fin mask can reduce a critical dimension (CD) of thesaddle type fin 115. As a result, device characteristics can be improved. The CD of thesaddle type fin 115 can be reduced because theamorphous carbon layer 112A has a higher etch selectivity to a bottom structure than thephotoresist pattern 114 due to material properties of theamorphous carbon layer 112A. - Referring to
FIG. 7D , the hard mask pattern 112 is removed via an etching process. Referring toFIG. 7E , a gate oxidation process is performed to form agate oxide layer 115 on an exposed portion of thesubstrate 110. Referring toFIG. 7F , apolysilicon layer 116 and aconductive layer 117 are sequentially formed to cover thesaddle type fin 115. Thepolysilicon layer 116 and theconductive layer 117 function as a gate. Theconductive layer 117 is formed of a material such as tungsten, tungsten silicide, or a combination thereof. - As described above, the
amorphous carbon layer 112A is used as a hard mask material for forming thesaddle type fin 115. Thus, when the field region and the active region (i.e., thedevice isolation structure 111 and the substrate 110) have different heights, those layers for forming the hard mask pattern 112 are formed over thedevice isolation structure 111 and thesubstrate 110 with different heights. Detail description of this step coverage characteristic of the hard mask pattern 112 comprising amorphous carbon, will be provided inFIG. 8 . -
FIG. 8 illustrates a detail cross-sectional view of a typical saddle type fin transistor structure to describe the hard mask pattern formation. When a pad nitride layer is removed, the height of a device isolation structure 111 (i.e., the field region) becomes different from that of the substrate 110 (i.e., the active region 103). Thus, anamorphous carbon layer 112A and aSiON layer 112B formed thereon also have different heights depending on the position on theactive region 103 and thedevice isolation structure 111. As a result, theanti-reflective coating layer 113 is also formed to have a different height because theanti-reflective coating layer 113 flows when a photolithography process is performed to form aphotoresist pattern 114. When theanti-reflective coating layer 113 having a regionally different height is etched, a final inspection critical dimension (FICD) of a target structure becomes different depending on the height of theanti-reflective coating layer 113.Reference numeral 102 represents the aforementioned wall oxide layer. -
FIGS. 9A and 9B illustrate this limitation associated with the regionally different height of an anti-reflective coating layer.FIGS. 10A and 10B illustrate a change in FICD of a target structure depending on the height of an anti-reflective coating layer. Particularly,FIG. 10A illustrates a micrographic scanning electron microscopy (SEM) image of a target structure after an etching process for forming a saddle type fin.FIG. 10B illustrates a micrographic SEM image of a target structure after an etching process for forming gates. Table 1 below provide the exemplary data supporting the change in the FICD of the target structure depending on the height of the anti-reflective coating layer illustrated inFIGS. 10A and 10B .TABLE 1 S-fin (Saddle type): Split: FIG. 10B Height of anti-reflective 250 Å 450 Å coating layer FICD 52 nm 76 nm - As the saddle type fin (S-fin) has a large height difference, the FICD thereof becomes increased. As a result, as illustrated in
FIG. 10B , a device isolation structure Fox has an increased CD. Thus, it may be difficult to achieve an overlap between the device isolation structure Fox and the corresponding gate Gate. This difficulty may result in generation of bridges between the gates, or leakage current during formation of contacts, thereby degrading device characteristics. - It is, therefore, an object of the present invention to provide a method for fabricating a saddle type fin transistor advantageous of improving a device characteristic by reducing an increase of a FICD of a target structure, usually caused by a height difference between an active region and a field region.
- In accordance with an aspect of the present invention, there is provided a method for fabricating a saddle type fin transistor, including: preparing a substrate where a device isolation structure is already formed; forming a hard mask pattern over the substrate, the hard mask pattern including a coating layer obtained through a coating method; and performing an etching process using the hard mask pattern as an etch mask to form a saddle type fin.
- The above and other objects and features of the present invention will become better understood with respect to the following description of the exemplary embodiments given in conjunction with the accompanying drawings, in which:
-
FIG. 1 illustrates a simplified cross-sectional view of a typical fin transistor; -
FIG. 2 illustrates a simplified cross-sectional view of a recess transistor; -
FIG. 3 illustrates simplified cross-sectional views of various types of typical transistors; -
FIG. 4 illustrates a top view of a typical saddle type fin transistor; -
FIG. 5 illustrates an enlarged perspective view of a portion ‘A’ illustrated inFIG. 4 ; -
FIG. 6A illustrates a cross-sectional view of the typical saddle type fin transistor cut along a line I-I′ ofFIG. 5 ; -
FIG. 6B illustrates a cross-sectional view of the typical saddle type fin transistor cut along II-II′ ofFIG. 5 ; -
FIGS. 7A to 7F illustrate simplified cross-sectional views of the saddle type fin transistor illustrated inFIG. 5 to describe a method for fabricating the same; -
FIG. 8 illustrates a cross-sectional view of a typical saddle type fin transistor; -
FIGS. 9A and 9B are micrographic SEM images illustrating a change in FICD of a typical saddle type fin or gate obtained through the typical fabrication method of the saddle type fin transistor; -
FIGS. 10A and 10B illustrate respective micrographic SEM images of a typical saddle type fin and a gate after corresponding etching processes to show a change in FICD of a typical saddle type fin or gate; -
FIG. 11 illustrates a simplified cross-sectional view of a saddle type fin transistor in accordance with an embodiment of the present invention to illustrate a method for fabricating the same; -
FIGS. 12 and 13 illustrate cross-sectional views of exemplary multi-film hard masks (MFHMs) illustrated inFIG. 11 ; and -
FIGS. 14A to 14C illustrate cross-sectional views of various hard mask structures in accordance with another embodiment of the present invention. - A method for fabricating a saddle type fin transistor in accordance with exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. If it is stated that a layer is formed “on” another layer or on a substrate, it should be construed that the layer is formed directly on the other layer or on the substrate, or a third layer may be interposed therebetween. Also, like reference numerals denote like elements even in different drawings.
-
FIG. 11 illustrates a simplified cross-sectional view of a saddle type fin transistor in accordance with an embodiment of the present invention to illustrate a method for fabricating the same. The saddle type fin transistor ofFIG. 11 corresponds to that ofFIG. 8 . - Instead of using the
amorphous carbon layer 112A as a hard mask pattern (refer toFIG. 8 ), the saddle type fin transistor is fabricated using anMFHM layer 212A as a hard mask according to the embodiment of the present invention. Different from a typical deposition method for the amorphous carbon layer, theMFHM layer 212A includes all types of coating layers obtained via any coating method. TheMFHM layer 212A can be coated over a target structure, flowing evenly. As a result, theMFHM layer 212A can be formed with the even height even though a bottom structure has different heights depending on the position. For the even height of theMFHM layer 212A (i.e., theplanarized MFHM layer 212A), theMFHM layer 212A is formed to a height larger than a height difference between an active region 203 and a field region (i.e., the device isolation structure 211). TheMFHM layer 212A may include a bifunctional hard mask (BFHM) layer or trifunctional hard mask (TFHM) layer. A SiON layer 203B may also be used as a hard mask. - As illustrated in
FIGS. 12 and 13 , the BFHM is formed in a stack structure including a spin on glass (SOG) layer and a hybrid anti-reflective coating (ARC) layer. The SOG layer may include a bottom anti-reflective coating (BARC) layer and a high-K dielectric layer. The hybrid ARC layer may include a low-K dielectric layer. The TFHM has a stack structure including triple hybrid ARC layers. - As illustrated in
FIGS. 14A to 14C, a hard mask pattern can be formed in a single layer of MFHM or in a stack structure including an amorphous carbon layer a-C and an MFHM layer. The hard mask pattern is formed in the stack structure to obtain a desired level of etch selectivity to the bottom structure when the MFHM layer alone cannot provide a sufficient level of etch selectivity. In such a case, the amorphous carbon layer may cause a height difference, and thus, the amorphous carbon layer is formed thinly. - The saddle type fin transistor according to the embodied fabrication method can be obtained using substantially the same processes as the typical method illustrated in
FIGS. 7A to 7F, except for the hard mask including theMFHM layer 212A illustrated inFIG. 11 . Thus, detailed description thereof will be omitted for simplicity. - According to the embodiments of the present invention, the fin etching process is performed using a coating material that can be easily planarized. Thus, a FICD of a target structure (i.e., the saddle type fin or gate) is less likely to increase, and as a result, a short circuit effect or leakage current may not be induced during subsequent processes. Accordingly, a device characteristic can be improved.
- The present application contains subject matter related to the Korean patent application No. KR 2005-133846, filed in the Korean Patent Office on Dec. 29, 2005, the entire contents of which being incorporated herein by reference.
- While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.
Claims (10)
1. A method for fabricating a saddle type fin transistor, comprising:
preparing a substrate where a device isolation structure is already formed;
forming a hard mask pattern over the substrate, the hard mask pattern including a coating layer obtained through a coating method; and
performing an etching process using the hard mask pattern as an etch mask to form a saddle type fin.
2. The method of claim 1 , wherein the hard mask pattern is formed in a stack structure including an amorphous carbon layer and the coating layer.
3. The method of claim 2 , wherein the amorphous carbon layer is formed over the coating layer.
4. The method of claim 2 , wherein the amorphous carbon layer is formed underneath the coating layer.
5. The method of claim 3 , wherein the coating layer includes an anti-reflective coating layer.
6. The method of claim 4 , wherein the coating layer includes an anti-reflective coating layer.
7. The method of claim 5 , wherein the coating layer is formed to a height larger than a height difference created beneath the hard mask pattern.
8. The method of claim 6 , wherein the coating layer is formed to a height larger than a height difference created beneath the hard mask pattern.
9. The method of claim 7 , wherein the forming of the hard mask pattern comprises:
forming a silicon oxynitride (SiON) layer over the hard mask pattern;
coating an anti-reflective coating layer over the SiON layer;
forming a photoresist pattern over the anti-reflective coating layer; and
performing a photolithography process on the photoresist pattern to sequentially etch the anti-reflective coating layer, the SiON layer and the hard mask pattern.
10. The method of claim 8 , wherein the forming of the hard mask pattern comprises:
forming a silicon oxynitride (SiON) layer over the hard mask pattern;
coating an anti-reflective coating layer over the SiON layer;
forming a photoresist pattern over the anti-reflective coating layer; and
performing a photolithography process on the photoresist pattern to sequentially etch the anti-reflective coating layer, the SiON layer and the hard mask pattern.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/574,634 US7846844B2 (en) | 2005-12-29 | 2009-10-06 | Method for fabricating saddle type fin transistor |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020050133846A KR100726150B1 (en) | 2005-12-29 | 2005-12-29 | Method for manufacturing saddle type fin transistor |
KR2005-0133846 | 2005-12-29 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/574,634 Division US7846844B2 (en) | 2005-12-29 | 2009-10-06 | Method for fabricating saddle type fin transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
US20070155076A1 true US20070155076A1 (en) | 2007-07-05 |
Family
ID=38224972
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/480,198 Abandoned US20070155076A1 (en) | 2005-12-29 | 2006-06-29 | Method for fabricating saddle type fin transistor |
US12/574,634 Active US7846844B2 (en) | 2005-12-29 | 2009-10-06 | Method for fabricating saddle type fin transistor |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/574,634 Active US7846844B2 (en) | 2005-12-29 | 2009-10-06 | Method for fabricating saddle type fin transistor |
Country Status (2)
Country | Link |
---|---|
US (2) | US20070155076A1 (en) |
KR (1) | KR100726150B1 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080227281A1 (en) * | 2007-03-15 | 2008-09-18 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device with recess gate |
US20080280444A1 (en) * | 2007-05-11 | 2008-11-13 | Hynix Semiconductor Inc. | Method of forming micro pattern of semiconductor device |
US20100184259A1 (en) * | 2007-06-27 | 2010-07-22 | Radigan Steven J | Method for fabricating a 3-d integrated circuit using a hard mask of silicon-oxynitride on amorphous carbon |
US20110284969A1 (en) * | 2010-05-19 | 2011-11-24 | Elpida Memory, Inc. | Semiconductor device, method of forming semiconductor device, and data processing system |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100979359B1 (en) * | 2008-05-30 | 2010-08-31 | 주식회사 하이닉스반도체 | Method of fabricating semiconductor apparatus having saddle-fin transistor and semiconductor apparatus fabricated thereby |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6211061B1 (en) * | 1999-10-29 | 2001-04-03 | Taiwan Semiconductor Manufactuirng Company | Dual damascene process for carbon-based low-K materials |
US6326300B1 (en) * | 1998-09-21 | 2001-12-04 | Taiwan Semiconductor Manufacturing Company | Dual damascene patterned conductor layer formation method |
US20030003756A1 (en) * | 2001-06-28 | 2003-01-02 | Hynix Semiconductor | Method for forming contact by using arf lithography |
US20040009633A1 (en) * | 2002-07-09 | 2004-01-15 | Abbott Todd R. | Method of using high-k dielectric materials to reduce soft errors in sram memory cells, and a device comprising same |
US20040203238A1 (en) * | 2003-03-19 | 2004-10-14 | Hans-Peter Moll | Process for producing an etching mask on a microstructure, in particular a semiconductor structure with trench capacitors, and corresponding use of the etching mask |
US20050214694A1 (en) * | 2003-12-13 | 2005-09-29 | Samsung Electronics Co., Ltd. | Pattern formation method |
US6956256B2 (en) * | 2003-03-04 | 2005-10-18 | Micron Technology Inc. | Vertical gain cell |
US20070032086A1 (en) * | 2003-05-19 | 2007-02-08 | Yukiko Furukawa | Mehtod of manufacturing an electronic device |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100673223B1 (en) * | 2002-07-16 | 2007-01-22 | 주식회사 하이닉스반도체 | Method for forming gate line of flash memory device |
KR100555518B1 (en) * | 2003-09-16 | 2006-03-03 | 삼성전자주식회사 | Double gate field effect transistor and manufacturing method for the same |
KR20050055978A (en) | 2003-12-09 | 2005-06-14 | 삼성전자주식회사 | Fin field effect transistors and methods of forming the same |
KR100689211B1 (en) * | 2004-12-11 | 2007-03-08 | 경북대학교 산학협력단 | Saddle type MOS device |
-
2005
- 2005-12-29 KR KR1020050133846A patent/KR100726150B1/en not_active IP Right Cessation
-
2006
- 2006-06-29 US US11/480,198 patent/US20070155076A1/en not_active Abandoned
-
2009
- 2009-10-06 US US12/574,634 patent/US7846844B2/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6326300B1 (en) * | 1998-09-21 | 2001-12-04 | Taiwan Semiconductor Manufacturing Company | Dual damascene patterned conductor layer formation method |
US6211061B1 (en) * | 1999-10-29 | 2001-04-03 | Taiwan Semiconductor Manufactuirng Company | Dual damascene process for carbon-based low-K materials |
US20030003756A1 (en) * | 2001-06-28 | 2003-01-02 | Hynix Semiconductor | Method for forming contact by using arf lithography |
US20040009633A1 (en) * | 2002-07-09 | 2004-01-15 | Abbott Todd R. | Method of using high-k dielectric materials to reduce soft errors in sram memory cells, and a device comprising same |
US6956256B2 (en) * | 2003-03-04 | 2005-10-18 | Micron Technology Inc. | Vertical gain cell |
US20040203238A1 (en) * | 2003-03-19 | 2004-10-14 | Hans-Peter Moll | Process for producing an etching mask on a microstructure, in particular a semiconductor structure with trench capacitors, and corresponding use of the etching mask |
US20070032086A1 (en) * | 2003-05-19 | 2007-02-08 | Yukiko Furukawa | Mehtod of manufacturing an electronic device |
US20050214694A1 (en) * | 2003-12-13 | 2005-09-29 | Samsung Electronics Co., Ltd. | Pattern formation method |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080227281A1 (en) * | 2007-03-15 | 2008-09-18 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device with recess gate |
US7759234B2 (en) * | 2007-03-15 | 2010-07-20 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device with recess gate |
US20080280444A1 (en) * | 2007-05-11 | 2008-11-13 | Hynix Semiconductor Inc. | Method of forming micro pattern of semiconductor device |
US7981803B2 (en) * | 2007-05-11 | 2011-07-19 | Hynix Semiconductor Inc. | Method of forming micro pattern of semiconductor device |
US20100184259A1 (en) * | 2007-06-27 | 2010-07-22 | Radigan Steven J | Method for fabricating a 3-d integrated circuit using a hard mask of silicon-oxynitride on amorphous carbon |
US7994068B2 (en) * | 2007-06-27 | 2011-08-09 | Sandisk 3D Llc | Method for fabricating a 3-D integrated circuit using a hard mask of silicon-oxynitride on amorphous carbon |
US20110284969A1 (en) * | 2010-05-19 | 2011-11-24 | Elpida Memory, Inc. | Semiconductor device, method of forming semiconductor device, and data processing system |
US8624333B2 (en) * | 2010-05-19 | 2014-01-07 | Nan Wu | Semiconductor device, method of forming semiconductor device, and data processing system |
Also Published As
Publication number | Publication date |
---|---|
US20100055616A1 (en) | 2010-03-04 |
US7846844B2 (en) | 2010-12-07 |
KR100726150B1 (en) | 2007-06-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7871914B2 (en) | Methods of fabricating semiconductor devices with enlarged recessed gate electrodes | |
US7358142B2 (en) | Method for forming a FinFET by a damascene process | |
KR100515061B1 (en) | Semiconductor devices having a fin field effect transistor and methods for forming the same | |
US7501674B2 (en) | Semiconductor device having fin transistor and planar transistor and associated methods of manufacture | |
US7619281B2 (en) | Semiconductor device having buried gate line and method of fabricating the same | |
US20030211703A1 (en) | Methods of fabricating integrated circuit devices having trench isolation structures | |
US8823091B2 (en) | Semiconductor device having saddle fin transistor and manufacturing method of the same | |
JP5073157B2 (en) | Semiconductor device | |
JP2006339621A (en) | Method for fabricating semiconductor device | |
US7846844B2 (en) | Method for fabricating saddle type fin transistor | |
US20080029810A1 (en) | Methods of fabricating semiconductor devices having buried gates and related semiconductor devices | |
US6680511B2 (en) | Integrated circuit devices providing improved short prevention | |
JPH11284148A (en) | Semiconductor device and manufacture of the same | |
US8928040B2 (en) | Semiconductor device including line-type active region and method for manufacturing the same | |
KR101024771B1 (en) | Semiconductor having buried wordline and method for manufacturing the same | |
US6995452B2 (en) | MOSFET device with nanoscale channel and method of manufacturing the same | |
US8803224B2 (en) | MOS transistor suppressing short channel effect and method of fabricating the same | |
KR100586553B1 (en) | Gate of semiconductor device and method thereof | |
US7407880B2 (en) | Semiconductor device and manufacturing process therefore | |
US20070004188A1 (en) | Method for fabricating semiconductor device | |
KR100961195B1 (en) | Method for manufacturing transistor in semiconductor device | |
KR20070070921A (en) | Method for manufacturing saddle type fin transistor | |
KR20010046916A (en) | Method for fabricating of semiconductor device | |
KR19990057861A (en) | Method for preventing leakage current at the edge of field oxide film |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: HYNIX SEMICONDUCTOR INC., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KIM, KWANG-OK;REEL/FRAME:018030/0727 Effective date: 20060614 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |