US20070109030A1 - Phase-Locked Loop Integrated Circuits Having Fast Phase Locking Characteristics - Google Patents
Phase-Locked Loop Integrated Circuits Having Fast Phase Locking Characteristics Download PDFInfo
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- US20070109030A1 US20070109030A1 US11/623,437 US62343707A US2007109030A1 US 20070109030 A1 US20070109030 A1 US 20070109030A1 US 62343707 A US62343707 A US 62343707A US 2007109030 A1 US2007109030 A1 US 2007109030A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
- B01D—SEPARATION
- B01D39/00—Filtering material for liquid or gaseous fluids
- B01D39/08—Filter cloth, i.e. woven, knitted or interlaced material
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
- B01D—SEPARATION
- B01D46/00—Filters or filtering processes specially modified for separating dispersed particles from gases or vapours
- B01D46/02—Particle separators, e.g. dust precipitators, having hollow filters made of flexible material
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
- H03L7/1075—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
- B01D—SEPARATION
- B01D2258/00—Sources of waste gases
- B01D2258/02—Other waste gases
- B01D2258/0258—Other waste gases from painting equipments or paint drying installations
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S331/00—Oscillators
- Y10S331/02—Phase locked loop having lock indicating or detecting means
Definitions
- the present invention relates to integrated circuit devices and, more particularly, to integrated circuit devices that utilize phase detectors when generating periodic signals.
- a conventional PLL integrated circuit 10 may include a phase detector 12 , a charge pump 14 , a loop filter 16 , a voltage controlled oscillator (VCO) 18 , a clock decoder and buffer 20 , and a frequency divider 22 .
- the phase detector 12 may be configured to generate UP and DOWN control signals in response to a reference clock signal (CKREF) and a feedback clock signal (CKVCO).
- CKREF reference clock signal
- CKVCO feedback clock signal
- the phase detector 12 may be configured to compare the phases of the clock signals and generate an active UP signal or an active DOWN signal when the feedback clock signal CKVCO lags or leads the reference clock signal CKREF.
- the reference clock signal (CKREF) may be a buffered version of an external clock signal (not shown) that is received by an integrated circuit chip.
- the charge pump 14 may be operative to convert the digitally encoded UP and DOWN control signals into an analog output (POUT) that sources current to or sinks current from the loop filter 16 .
- the loop filter 16 is illustrated as generating a control voltage (Vcontrol), which is provided as an input to the VCO 18 .
- the VCO 18 may generate a plurality of outputs, which are provided to the clock decoder and buffer 20 .
- One of the outputs of the clock decoder and buffer 20 (shown as clock signal ( ⁇ 1 ) may be provided as an input to the frequency divider 22 , which generates the feedback clock signal CKVCO.
- An active UP signal operates to increase the value of Vcontrol, which speeds up the VCO 18 and causes the feedback clock signal CKVCO to catch up with the reference clock signal CKREF.
- an active DOWN signal slows down the VCO 18 and eliminates the phase lead of the feedback clock signal CKVCO.
- FIG. 2 illustrates a conventional charge pump 14 having both pull-up and pull-down sections.
- the pull-up section includes an NMOS pull-down transistor N 1 in series with a resistor R 1 .
- a pull-up current mirror is provided by PMOS transistors P 1 and P 2 .
- the NMOS pull-down transistor N 1 is responsive to the UP control signal. When the UP control signal is active at a logic 1 level, the NMOS pull-down transistor N 1 turns on and pulls-down the drain and gate of PMOS transistor P 1 .
- the feedback signal line NMOS_ON is also switched high-to-low. This causes both PMOS transistors P 1 and P 2 to turn on and provide a sourcing current (I source ) to the output terminal (POUT) of the charge pump 14 .
- the pull-down section includes a PMOS pull-up transistor P 3 in series with a resistor R 2 .
- a pull-down current mirror is provided by NMOS transistors N 2 and N 3 .
- the gate of the PMOS pull-up transistor P 3 is connected to an output of an inverter I 1 , which receives the DOWN control signal.
- the PMOS pull-up transistor P 3 turns on and pulls-up the drain and gate of NMOS transistor N 2 .
- the feedback signal line PMOS_ON is also switched low-to-high. This causes both NMOS transistors N 2 and N 3 to turn on and withdraw a sinking current (I sink ) from the output terminal POUT.
- FIG. 3 illustrates a conventional phase detector 12 that utilizes a delay device D 1 to provide a dead zone compensation time interval during which both the UP and DOWN control signals are temporarily active. Maintaining the UP and DOWN control signals at active levels during an overlapping time interval prevents a “dead zone” from occurring when the phases of the reference clock signal CKREF and the feedback clock signal CKVCO are so closely aligned that the generation of any active UP control signal would otherwise be immediately canceled by the generation of any active DOWN control signal and vice versa.
- CKREF the reference clock signal
- CKVCO feedback clock signal
- the delay device D 1 may also be referred to as an “anti-backlash” delay unit.
- the phase detector 12 is illustrated as including a pair of D-type flip-flops (DFF 1 and DFF 2 ), a NAND gate ND 1 , an inverter I 2 and a delay device D 1 .
- the D-type flip-flops are synchronized with the reference and feedback clock signals CKREF and CKVCO.
- This low-to-high switching at the output of inverter I 2 is delayed by a fixed time amount equal to T 1 , by the delay device D 1 .
- the delay T 1 may be about 5 nanoseconds in some cases.
- the reset signal RST at the output of the delay device D 1 will switch low-to-high some time after the output of the inverter I 2 switches low-to-high in response to simultaneously active UP and DOWN control signals.
- the UP and DOWN control signals Upon reset, the UP and DOWN control signals will switch to inactive levels and the output POUT of the charge pump 14 of FIG. 2 will be disposed in a high impedance state.
- another conventional PLL integrated circuit 10 ′ includes a phase detector 12 ′, a charge pump 14 ′, a loop filter 16 ′, a voltage controlled oscillator (VCO) 18 ′ and a second frequency divider 22 ′, which is configured to divide a frequency of an output clock signal CLKOUT by N, where N is a positive integer.
- VCO voltage controlled oscillator
- FIG. 4 the loop filter 16 ′ is illustrated as including a parallel combination of an RC network (resistor R and capacitor C 2 ) and a capacitor C 1 .
- This PLL 50 may be used having a faster phase lock time.
- This PLL 50 is similar to the PLL 10 ′ of FIG. 4 , however, a register 17 and a digital-to-analog converter (DAC) 19 are provided.
- the register 17 stores a digital signal ds received from an external source and the DAC 19 coverts the stored digital signal ds into an analog signal that is applied internally to the loop filter 16 ′.
- This application of the analog signal operates to reduce the lock-time of the PLL 50 , but requires an accurate generation of the digital signal ds, which can be complicated by process and temperature variations associated with the operation of a memory device containing the PLL 50 .
- Embodiments of the present invention include a phase-locked loop (PLL) integrated circuit with accelerated phase locking characteristics.
- PLL integrated circuits include a voltage-controlled oscillator and a loop filter having first and second input terminals and an output terminal coupled to an input of the voltage-controlled oscillator.
- a charge pump and a phase-lock accelerator are also provided.
- the charge pump is configured to drive the first input terminal of the loop filter with a pump output signal and the phase-lock accelerator is configured to drive the second input terminal of the loop filter with an analog output signal.
- the phase-lock accelerator is responsive to a reference clock signal and a feedback clock signal.
- the loop filter may include at least one capacitor having a first electrode electrically coupled to the first input terminal of the loop filter and a second electrode electrically coupled to the second input terminal of the loop filter.
- the first electrode of the capacitor may also be electrically connected to the input of the voltage-controlled oscillator.
- the PLL integrated circuit also includes a first phase detector, which is configured to generate a first pair of output signals (PUP, PDN) in response to the reference clock signal and the feedback clock signal.
- the phase-lock accelerator may include a second phase detector configured to generate a second pair of output signals (FUP, FDN) in response to the reference clock signal and the feedback clock signal and digital-to-analog converter configured to generate the analog output signal in response to the second pair of output signals.
- This analog output signal operates to influence a voltage of an internal node within the loop filter and thereby adjust an amount charge required to be pumped into the loop filter by the charge pump in order to achieve a locking condition within the PLL.
- inventions of the invention may also include a frequency divider configured to generate the feedback clock signal in response to a clock signal generated at an output of the voltage-controlled oscillator.
- a frequency divider configured to generate the feedback clock signal in response to a clock signal generated at an output of the voltage-controlled oscillator.
- a first frequency divider may be provided that is configured to generate the reference clock signal in response to an input clock signal; and a second frequency divider may be provided that is configured to generate the feedback clock signal in response to a clock signal generated at an output of the voltage-controlled oscillator.
- FIG. 1 is a block diagram of a first phase-locked loop integrated circuit according to the prior art.
- FIG. 2 is an electrical schematic of a conventional charge pump that may be used in the phase-locked loop integrated circuit of FIG. 1 .
- FIG. 3 is an electrical schematic of a conventional phase detector that may be used in the phase-locked loop integrated circuit of FIG. 1 .
- FIG. 4 is a block diagram of a second phase-locked loop integrated circuit according to the prior art.
- FIG. 5 is a block diagram of a third phase-locked loop integrated circuit according to the prior art.
- FIG. 6A is a block diagram of a phase-locked loop integrated circuit according to an embodiment of the present invention.
- FIG. 6B is a block diagram of a phase-locked loop integrated circuit according to an embodiment of the present invention.
- FIG. 6C is a block diagram of phase-locked loop integrated circuit according to an embodiment of the present invention.
- FIG. 7A is an electrical schematic of a phase detector circuit that may be used in the phase-locked loop integrated circuits of FIGS. 6A-6C .
- FIG. 7B is an electrical schematic of a phase detector circuit that may be used in the phase-locked loop integrated circuits of FIGS. 6A-6C .
- a phase-locked loop (PLL) integrated circuit 60 includes a voltage-controlled oscillator (VCO) 18 ′ and a loop filter 35 having first and second input terminals and an output terminal coupled to an input of the voltage-controlled oscillator 18 ′.
- the first and second input terminals are shown as nodes 33 and 34 of the loop filter 35 , which includes a resistor R and a pair of capacitors C 1 and C 2 , connected as illustrated.
- a charge pump 14 ′ is also provided, which is configured to drive the first input terminal (e.g., node 33 ) of the loop filter 35 with a pump output signal POUT.
- the PLL integrated circuit 60 also includes a phase-lock accelerator 37 , which is configured to drive the second input terminal (e.g., node 34 ) of the loop filter 35 with an analog output signal, in response a reference clock signal CKREF and a feedback clock signal CKFBK.
- the reference clock signal CKREF may be generated by a first frequency divider 11 , which is a divide-by-M frequency divider responsive to an input clock signal CLKIN.
- the feedback clock signal CKFBK may be generated by a second frequency divider 22 ′, which is a divide-by-N frequency divider responsive to a clock signal CLKOUT generated by the voltage-controlled oscillator 18 ′.
- the phase-lock accelerator 37 has a pair of inputs that are coupled to a pair of inputs of a first phase detector 31 A.
- the first phase detector 31 A is configured to generate a first pair of output signals PUP and PDN in response to the reference clock signal CKREF and the feedback clock signal CKFBK.
- the phase-lock accelerator 37 includes a second phase detector 31 B and a digital-to-analog converter 32 that generates the analog output signal.
- Embodiments of a phase detector circuit 31 that may be used to perform the operations of the first and second phase detectors 31 A and 31 B of FIG. 6A are illustrated by FIGS. 7A-7B .
- the loop filter 35 includes a series RC network containing a resistor R and a capacitor C 2 in parallel with a capacitor C 1 having a first electrode connected to the first input terminal 33 (and the input of the voltage-controlled oscillator 18 ′) and a second electrode connected to the second input terminal 34 , which receives the analog voltage generated by the digital-to-analog converter 32 .
- the PLL integrated circuits 60 ′ and 60 ′′ of FIGS. 6B and 6C are similar to the PLL integrated circuit of FIG. 6A , however, the loop filters 45 and 55 in FIGS. 6B and 6C are different than the loop filter 35 in FIG. 6A .
- the RC network containing resistor R and capacitor C 2 in the loop filter 45 of FIG. 6B is not directly connected to the second input terminal (i.e., node 44 ) or the output of the digital-to-analog converter 32 .
- the capacitor C 1 includes a first electrode connected to the first input terminal (i.e., node 53 ) and a second electrode connected to the second input terminal (i.e., node 44 ).
- an electrode of the capacitor C 2 in the RC network containing resistor R and capacitor C 2 is directly connected to the second input terminal (i.e., node 54 ) and the output of the digital-to-analog converter 32 .
- the first electrode of the capacitor C 1 is connected to the first input terminal 53 and a terminal of the resistor R within the RC network.
- FIGS. 7A-7B Two embodiments of a phase detector circuit are illustrated by FIGS. 7A-7B .
- a phase detector circuit 31 is illustrated as including a first phase detector 31 A and a second phase detector 31 B.
- the second phase detector 31 B is illustrated as including third and fourth D-type flip-flops (DFF 3 , DFF 4 ), which are responsive to the true outputs of the first phase detector 31 A.
- the third and fourth D-type flip-flops DDF 3 and DFF 4 are also responsive to a reset signal RST.
- the true output Q of the third D-type flip-flop DDF 3 i.e., signal FUP
- the true output Q of the third D-type flip-flop DDF 3 i.e., signal FUP
- the true output Q of the fourth D-type flip-flop DDF 4 (i.e., signal FDN) will be set to a logic 1 level when the true output Q of the second D-type flip-flop is high at a logic 1 level and a leading edge of the feedback clock signal CKFBK is received.
- the phase detector circuit 31 ′ of FIG. 7B is illustrated as including first and second D-type flip-flops (DFF 1 , DFF 2 ) and a reset circuit, which is responsive to the true outputs Q of the first and second flip-flops DFF 1 and DFF 2 and also responsive to the complementary outputs /Q of the third and fourth flip-flips DFF 3 and DFF 4 .
- These complementary outputs /Q develop the signals FUPb and FDNb, which are provided as inputs to respective delay elements DL 1 and DL 2 within the reset circuit.
- the reset circuit also includes three AND gates (A 1 , A 2 and A 3 ), connected as illustrated.
- the true outputs Q of the first and second flip-flops DFF 1 and DFF 2 are connected to the output terminals PUP and PDN of the first phase detector 31 A.
- the second phase detector within the phase detector circuit 31 ′ is illustrated as including third and fourth D-type flip-flops (DFF 3 , DFF 4 ), which are responsive to the true outputs of the first phase detector and a reset signal RST.
Abstract
A phase-locked loop (PLL) integrated circuit includes a voltage-controlled oscillator and a loop filter having first and second input terminals and an output terminal coupled to an input of the voltage-controlled oscillator. A charge pump and a phase-lock accelerator are provided. The charge pump is configured to drive the first input terminal of the loop filter with a pump output signal and the phase-lock accelerator is configured to drive the second input terminal of the loop filter with an analog output signal. The phase-lock accelerator is responsive to a reference clock signal and a feedback clock signal.
Description
- This application is a continuation of U.S. application Ser. No. 11/068,127, filed Feb. 28, 2005, which claims priority to Korean Application No. 2004-28629, filed Apr. 26, 2004. The disclosure of U.S. application Ser. No. 11/068,127 is hereby incorporated herein by reference.
- The present invention relates to integrated circuit devices and, more particularly, to integrated circuit devices that utilize phase detectors when generating periodic signals.
- Phase-locked loop (PLL) integrated circuits are frequently used to generate highly accurate internal clock signals on an integrated circuit substrate. As illustrated by
FIG. 1 , a conventional PLL integratedcircuit 10 may include aphase detector 12, acharge pump 14, aloop filter 16, a voltage controlled oscillator (VCO) 18, a clock decoder andbuffer 20, and afrequency divider 22. Thephase detector 12 may be configured to generate UP and DOWN control signals in response to a reference clock signal (CKREF) and a feedback clock signal (CKVCO). In particular, thephase detector 12 may be configured to compare the phases of the clock signals and generate an active UP signal or an active DOWN signal when the feedback clock signal CKVCO lags or leads the reference clock signal CKREF. As will be understood by those skilled in the art, the reference clock signal (CKREF) may be a buffered version of an external clock signal (not shown) that is received by an integrated circuit chip. Thecharge pump 14 may be operative to convert the digitally encoded UP and DOWN control signals into an analog output (POUT) that sources current to or sinks current from theloop filter 16. Theloop filter 16 is illustrated as generating a control voltage (Vcontrol), which is provided as an input to theVCO 18. The VCO 18 may generate a plurality of outputs, which are provided to the clock decoder andbuffer 20. One of the outputs of the clock decoder and buffer 20 (shown as clock signal (φ1) may be provided as an input to thefrequency divider 22, which generates the feedback clock signal CKVCO. An active UP signal operates to increase the value of Vcontrol, which speeds up theVCO 18 and causes the feedback clock signal CKVCO to catch up with the reference clock signal CKREF. On the other hand, an active DOWN signal slows down theVCO 18 and eliminates the phase lead of the feedback clock signal CKVCO. These and other aspects of thePLL 10 ofFIG. 1 are more fully illustrated and described at section 9.5.2 of a textbook by Jan M. Rabaey, entitled Digital Integrated Circuits: A Design Perspective, Prentice-Hall, ISBN 0-13-178609-1, pp. 540-542. -
FIG. 2 illustrates aconventional charge pump 14 having both pull-up and pull-down sections. The pull-up section includes an NMOS pull-down transistor N1 in series with a resistor R1. A pull-up current mirror is provided by PMOS transistors P1 and P2. The NMOS pull-down transistor N1 is responsive to the UP control signal. When the UP control signal is active at alogic 1 level, the NMOS pull-down transistor N1 turns on and pulls-down the drain and gate of PMOS transistor P1. The feedback signal line NMOS_ON is also switched high-to-low. This causes both PMOS transistors P1 and P2 to turn on and provide a sourcing current (Isource) to the output terminal (POUT) of thecharge pump 14. The pull-down section includes a PMOS pull-up transistor P3 in series with a resistor R2. A pull-down current mirror is provided by NMOS transistors N2 and N3. The gate of the PMOS pull-up transistor P3 is connected to an output of an inverter I1, which receives the DOWN control signal. When the DOWN control signal is active at alogic 1 level, the PMOS pull-up transistor P3 turns on and pulls-up the drain and gate of NMOS transistor N2. The feedback signal line PMOS_ON is also switched low-to-high. This causes both NMOS transistors N2 and N3 to turn on and withdraw a sinking current (Isink) from the output terminal POUT. When the control signals UP and DOWN are both active atlogic 1 levels, the pull-up and pull-down sections are simultaneously active. The pull-up and pull-down sections of the charge pump may be balanced so that Isource equals Isink and no net current is provided to or withdrawn from the output terminal POUT. A similar charge pump is illustrated atFIG. 4 of commonly assigned U.S. Pat. No. 6,430,244 to Rhu, entitled “Digital Phase-Locked Loop Apparatus With Enhanced Phase Error Compensating Circuit,” the disclosure of which is hereby incorporated by reference. -
FIG. 3 illustrates aconventional phase detector 12 that utilizes a delay device D1 to provide a dead zone compensation time interval during which both the UP and DOWN control signals are temporarily active. Maintaining the UP and DOWN control signals at active levels during an overlapping time interval prevents a “dead zone” from occurring when the phases of the reference clock signal CKREF and the feedback clock signal CKVCO are so closely aligned that the generation of any active UP control signal would otherwise be immediately canceled by the generation of any active DOWN control signal and vice versa. As described in U.S. Pat. No. 4,322,643 to Prescar and U.S. Pat. No. 6,192,094 to Herrmann et al., and in an article by X. Zhang entitled “Analysis and Verification on Side Effect of Anti-Backlash Delay in Phase-Frequency Detector,” Microwave Theory and Techniques Society (MTT-S) Digest, IEEE International Microwave Symposium, pp. 17-20, June 8-13 (2003), the delay device D1 may also be referred to as an “anti-backlash” delay unit. Thephase detector 12 is illustrated as including a pair of D-type flip-flops (DFF1 and DFF2), a NAND gate ND1, an inverter I2 and a delay device D1. The D-type flip-flops are synchronized with the reference and feedback clock signals CKREF and CKVCO. A rising edge of the reference clock signal CKREF will cause the true output Q1 of DFF1 to switch high and a rising edge of the feedback clock signal CKVCO will cause the true output Q2 of DFF2 to switch high. To prevent dead zone operation, the UP and DOWN control signals remain active whenever a rising edge of the reference clock signal CKREF is registered (by DFF1) while the DOWN control signal is active or whenever a rising edge of the feedback clock signal CKVCO is registered (by DFF2) while the UP control signal is active. Setting the UP and DOWN control signals tologic 1 levels causes the output of the NAND gate ND1 to switch high-to-low and the output of the inverter I2 to switch low-to-high. This low-to-high switching at the output of inverter I2 is delayed by a fixed time amount equal to T1, by the delay device D1. The delay T1 may be about 5 nanoseconds in some cases. The reset signal RST at the output of the delay device D1 will switch low-to-high some time after the output of the inverter I2 switches low-to-high in response to simultaneously active UP and DOWN control signals. When active, the reset signal RST operates to reset the flip-flops DFF1 and DFF2 (Q1=Q2=0). Upon reset, the UP and DOWN control signals will switch to inactive levels and the output POUT of thecharge pump 14 ofFIG. 2 will be disposed in a high impedance state. - As illustrated by
FIG. 4 , another conventional PLL integratedcircuit 10′ includes aphase detector 12′, acharge pump 14′, aloop filter 16′, a voltage controlled oscillator (VCO) 18′ and asecond frequency divider 22′, which is configured to divide a frequency of an output clock signal CLKOUT by N, where N is a positive integer. These elements ofFIG. 4 are similar to the corresponding elements shown inFIGS. 1-3 . Moreover, theloop filter 16′ is illustrated as including a parallel combination of an RC network (resistor R and capacitor C2) and a capacitor C1. The reference clock signal (CKREF) is also shown as being generated by afirst frequency divider 11, which is configured to divide a frequency of an applied input clock signal CLKIN by M, where M is a positive integer. Unfortunately, because the phase lock time of the PLL integratedcircuit 10′ ofFIG. 4 is influenced by the amount of capacitance in theloop filter 16′, a relatively large capacitance in theloop filter 16′ may prevent the PLL from being used in high frequency memory devices operating at dual and higher data rates. To address this lock time deficiency, delay-locked loops (DLLs) have frequently be used as substitutes for PLLs in high frequency applications. Alternatively, a modified PLL, such as the PLL 50 ofFIG. 5 , may be used having a faster phase lock time. ThisPLL 50 is similar to thePLL 10′ ofFIG. 4 , however, aregister 17 and a digital-to-analog converter (DAC) 19 are provided. Theregister 17 stores a digital signal ds received from an external source and theDAC 19 coverts the stored digital signal ds into an analog signal that is applied internally to theloop filter 16′. This application of the analog signal operates to reduce the lock-time of thePLL 50, but requires an accurate generation of the digital signal ds, which can be complicated by process and temperature variations associated with the operation of a memory device containing thePLL 50. - Embodiments of the present invention include a phase-locked loop (PLL) integrated circuit with accelerated phase locking characteristics. Some of these PLL integrated circuits include a voltage-controlled oscillator and a loop filter having first and second input terminals and an output terminal coupled to an input of the voltage-controlled oscillator. A charge pump and a phase-lock accelerator are also provided. The charge pump is configured to drive the first input terminal of the loop filter with a pump output signal and the phase-lock accelerator is configured to drive the second input terminal of the loop filter with an analog output signal. The phase-lock accelerator is responsive to a reference clock signal and a feedback clock signal. In some of these embodiments, the loop filter may include at least one capacitor having a first electrode electrically coupled to the first input terminal of the loop filter and a second electrode electrically coupled to the second input terminal of the loop filter. The first electrode of the capacitor may also be electrically connected to the input of the voltage-controlled oscillator.
- The PLL integrated circuit also includes a first phase detector, which is configured to generate a first pair of output signals (PUP, PDN) in response to the reference clock signal and the feedback clock signal. In addition, the phase-lock accelerator may include a second phase detector configured to generate a second pair of output signals (FUP, FDN) in response to the reference clock signal and the feedback clock signal and digital-to-analog converter configured to generate the analog output signal in response to the second pair of output signals. This analog output signal operates to influence a voltage of an internal node within the loop filter and thereby adjust an amount charge required to be pumped into the loop filter by the charge pump in order to achieve a locking condition within the PLL.
- These embodiments of the invention may also include a frequency divider configured to generate the feedback clock signal in response to a clock signal generated at an output of the voltage-controlled oscillator. In particular, a first frequency divider may be provided that is configured to generate the reference clock signal in response to an input clock signal; and a second frequency divider may be provided that is configured to generate the feedback clock signal in response to a clock signal generated at an output of the voltage-controlled oscillator.
-
FIG. 1 is a block diagram of a first phase-locked loop integrated circuit according to the prior art. -
FIG. 2 is an electrical schematic of a conventional charge pump that may be used in the phase-locked loop integrated circuit ofFIG. 1 . -
FIG. 3 is an electrical schematic of a conventional phase detector that may be used in the phase-locked loop integrated circuit ofFIG. 1 . -
FIG. 4 is a block diagram of a second phase-locked loop integrated circuit according to the prior art. -
FIG. 5 is a block diagram of a third phase-locked loop integrated circuit according to the prior art. -
FIG. 6A is a block diagram of a phase-locked loop integrated circuit according to an embodiment of the present invention. -
FIG. 6B is a block diagram of a phase-locked loop integrated circuit according to an embodiment of the present invention. -
FIG. 6C is a block diagram of phase-locked loop integrated circuit according to an embodiment of the present invention. -
FIG. 7A is an electrical schematic of a phase detector circuit that may be used in the phase-locked loop integrated circuits ofFIGS. 6A-6C . -
FIG. 7B is an electrical schematic of a phase detector circuit that may be used in the phase-locked loop integrated circuits ofFIGS. 6A-6C . - The present invention now will be described more fully herein with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout and signal lines and signals thereon may be referred to by the same reference characters. Signals may also be synchronized and/or undergo minor boolean operations (e.g., inversion) without being considered different signals. The suffix B (or prefix symbol “/”) to a signal name may also denote a complementary data or information signal or an active low control signal, for example.
- Referring now to
FIG. 6A , a phase-locked loop (PLL) integratedcircuit 60 according to an embodiment of the invention includes a voltage-controlled oscillator (VCO) 18′ and aloop filter 35 having first and second input terminals and an output terminal coupled to an input of the voltage-controlledoscillator 18′. The first and second input terminals are shown asnodes loop filter 35, which includes a resistor R and a pair of capacitors C1 and C2, connected as illustrated. Acharge pump 14′ is also provided, which is configured to drive the first input terminal (e.g., node 33) of theloop filter 35 with a pump output signal POUT. - The PLL
integrated circuit 60 also includes a phase-lock accelerator 37, which is configured to drive the second input terminal (e.g., node 34) of theloop filter 35 with an analog output signal, in response a reference clock signal CKREF and a feedback clock signal CKFBK. The reference clock signal CKREF may be generated by afirst frequency divider 11, which is a divide-by-M frequency divider responsive to an input clock signal CLKIN. The feedback clock signal CKFBK may be generated by asecond frequency divider 22′, which is a divide-by-N frequency divider responsive to a clock signal CLKOUT generated by the voltage-controlledoscillator 18′. The phase-lock accelerator 37 has a pair of inputs that are coupled to a pair of inputs of afirst phase detector 31A. Thefirst phase detector 31A is configured to generate a first pair of output signals PUP and PDN in response to the reference clock signal CKREF and the feedback clock signal CKFBK. The phase-lock accelerator 37 includes asecond phase detector 31B and a digital-to-analog converter 32 that generates the analog output signal. Embodiments of aphase detector circuit 31 that may be used to perform the operations of the first andsecond phase detectors FIG. 6A are illustrated byFIGS. 7A-7B . - The
loop filter 35 includes a series RC network containing a resistor R and a capacitor C2 in parallel with a capacitor C1 having a first electrode connected to the first input terminal 33 (and the input of the voltage-controlledoscillator 18′) and a second electrode connected to thesecond input terminal 34, which receives the analog voltage generated by the digital-to-analog converter 32. - The PLL
integrated circuits 60′ and 60″ ofFIGS. 6B and 6C are similar to the PLL integrated circuit ofFIG. 6A , however, the loop filters 45 and 55 inFIGS. 6B and 6C are different than theloop filter 35 inFIG. 6A . In particular, the RC network containing resistor R and capacitor C2 in theloop filter 45 ofFIG. 6B is not directly connected to the second input terminal (i.e., node 44) or the output of the digital-to-analog converter 32. However, the capacitor C1 includes a first electrode connected to the first input terminal (i.e., node 53) and a second electrode connected to the second input terminal (i.e., node 44). In contrast, in theloop filter 55 ofFIG. 6C , an electrode of the capacitor C2 in the RC network containing resistor R and capacitor C2 is directly connected to the second input terminal (i.e., node 54) and the output of the digital-to-analog converter 32. In addition, the first electrode of the capacitor C1 is connected to thefirst input terminal 53 and a terminal of the resistor R within the RC network. - Two embodiments of a phase detector circuit are illustrated by
FIGS. 7A-7B . InFIG. 7A , aphase detector circuit 31 is illustrated as including afirst phase detector 31A and asecond phase detector 31B. Thefirst phase detector 31A is illustrated as including first and second D-type flip-flops (DFF1, DFF2) and an AND logic gate which operates to reset these flip-flops when the true outputs Q of these flip-flops are both set tologic 1 levels (i.e., PUP=PDN=1). These true outputs Q of the first and second flip-flops are connected to the output terminals PUP and PDN of thefirst phase detector 31A. Thesecond phase detector 31B is illustrated as including third and fourth D-type flip-flops (DFF3, DFF4), which are responsive to the true outputs of thefirst phase detector 31A. The third and fourth D-type flip-flops DDF3 and DFF4 are also responsive to a reset signal RST. As will be understood by those skilled in the art, the true output Q of the third D-type flip-flop DDF3 (i.e., signal FUP) will be set to alogic 1 level when the true output Q of the first D-type flip-flop is high at alogic 1 level and a leading edge of the reference clock signal CKREF is received. Similarly, the true output Q of the fourth D-type flip-flop DDF4 (i.e., signal FDN) will be set to alogic 1 level when the true output Q of the second D-type flip-flop is high at alogic 1 level and a leading edge of the feedback clock signal CKFBK is received. Once these third and fourth flip-flops have both been set (i.e., FUP=FDN=1), the value of the analog output voltage generated by the digital-to-analog converter 32 will cease to vary until such time as these flip-flips are reset and a new phase locking adjustment is performed. - The
phase detector circuit 31′ ofFIG. 7B is illustrated as including first and second D-type flip-flops (DFF1, DFF2) and a reset circuit, which is responsive to the true outputs Q of the first and second flip-flops DFF1 and DFF2 and also responsive to the complementary outputs /Q of the third and fourth flip-flips DFF3 and DFF4. These complementary outputs /Q develop the signals FUPb and FDNb, which are provided as inputs to respective delay elements DL1 and DL2 within the reset circuit. The reset circuit also includes three AND gates (A1, A2 and A3), connected as illustrated. The true outputs Q of the first and second flip-flops DFF1 and DFF2 are connected to the output terminals PUP and PDN of thefirst phase detector 31A. The second phase detector within thephase detector circuit 31′ is illustrated as including third and fourth D-type flip-flops (DFF3, DFF4), which are responsive to the true outputs of the first phase detector and a reset signal RST. - In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.
Claims (4)
1. A phase-locked loop (PLL) integrated circuit, comprising:
a voltage-controlled oscillator;
a loop filter having first and second input terminals and an output terminal coupled to an input of said voltage-controlled oscillator;
a charge pump configured to drive the first input terminal of said loop filter with a pump output signal; and
a phase-lock accelerator configured to drive the second input terminal of said loop filter with an analog output signal, in response to a reference clock signal and a feedback clock signal.
2. The PLL integrated circuit of claim 1 , wherein said loop filter comprises a capacitor having a first electrode electrically coupled to the first input terminal of said loop filter and a second electrode electrically coupled to the second input terminal of said loop filter.
3. The PLL integrated circuit of claim 2 , wherein the first electrode of the capacitor is electrically connected to the input of said voltage-controlled oscillator.
4. The PLL integrated circuit of claim 1 , further comprising a first phase detector configured to generate a first pair of output signals in response to the reference clock signal and the feedback clock signal.
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US11/623,437 US20070109030A1 (en) | 2004-04-26 | 2007-01-16 | Phase-Locked Loop Integrated Circuits Having Fast Phase Locking Characteristics |
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Also Published As
Publication number | Publication date |
---|---|
TWI305448B (en) | 2009-01-11 |
KR20050103367A (en) | 2005-10-31 |
KR100574980B1 (en) | 2006-05-02 |
US20050237120A1 (en) | 2005-10-27 |
TW200611494A (en) | 2006-04-01 |
JP2005318599A (en) | 2005-11-10 |
US7176763B2 (en) | 2007-02-13 |
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