US20060282604A1 - Methods and apparatus for processing graphics data using multiple processing circuits - Google Patents
Methods and apparatus for processing graphics data using multiple processing circuits Download PDFInfo
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- US20060282604A1 US20060282604A1 US11/139,733 US13973305A US2006282604A1 US 20060282604 A1 US20060282604 A1 US 20060282604A1 US 13973305 A US13973305 A US 13973305A US 2006282604 A1 US2006282604 A1 US 2006282604A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/363—Graphics controllers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2200/00—Indexing scheme for image data processing or generation, in general
- G06T2200/28—Indexing scheme for image data processing or generation, in general involving image processing hardware
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2210/00—Indexing scheme for image generation or computer graphics
- G06T2210/52—Parallel processing
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Abstract
Methods and apparatus for providing multiple graphics processing capacity, while utilizing unused integrated graphics processing circuitry on a bridge circuit along with an external or discrete graphics processing unit is disclosed. In particular, a bridge circuit includes an integrated graphics processing circuit configured to process graphics jobs. The bridge circuit also includes an interface operable according to interface with a discrete graphics processing circuit. A controller is included with the bridge circuit and responsive whenever the discrete graphics processing circuit is coupled to the interface to cause the integrated graphics processing circuit to process a task of the graphics job in conjunction with operation of the discrete graphics processing circuit that is operable to process another task of the graphics job. Corresponding methods are also disclosed.
Description
- The present disclosure relates to methods and apparatus for processing video graphics data using multiple processors and, more particularly, to processing video graphics data using a combination of integrated graphics processing circuitry and discrete graphics processing circuitry.
- In typical computer architectures, video graphics data that is to be processed from an application running on a processor, for example, may either be processed by integrated or discrete graphics processing circuitry. Integrated graphics processing circuitry is typically circuitry integrated in a bridge circuit connected to the processor system bus, otherwise known as a “Northbridge.” Discrete processing circuitry is typically an external graphics processing unit that connects to the Northbridge via an interconnect utilizing an interconnect standard such as AGP, PCI, or PCI Express. In order to further increase the processing resources for video graphics processing, it is also known to utilize one or more discrete graphics processing units working in parallel, all of which are connected to the Northbridge via standard interconnects.
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FIG. 1 illustrates a typical computer architecture known in the art utilizing this type of parallel processing. As shown, amain processor 102, such as a CPU or any other processing device is connected to abridge circuit 104 via asystem bus 106. As shown, thebridge circuit 104, which may be a Northbridge, includes an integratedgraphics processing circuitry 108, which may be used for video graphics processing if an external graphics processing unit is not connected to thebridge circuit 104. An example of a known Northbridge circuit utilizing an integrated graphics processing circuitry is ATI's Mobility Radeon® 9100 IGP integrated graphics processor sold by ATI Technologies, Inc. of Markham, Ontario, Canada. - The architecture of
FIG. 1 also illustrates at least two external or discretegraphics processing units bridge circuit 104 viarespective interconnects interconnects graphics processing units bridge circuit 104. This is shown, for example, by dashedline connection 117, whereinterconnect 116 would not be present (also indicated by the dashing line 116). - Currently when an add-in card, such as
GPU 110 is plugged into an AGP, PCI or PCI Express slot connected to the Northbridgecircuit 104, theprocessing circuitry 108 in the Northbridge 104 is not utilized and only the external graphics processing unit, such asGPU 110 is used to perform processing of graphics data. Accordingly, the resources of the integratedgraphics processing circuitry 108 are usually not utilized and, thus, wasted. - Moreover, as discussed previously, it is known to employ parallel processors, such as GPU 110 and GPU 112 in order to increase the processing capacity and band width of the system 100 in order to deliver processed video and graphics to display
media 118, which may include one or more monitors, PDA displays, cell phone displays or printers. Although the utilization of multiple graphics processing units (e.g., 110, 112) increases the system processing capacity, existingprocessing circuitry 108, as mentioned above, cannot be applied to the same graphics job, and potentially is unused when one or more external or discrete processing units are connected to the Northbridgecircuit 104. It is noted that a graphics job, for purposes of this application, refers to a number of tasks, such as graphics processing or display operations, that are performed in conjunction to produce a display. For example, a graphics job could include multiple tasks such as vertex processing, 3D rendering, and driving the display that are performed in conjunction with one another to produce a display. -
FIG. 1 illustrates an example of a conventional computer system architecture including integrated graphics processing as well as discrete graphics processing. -
FIG. 2 illustrates a computer architecture according to an example of the present disclosure. -
FIG. 3 illustrates a flow diagram of a method for achieving multiple graphics processing according to an example of the present disclosure. - The present disclosure relates to methods and apparatus for providing multiple graphics processing capacity, while utilizing unused integrated graphics processing circuitry on a bridge circuit along with an external or discrete graphics processing unit. In particular, a bridge circuit includes an integrated graphics processing circuit configured to process graphics data. The bridge circuit also includes an interface operable according to a standard to interface with a discrete graphics processing circuit. A controller, which may be implemented with hardware, firmware or software, is also included and configured to detect when the external graphics processing circuit is connected to the interface and to cause the integrated graphics processing circuit to process at least a portion of the graphics data in conjunction with operation of the discrete graphics processing circuit, which processes another portion of the graphics data. The portions of the data are each associated with respective processing functions.
- It is noted that the terms “processing graphics data” or “to process graphics data” (or similar terms related to processing graphics data) may be tasks performed in a graphics job, as defined previously, and may include tasks performing calculations. Also included in these terms (i.e., processing graphics data, etc.) is the displaying of graphics data, whether or not displaying necessarily requires calculations.
- By using the internal graphics processing circuitry of a Northbridge circuit as one of the graphics controllers in a dual graphics controller architecture, the previously unutilized circuitry of the Northbridge is utilized, thus reducing the need for further external or discrete graphics processing units, thereby reducing system cost. Moreover, because graphics tasks are split between the external and internal graphics processing units, less memory can be provided with the external graphics processing unit, which can greatly reduce the system cost. For example, if the system is configured such that the internal graphics processing unit handles real time clients, which require careful control over latency and memory usage, the external graphics processing unit can be delegated to handle computationally intensive, latency insensitive, or low memory bandwidth tasks.
- Additionally, by using the integrated graphics of the Northbridge, fewer external interfaces are required on the Northbridge circuit, further reducing the cost of the system. Moreover, in a system utilizing PCI Express, in particular, the downstream load over the PCI Express bus is potentially reduced in contrast to a dual discrete graphics processing system due to the above mentioned reduction in link bandwidth. That is, the integrated graphics processing circuitry is performing some of the graphics processing tasks, which were previously performed by a discrete graphics processing unit, the external graphics processing circuit will not require as much interconnect bandwidth and therefore will not need to utilize as many PCI Express lanes in the interface. Thus, a less expensive component can be built to perform these tasks.
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FIG. 2 illustrates an example of anarchitecture 200 according to the present disclosure.Architecture 200 includes aprocessor 202 such as a central processing unit or any other processor. The processor is connected to abridge circuit 204, which is typically a Northbridge via asystem bus 206. Similar to the conventional system illustrated inFIG. 1 , the Northbridge 204 inFIG. 2 includes an integratedgraphics processing circuitry 208 configured to process video graphics data, such as data received from an application running on theprocessor 202. Additionally, the circuit includes a main externalgraphics processing unit 210 connected to the Northbridge 204 with astandard interface 212, such as AGP, PCI or PCI Express. For purposes of the disclosed examples,interface 212 will be assumed to operate according to PCI Express. - Typically, the main GPU drives
external display media 214, which may include one or more monitors, cell phone or PDA displays, or printers. It is noted that, an alternate connection from the Northbridgecircuit 204 to thedisplay media 214 may be utilized for display of data processed bycircuitry 208 as indicated by dashed lined 216. - In order to maintain operation of integrated graphics processing circuitry, such as
circuitry 208, when an external or discrete graphics processing unit is connected to the Northbridge 204, thebridge circuit 204 includes acontroller 218, which may, or may not, have synchronization capabilities. 218 may be a set of independent data paths. 218 may be implemented as software, firmware, or hardware. In particular,controller 218 is used to ensure theprocessing circuitry 208 remains functional when anexternal GPU 210 is connected to aninterface 219, which may be a PCI Express Interface, connecting the Northbridge 204 to theexternal GPU 210. More particularly,controller 218 may establish separate data paths for the integratedgraphics processing circuitry 208 and thediscrete graphics processor 210 for each to independently access at least one of the system processing circuitry (e.g, CPU 202) and the system memory (e.g., memory 220). This independent access ensures that the graphics processing circuitry may remain enabled and capable of processing data when theexternal GPU 210 is connected. Therefore both GPUs (208 and 210) may be cooperatively used to process graphics information for the graphics job. - Additionally, processing and frame buffer control, which may be performed either in
controller 218, as shown, or processingcircuitry 208, or in software, is used to direct which tasks each of thedifferent processing circuitries display media 214. This affords thesystem 200 the capability of off-loading processing from the external GPU to theprocessing circuitry 208 on the Northbridge 204. -
FIG. 3 illustrates a flow diagram of an operational aspect of thesystem 200. The flow diagram 300 begin at aninitialization block 302. Next, a discrete graphics processor is connected to thebridge 204 as illustrated inblock 304. It is noted that this initialization may also include detection of the discrete graphics processor (e.g., processor 210) to thebridge 204. This detection may be performed either by software running withinprocessing circuitry 208 of the Northbridge 204 or by software run by thecentral processing unit 202 directing the Northbridge with information passed via thesystem bus 206. Additionally, one of ordinary skill in the art will appreciate that thecontroller 218 may receive an acknowledgement of this detection. - Once the detection information is received by the
controller 218, the control of the integratedgraphics processing circuitry 208 ensures that thecircuitry 208 is not disabled according to conventional operation, but is kept active, or in the case where the system is booting up, initialization and enablement of thecircuitry 208 is performed. This part of the process is illustrated inblock 306. The flow then proceeds to block 308 where parallel graphics processing (i.e., processing performed in conjunction) is performed using both theintegrated processing circuit 208 and thediscrete processing circuitry 210. After this operation, flow continues as illustrated inblock 310. It is noted that the operation inblock 308 ofFIG. 3 is a continuous, on-going operation performed as long as parallel graphics processing is being effected. - The particular methods in which the
frame buffer controller 218, or the software driver, direct processing of video graphics data received from an application are varied and numerous. According to one example, thecontroller 218 or the driver may divide processing tasks betweencircuitry 208 andcircuitry 210. For example, the types of tasks may be divided where the integratedgraphics processing circuitry 208 performs calculating vertexes, whereas the discretegraphics processing unit 210 performs rendering. In yet another example, tasks such as the 2D engine and 3D engine may be divided between thecircuitry graphics processing unit 210. Although these examples are given, the different tasks allocated between multiple processors, and the methods of dividing or allocating tasks between the integrated circuitry and discrete circuitry are not limited to these and may include any other suitable methods that may be contemplated by those skilled in the art. - Further, it is contemplated that the processing tasks may be allocated by the
synchronization controller 218 based on determining the currently available processing resources of theintegrated circuitry 208 andexternal circuitry 210. For example, typical integrated graphics processing circuitry has less capacity and performance than discrete graphics processors. Accordingly, tasks which do not have high performance requirements, such as 2D rendering, could be given preference for processing by the integrated graphics whereas 3D processing would be performed by thediscrete graphics processor 210. In the case where the discrete graphics has limited memory resources, tasks with considerable memory needs could be given preference for processing by the integrated graphics processor, whereas tasks that require less memory resources are given to the discrete graphics processor. Additionally, the utilization ofPCI Express bus 212 may be optimized by performing processing tasks with the integratedgraphics processing circuit 208 that may be simply “pass through” themain graphics processor 210 without any further processing, thus minimizing the utilization of thePCI Express bus 212 as information is sent from theprocessing circuitry 208 to theexternal processor 210 to be displayed by thedisplay media 214. Alternatively, processed video graphics data may be sent directly from theprocessing circuitry 208 via an interface on the Northbridge and aconnection 216 to thedisplay media 214 in order reduce utilization of resources of thePCI Express bus 212. - As mentioned previously, the disclosed methods and apparatus afford cost reduction by utilizing extant processing resources typically found on a Northbridge circuit, which previously were wasted when an external graphics processing unit was connected to the Northbridge. Additionally, the number of external interfaces from the
bridge circuit 204 is reduced as only one external or discretegraphics processing circuit 210 is utilized, while providing multiple, parallel graphics processing, as illustrated in the example ofFIG. 2 . - A further feature of the presently disclosed methods and apparatus is that the dividing of the full range of tasks for the graphics job between the internal and external graphics processing units affords the graphics subsystem the ability to tune the processing to utilize the available resources for maximum efficiency. The various tasks for each graphics job are distributed to the graphics processing units that can process them while using the least amount of system resources in the least amount of time. An example of this optimization is PCI Express. Since PCI Express requires equal numbers of downstream and upstream circuits, circuits may not be dynamically allocated from upstream to downstream data transmission. Thus, by performing certain processing tasks which require many bytes of system memory for each byte of data produced with the integrated graphics processing circuitry, less transmission from the Northbridge to the external graphics processor will be required.
- It will be recognized that all or some of the disclosed operations may be useful as applied to printers or other devices. For example, the disclosed processor, circuits or graphic processor(s) may process information and/or output information in any suitable color space including but not limited to Y,U,V, RGB, YPbPr or CMYK (cyan, magenta, yellow, black) color spaces. Suitable considerations should be taken into account when converting from RGB to CMYK or vice versa or between any two color spaces. For example, as is known, the ink type, paper type, brightness settings, and other factors should be considered in converting from or to RGB space and CMYK space as a color displayed on a display screen may be different from that output by a color printing operation.
- The CMYK color space relates particularly to subtractive color technologies, where adding more color takes a pixel or dot closer to black, just as RGB relates to additive color technologies (where adding more color takes a pixel or dot closer to white). As such, if desired, pixel information, or dot color information, may be processed and/or output for any suitable display medium including electronic display screens or for printers on display medium such as paper, film or any other suitable article.
- The above-detailed description of the examples has been presented for the purposes of illustration and description and not by limitation. It is therefore contemplated that the present application covers any additional modifications, variations or equivalents that fall within the spirit and scope of the basic underlying principles disclosed above and the appended claims.
Claims (11)
1. A method comprising:
coupling discrete graphics processing configured to process graphics data with a bridge circuit having integrated graphics processing; and
processing at least a portion of the graphics data with the integrated graphics processing in the bridge circuit and processing at least another portion of the data with the discrete graphics processor unit, the portions of the data being associated with respective graphics tasks of a graphics job.
2. The method as defined in claim 1 , further comprising:
enabling functionality of the integrated graphics processing whenever the discrete graphics processing is coupled with the bridge circuit.
3. The method as defined in claim 2 , wherein enabling functionality of the integrated processing includes:
establishing separate data paths enabling the integrated graphics processing and the discrete graphics processing to independently access system resources.
4. A method for processing at least one graphics job comprising:
processing at least one task of a graphics job using integrated graphics processing circuitry in the bridge circuit; and
processing at least another task of the graphics job using a discrete graphics processor unit.
5. The method as defined in claim 4 , further comprising:
enabling functionality of the integrated graphics processing circuitry whenever the discrete graphics processing is coupled with the integrated graphics processing circuitry.
6. The method as defined in claim 5 , wherein enabling functionality of the integrated processing circuitry includes:
establishing separate data paths enabling the integrated graphics processing circuitry and the discrete graphics processor to independently access at least one of system processing circuitry and system memory.
7. A bridge circuit comprising:
an integrated graphics processing circuit configured to process graphics jobs from an application run on a processor;
an interface operable to interface with a discrete graphics processing circuit;
a controller configured to detect when a discrete graphics processing circuit is coupled to the interface and to cause the integrated graphics processing circuit to be operable to process at least one task of a graphics job in conjunction with operation of the discrete graphics processing circuit that is operable to process at least one other task of the graphics job.
8. The bridge circuit as defined in claim 7 , wherein the controller is further configured to enable functionality of the integrated processing circuitry whenever a discrete graphics processor is coupled to the bridge circuit.
9. The bridge circuit as defined in claim 8 , wherein the controller is further configured to establish separate data paths enabling the integrated graphics processing circuit and the discrete graphics processor to independently access at least one of system processing circuitry and a system memory.
10. A graphics processing circuit comprising:
a first graphics processing circuitry configured to process graphics jobs from an application and to couple with an interface operable to interface with at least a second graphics processing circuitry; and
a controller responsive to the coupling of the second external graphics processing circuitry to the interface and configured to cause the first graphics processing circuitry to be operable to process at least a task of a graphics job in conjunction with operation of the second graphics processing circuitry that is operable to process at least one other task of the graphics job.
11. The graphics processing circuit as defined in claim 10 , wherein the controller is further configured to enable functionality of the first graphics processing circuitry whenever the second graphics processing circuitry is coupled to the first graphics processing circuitry.
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US20190012760A1 (en) | 2019-01-10 |
US9424622B2 (en) | 2016-08-23 |
US9865030B2 (en) | 2018-01-09 |
US20160364834A1 (en) | 2016-12-15 |
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