US20060230214A1 - Method and system for embedded disk controllers - Google Patents
Method and system for embedded disk controllers Download PDFInfo
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- US20060230214A1 US20060230214A1 US11/447,572 US44757206A US2006230214A1 US 20060230214 A1 US20060230214 A1 US 20060230214A1 US 44757206 A US44757206 A US 44757206A US 2006230214 A1 US2006230214 A1 US 2006230214A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0674—Disk device
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0626—Reducing size or complexity of storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0038—System on Chip
Definitions
- the present invention relates generally to disk controllers, and more particularly to an embedded disk controller that includes a hard disk controller, a microprocessor, a digital signal processor, and a servo controller.
- Conventional computer systems typically include several functional components. These components may include a central processing unit (CPU), main memory, input/output (“I/O”) devices, and disk drives.
- the main memory is coupled to the CPU via a system bus or a local memory bus.
- the main memory is used to provide the CPU access to data and/or program information that is stored in main memory at execution time.
- the main memory is composed of random access memory (RAM) circuits.
- RAM random access memory
- a disk drive typically includes one or more magnetic disks. Each disk typically has a number of concentric rings or tracks on which data is stored. The tracks themselves may be divided into sectors, which are the smallest accessible data units. A positioning head above the appropriate track accesses a sector. An index pulse typically identifies the first sector of a track. The start of each sector is identified with a sector pulse. Typically, the disk drive waits until a desired sector rotates beneath the head before proceeding for a read or write operation. Data is accessed serially, one bit at a time and typically, each disk has its own read/write head.
- the disk drive is connected to the disk controller that performs numerous functions, for example, converting digital data to analog head signals, disk formatting, error checking and fixing, logical to physical address mapping and data buffering.
- the disk controller includes numerous components.
- the data buffering function is used to transfer data between the host and the disk.
- Data buffering is needed because the speed at which the disk drive can supply data or accept data from the host is different than the speed at which the host can correspondingly read or supply data.
- Conventional systems include a buffer memory that is coupled to the disk controller. The buffer memory temporarily stores data that is being read from or written to the disk drive.
- the interrupt controller module generates a regular interrupt based on a regular interrupt request (IRQ).
- the interrupt controller module includes an interrupt generation module that generates a fast interrupt when an FIQ is pending and processes an IRQ based on priority when an FIQ is not pending.
- FIG. 1 is a block diagram of a hard disk controller in the prior art
- FIGS. 2A-2B (referred herein as FIG. 2 ) is a block diagram of an embedded disk controller, according to one aspect of the present invention
- FIGS. 4A, 4B and 4 C show a table with various input signals to the external bus controller, according to one aspect of the present invention
- FIG. 15 is a state machine diagram of the external bus controller, according to one aspect of the present invention.
- FIG. 30 is a state machine diagram used by the interrupt controller, according to one aspect of the present invention.
- FIG. 32B is a table showing various output signals from the history module, according to one aspect of the present invention.
- FIGS. 44A-44B (referred to herein as FIG. 44 ) show a functional block diagram of the history module, according to one aspect of the present invention
- Disk formatter 112 is a disk interface controller and performs control operations when microprocessor 100 loads all required control information and parameter values into a writable control store (WCS) RAM (not shown) and issues a command. Disk formatter 112 executes the command with no microprocessor 100 intervention.
- WCS writable control store
- a host system sends a read command to disk controller 101 , which stores the read commands in buffer memory 111 .
- Microprocessor 100 then read the command out of buffer memory 111 and initializes the various functional blocks of disk controller 101 .
- Data is read from disk 115 and is passed through disk formatter 112 simultaneously to buffer controller 108 and to ECC module 109 . Thereafter, ECC module 109 provides the ECC mask for errors, which occurred during the read operation, while data is still in buffer controller 108 . The error is corrected and corrected data is sent to buffer memory 111 , and then passed to the host system.
- FIG. 2 shows a block diagram of an embedded disk controller system 200 according to one aspect of the present invention that not only includes the functionality of disk controller 101 , but also includes various other features to meet the demands of storage industry.
- System 200 may be an application specific integrated circuit (“ASIC”).
- ASIC application specific integrated circuit
- ROM read only memory
- MP 240 includes a TAP controller 242 that performs various de-bugging functions.
- System 200 includes registers 209 that include configuration, system control, clock and power management information.
- DSPIM 109 interfaces DSP 229 with MP 240 and updates a tightly coupled memory module (TCM) 212 (also referred to as “memory module” 212 ) with servo related information.
- TCM tightly coupled memory module
- MP 240 can access TCM 212 via DSPIM 210 .
- embedded processors provide independent real time control, with one processor as the system control processor (MP 240 ) and the second processor (DSP 229 ) as a slave to the first for real time control of the disk servo mechanism.
- DSP 229 as a slave also provides real time control for positioning a disk actuator. This includes analyzing error positioning data and outputting error correction data.
- the dual processors also improve overall performance for the host. It also allows data recovery when ECC cannot correct data failures. Using unique data recovery algorithms and error recovery information data may be recovered if the ECC module 109 fails to dynamically correct the data.
- DW 601 E specifies the data width of an external bus device (not shown).
- a state machine may be used by EBC 228 to use the various register 601 values, as shown by the state machine diagram in FIG. 15 and discussed below. It is noteworthy that the invention is not limited to the command terminology of FIG. 7 .
- FIG. 14 shows a functional block diagram of system 1400 used in EBC 228 for supporting plural external devices.
- Input signals 302 and 307 from AHB bus 236 are sent to a validation module 1401 that validates the incoming signals.
- a valid signal is then sent to state machine logic 1402 .
- State S0 This is an idle state, until a valid operation on the bus is received.
- State S6 This state is entered only during write operations and is used to provide write data hold time. During this state, EBC 228 continues to drive the write data on the external bus while it keeps the write enable signal de-asserted.
- FIG. 12 shows a diagram for a half word write access to a 16 bit external bus.
- Interrupt Controller (“IC”) 207
- FIG. 16 shows IC 207 with various input signals ( 1601 - 1609 ) and output signals ( 1610 - 1614 ).
- FIGS. 17 and 18 provide a description of signals 1601 - 1609 and 1610 - 1614 , respectively.
- Register 1904 also includes a trigger mode TM value 1904 E that specifies the mode of an interrupt source signal.
- Field 1904 E specifies whether the interrupt signal is edge triggered or level sensitive. Use of TM 1904 E in register 1904 is discussed below in detail.
- FIG. 25 shows the fields used in register 1907 .
- Register 1907 is a control register showing when an interrupt has been sent.
- Field 1907 A is used for a FIQ source and field 1907 B is used for IRQ sources, as described below.
- FIQ interrupt source as defined by TM 1904 E is level sensitive then the firmware ensures that the FIQ interrupt source is de-asserted and then an end of interrupt (“EOI”) is sent to IC 207 to clear the FIQIRS 1904 B state; or
- IRQ scanner 2011 that scans the vector values, as described below.
- IRQ scanner 2011 provides an input 2011 A to interrupt generator 2009 that generates IRQn 1613 .
- TM 1901 E or 1901 K level sensitive then the firmware ensures that the IRQ interrupt source is de-asserted. Thereafter, an end of interrupt (“EOI”) is sent to IC 207 to clear the IRQIRS 1901 B or 1901 I state; or
- IRQ interrupt source is defined by TM 1901 E or 1901 K as edge triggered
- the firmware need only read register 1905 .
- IRQIRP 1901 C or 1901 H is cleared and IRQIRS 1901 B or 1901 I is set.
- IRQIRS clears when the interrupt source de-asserts. The next interrupt does not occur until the interrupt source signal de-asserts, and asserts again.
- step S 2804 registers in register control array 1901 are read.
- step S 2805 vector values are scanned (discussed below with respect to FIG. 29 ).
- TM values prevents interlocking of interrupt service by MP 240 .
- History module 234 is a peripheral on APB Bus 208 that records transaction information over either AHB Bus 236 and/or APB Bus 208 . The recorded information may be used for debugging and analyzing firmware and hardware problems. History module 234 is set up and initiated through APB Bridge 235 and information from History module 234 is extracted through APB Bridge 235 . History module 234 includes a buffer(s) (not shown) for reading and writing recorded information.
- FIG. 31 shows a top-level block diagram of History Module 234 with plural input and output signals.
- Field 3300 J defines break point conditions for History Module 234 . Break point conditions are those, which stop recording/monitoring by History Module 234 . Field 3300 I enables break points, while break point testing stops after a break point is detected, if field 3300 E is set.
- An interrupt is generated based on the detection of the break point condition and if field 3300 F is set, after the interrupt source is enabled in IC module 207 .
- Bus ( 208 and 236 ) transactions are recorded when EnableRcrdReg is set.
- Mux 4324 samples signals HREADY 307 and PENABLE 1603 . The signals indicate that a valid transaction is on the bus that may be recorded unless masked by field 3300 A.
- FIG. 50 shows a flow diagram of communication between MP 240 and DSP 229 using IN/Out registers 4600 and 4700 , respectively.
- step S 5003 DSP 229 services the interrupt by reading register 4600 and clears field 4900 C.
- Semaphore register 5100 field 5100 A provides firmware interlock when MP 240 acquires the semaphore.
- Semaphore register 5100 field 5100 B provides hardware interlock when MP 240 acquires the semaphore.
- DSP 229 cannot execute a write access to any register except register 5100 or a status register.
Abstract
An embedded disk controller comprises a main processor in communication with a first bus. A second processor is in communication with a second bus. An external bus controller (EBC) is in communication with the first bus and in communication with external devices via an external bus interface. A history module is located in the embedded disk controller, communicates with the first bus and the second bus, and at least one of monitors transaction information of one of said external devices and masks information of one of said external devices via the EBC based on setup information, wherein the EBC and the history module are located on at least on of an integrated circuit (IC) and a system on a chip (SOC) with the embedded disk controller.
Description
- This application is a continuation of U.S. patent application Ser. No. 10/385,022 filed on Mar. 10, 2003. This application is related to the following U.S. patent applications assigned to the same assignee, filed on even date herewith and incorporated herein by reference in their entirety:
- “METHOD AND SYSTEM FOR SUPPORTING MULTIPLE EXTERNAL SERIAL PORT DEVICES USING A SERIAL PORT CONTROLLER IN AN EMBEDDED DISK CONTROLLER”, Docket Number QE1042.US, Ser. No. 10/385,039, with MICHAEL R. SPAUR AND IHN KIM as inventors;
- “METHOD AND SYSTEM FOR AUTOMATIC TIME BASE ADJUSTMENT FOR DISK DRIVE SERVO CONTROLLERS”, Docket NUMBER QE1040.US, Ser. No. 10/384,992, WITH MICHAEL R. SPAUR AND RAYMOND A. SANDOVAL as inventors;
- “METHOD AND SYSTEM FOR USING AN EXTERNAL BUS CONTROLLER IN EMBEDDED DISK CONTROLLERS” Ser. No. 10/385,046 Docket no. QE1035.US with GARY R. ROBECK, LARRY L. BYERS, JOSEBA M. DESUBIJANA, And FREDARICO E. DUTTON as inventors.
- “METHOD AND SYSTEM FOR USING AN INTERRUPT CONTROLLER IN EMBEDDED DISK CONTROLLERS”, Ser. No. 10/384,991, Docket No. QE1039.US, with DAVID M. PURDHAM, LARRY L. BYERS and ANDREW ARTZ as inventors.
- “METHOD AND SYSTEM FOR MONITORING EMBEDDED DISK CONTROLLER COMPONENTS”, Ser. No. 10/385,042, Docket Number QE1038.US, with LARRY L. BYERS, JOSEBA M. DESUBIJANA, GARY R. ROBECK, and WILLIAM W. DENNIN as inventors.
- “METHOD AND SYSTEM FOR COLLECTING SERVO FIELD DATA FROM PROGRAMMABLE DEVICES IN EMBEDDED DISK CONTROLLERS”, Ser. No. 10/385,405, Docket NO. QE1041.US, with MICHAEL R. SPAUR AND RAYMOND A. SANDOVAL as inventors.
- The present invention relates generally to disk controllers, and more particularly to an embedded disk controller that includes a hard disk controller, a microprocessor, a digital signal processor, and a servo controller.
- Conventional computer systems typically include several functional components. These components may include a central processing unit (CPU), main memory, input/output (“I/O”) devices, and disk drives. In conventional systems, the main memory is coupled to the CPU via a system bus or a local memory bus. The main memory is used to provide the CPU access to data and/or program information that is stored in main memory at execution time. Typically, the main memory is composed of random access memory (RAM) circuits. A computer system with the CPU and main memory is often referred to as a host system.
- The main memory is typically smaller than disk drives and may be volatile. Programming data is often stored on the disk drive and read into main memory as needed. The disk drives are coupled to the host system via a disk controller that handles complex details of interfacing the disk drives to the host system. Communications between the host system and the disk controller is usually provided using one of a variety of standard I/O bus interfaces.
- Typically, a disk drive includes one or more magnetic disks. Each disk typically has a number of concentric rings or tracks on which data is stored. The tracks themselves may be divided into sectors, which are the smallest accessible data units. A positioning head above the appropriate track accesses a sector. An index pulse typically identifies the first sector of a track. The start of each sector is identified with a sector pulse. Typically, the disk drive waits until a desired sector rotates beneath the head before proceeding for a read or write operation. Data is accessed serially, one bit at a time and typically, each disk has its own read/write head.
- The disk drive is connected to the disk controller that performs numerous functions, for example, converting digital data to analog head signals, disk formatting, error checking and fixing, logical to physical address mapping and data buffering. To perform the various functions for transferring data, the disk controller includes numerous components.
- Typically, the data buffering function is used to transfer data between the host and the disk. Data buffering is needed because the speed at which the disk drive can supply data or accept data from the host is different than the speed at which the host can correspondingly read or supply data. Conventional systems include a buffer memory that is coupled to the disk controller. The buffer memory temporarily stores data that is being read from or written to the disk drive.
- Conventionally, when data is read from the disk drive, a host system sends a read command to the disk controller, which stores the read command into the buffer memory. Data is read from the disk drive and stored in the buffer memory. An ECC module determines the errors that occur in the data and appropriately corrects those errors in the buffer memory. Once it is determined that there are no errors, data is transferred from the buffer memory to the host system.
- Conventional disk controllers do not have an embedded processor or specific modules that can efficiently perform the complex functions expected from disk controllers.
- Conventional disk controllers cannot access plural external memory having different timing characteristics. In addition, conventional controllers do not easily permit use of different bus data width to which external memory is coupled. In addition, conventional disk controllers do not have a built in module that can track bus activity and hence provide valuable information for de-bugging. In conventional disk controllers, the disk controller must be coupled to an external bus analyzer to debug and/or monitor bus activity. This process is cumbersome and requires additional pins on the disk controller. In addition, conventional monitoring techniques cannot easily isolate components within the disk controller that need to be monitored. Furthermore, conventional disk controllers do not have a dedicated module that controls, prioritizes and generates interrupts.
- Therefore, what is desired is an embedded disk controller system that can efficiently function in the fast paced, media storage environment.
- An embedded disk controller, comprises a main processor in communication with a first bus. A second processor is in communication with a second bus. An external bus controller (EBC) is in communication with the first bus and in communication with external devices via an external bus interface. A history module is located in the embedded disk controller, communicates with the first bus and the second bus, and at least one of monitors transaction information of one of said external devices and masks information of one of said external devices via the EBC based on setup information, wherein the EBC and the history module are located on at least on of an integrated circuit (IC) and a system on a chip (SOC) with the embedded disk controller.
- In other features of the invention, an interrupt controller module generates a fast interrupt to the main processor based on a fast interrupt request (FIQ). The EBC includes at least one of a segment descriptor register and a device range register, wherein the embedded disk controller programs timing characteristics of the external devices via the segment descriptor register and the main processor accesses address space of the external devices via the device range register. The history module records transaction information on at least one of the first bus and the second bus based on a register map. The register map stores a break point condition value that is set by the first processor and the history module stops recording the transaction information based on the break point condition value. The history module stores a trigger mode field value, wherein the history module records a predetermined number of entries after the break point condition value reaches a threshold based on the trigger mode field value.
- In other features of the invention, the history module at least one of stores a read mask field value and stops reading operations based on the read mask field value and stores a write mask field value and stops write operations based on the write mask field value. The history module stores an enable clock slam field value and the history module generates a signal that stops clocks in the embedded disk controller based on the enable clock slam field value. A servo controller communicates with the second processor via a servo controller interface and provides real time servo controller information to the second processor. The second processor is a digital signal processor (DSP) that communicates with the first main processor via an interface.
- In other features of the invention, the interrupt controller module generates a regular interrupt based on a regular interrupt request (IRQ). The interrupt controller module includes an interrupt generation module that generates a fast interrupt when an FIQ is pending and processes an IRQ based on priority when an FIQ is not pending.
- In still other features, the systems and methods described above are implemented by a computer program executed by one or more processors. The computer program can reside on a computer readable medium such as but not limited to memory, non-volatile data storage and/or other suitable tangible storage mediums.
- Further areas of applicability of the present disclosure will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the disclosure, are intended for purposes of illustration only and are not intended to limit the scope of the disclosure.
- The foregoing features and other features of the present invention will now be described. In the drawings, the same components have the same reference numerals. The illustrated embodiment is intended to illustrate, but not to limit the invention. The drawings include the following Figures:
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FIG. 1 is a block diagram of a hard disk controller in the prior art; -
FIGS. 2A-2B (referred herein asFIG. 2 ) is a block diagram of an embedded disk controller, according to one aspect of the present invention; -
FIG. 3 is a block diagram of an external bus controller, according to one aspect of the present invention; -
FIGS. 4A, 4B and 4C (referred herein asFIG. 4 ) show a table with various input signals to the external bus controller, according to one aspect of the present invention; -
FIGS. 5A-5C (referred herein asFIG. 5 ) show a table with various output signals from the external bus controller, according to one aspect of the present invention; -
FIG. 6 is a table showing a register map used by the external bus controller, according to one aspect of the present invention; -
FIGS. 7-9 show various registers with plural fields that are used by the external bus controller, according to one aspect of the present invention; -
FIGS. 10-13 show various timing diagrams for the external bus controller, according to one aspect of the present invention; -
FIG. 14 is a functional block diagram of the external bus controller, according to one aspect of the present invention; -
FIG. 15 is a state machine diagram of the external bus controller, according to one aspect of the present invention; -
FIG. 16 is a block diagram of an interrupt controller, according to one aspect of the present invention; -
FIGS. 17A-17B (referred herein asFIG. 17 ) show a table with various input signals to the interrupt controller, according to one aspect of the present invention; -
FIG. 18 is a table showing various output signals from the interrupt controller, according to one aspect of the present invention; -
FIG. 19 is a table showing a register map used by the interrupt controller, according to one aspect of the present invention; -
FIGS. 20-26 show various registers with various fields that are used by the interrupt controller, according to one aspect of the present invention; -
FIGS. 27A-27B (referred herein asFIG. 27 ) show a functional block diagram of the interrupt controller, according to one aspect of the present invention; -
FIG. 28 is a process flow diagram for generating interrupts, according to one aspect of the present invention; -
FIG. 29 is a process flow diagram for setting interrupt priority, according to one aspect of the present invention; -
FIG. 30 is a state machine diagram used by the interrupt controller, according to one aspect of the present invention; -
FIG. 31 is a block diagram of history module, according to one aspect of the present invention; -
FIGS. 32A-1 to 32A4-4 show a table with various input signals to the history module, according to one aspect of the present invention; -
FIG. 32B is a table showing various output signals from the history module, according to one aspect of the present invention; -
FIGS. 33-43 show various registers with various fields that are used by the history module, according to one aspect of the present invention; -
FIGS. 44A-44B (referred to herein asFIG. 44 ) show a functional block diagram of the history module, according to one aspect of the present invention; -
FIG. 45 is a flow diagram of process steps for updating a history stack pointer, according to one aspect of the present invention; -
FIGS. 46-49 show various registers with various fields that are used as “mail boxes”, according to one aspect of the present invention; -
FIG. 50 shows a flow diagram of process steps for inter-processor communication, according to one aspect of the present invention; and -
FIGS. 51-53 show various registers with various fields that are used for indirect access of a memory module, according to one aspect of the present invention. - To facilitate an understanding of the preferred embodiment, the general architecture and operation of a disk controller will be described initially. The specific architecture and operation of the preferred embodiment will then be described.
- The disk drive system of
FIG. 1 is an example of an internal (hard) disk drive included in a computer system system. The host computer (not shown) and the disk drive communicate viaport 102, which is connected to a data bus (not shown). In an alternate embodiment (not shown), the disk drive is an external storage device, which is connected to the host computer via a data bus. The data bus, for example, is a bus in accordance with a Small Computer System Interface (SCSI) specification. Those skilled in the art will appreciate that other communication buses known in the art can be used to transfer data between the disk drive and the host system. - As shown in
FIG. 1 , the disk drive includesdisk controller 101, which is coupled toSCSI port 102,disk port 114,buffer memory 111 andmicroprocessor 100.Interface 118 serves to couplemicroprocessor bus 107 tomicroprocessor 100. It is noteworthy thatmicroprocessor 100 is not on the same chip asdisk controller 101. A read only memory (“ROM”) omitted from the drawing is used to store firmware code executed bymicroprocessor 100.Disk port 114couples disk controller 101 todisk 115. - As is standard in the industry, data is stored on
disk 115 in sectors. Each sector is byte structured and includes various fields, referred to as the sector format. A typical sector format includes a logical block address (“LBA”) of about four bytes followed by a data field of about 512 bytes. The LBA contains position information, for example, cylinder, head and sector numbers. A field for a CRC checksum of 4 bytes typically follows the data field. A subsequent field for a number of ECC bytes, for example 40-80 bytes, is located at the end of the sector. -
Controller 101 can be an integrated circuit (IC) (or application specific integrated circuit “ASIC”) that comprises of various functional modules, which provide for the writing and reading of data stored ondisk 115.Microprocessor 100 is coupled tocontroller 101 viainterface 118 to facilitate transfer of data, address, timing and control information.Buffer memory 111 is coupled tocontroller 101 via ports to facilitate transfer of data, timing and address information. -
Data flow controller 116 is connected tomicroprocessor bus 107 and to buffercontroller 108. AnECC module 109 anddisk formatter 112 are both connected tomicroprocessor bus 107.Disk formatter 112 is also coupled to data and controlport 113 and todata bus 107. -
SCSI controller 105 includes programmable registers and state machine sequencers that interface withSCSI port 102 on one side and to a fast, buffered direct memory access (DMA) channel on the other side. -
Sequencer 106 supports customized SCSI sequences, for example, by means of a 256-location instruction memory that allows users to customize command automation features.Sequencer 106 is organized in accordance with the Harvard architecture, which has separate instruction and data memories.Sequencer 106 includes, for example, a 32-byte register file, a multi-level deep stack, an integer algorithmic logic unit (ALU) and other special purpose modules.Sequencer 106 support's firmware and hardware interrupts schemes. The firmware interrupt allowsmicroprocessor 100 to initiate an operation withinSequencer 106 without stopping sequencer operation. Hardware interrupt comes directly fromSCSI controller 105. -
Disk formatter 112 is a disk interface controller and performs control operations whenmicroprocessor 100 loads all required control information and parameter values into a writable control store (WCS) RAM (not shown) and issues a command.Disk formatter 112 executes the command with nomicroprocessor 100 intervention. -
Buffer controller 108 can be a multi-channel, high speed DMA controller.Buffer controller 108 connectsbuffer memory 111 todisk formatter 112 and to an ECC channel ofECC module 109, a SCSI channel ofSCSI controller 105 andmicro-controller bus 107.Buffer controller 108 regulates data movement into and out ofbuffer memory 111. - To read data from
disk 115, a host system sends a read command todisk controller 101, which stores the read commands inbuffer memory 111.Microprocessor 100 then read the command out ofbuffer memory 111 and initializes the various functional blocks ofdisk controller 101. Data is read fromdisk 115 and is passed throughdisk formatter 112 simultaneously tobuffer controller 108 and toECC module 109. Thereafter,ECC module 109 provides the ECC mask for errors, which occurred during the read operation, while data is still inbuffer controller 108. The error is corrected and corrected data is sent to buffermemory 111, and then passed to the host system. -
FIG. 2 shows a block diagram of an embeddeddisk controller system 200 according to one aspect of the present invention that not only includes the functionality ofdisk controller 101, but also includes various other features to meet the demands of storage industry.System 200 may be an application specific integrated circuit (“ASIC”). -
System 200 includes a microprocessor (“MP”) 240 (which is also the overall system processor) that performs various functions described below.MP 240 may be a Pentium® Class processor designed and developed by Intel Corporation® or an ARM processor (for example, ARM966E-S®) or any other processor.MP 240 is operationally coupled tovarious system 200 components viabuses Bus 236 may be an Advanced High performance (AHB) bus as specified by ARM Inc.Bus 208 may an Advanced Peripheral Bus (“APB”) as specified by ARM Inc. The specifications for AHB and APB are incorporated herein by reference in their entirety. It is noteworthy that the present invention is not limited to any particular bus or bus standard. -
Arbiter 245 arbitrates access toAHB bus 236, whileAPB bridge 235 is used to communicate betweenbuses -
System 200 is also provided with a random access memory (RAM) or static RAM (SRAM) 238 that stores programs and instructions, which allowsMP 240 to execute computer instructions.MP 240 may execute code instructions (also referred to as “firmware”) out ofRAM 238. -
System 200 is also provided with read only memory (ROM) 237 that stores invariant instructions, including basic input/output instructions. -
MP 240 includes aTAP controller 242 that performs various de-bugging functions. -
MP 240 is also coupled to an External Bus Interface Bridge (or Controller) (“EBC” also referred to as “EBI” or “EBI controller”) 228 via an external bus interface (“EBI/F”) 227.EBC 228 allowssystem 200 viaMP 240 and EBI/F 227 to read and write data using an external bus, for example, a storage device external tosystem 200, including FLASH memory, read only memory and static RAM.EBC 228 may be used to control external memory (not shown), as discussed in detail below. EBI/F 227 may be programmed to interface with plural external devices. -
System 200 includes an interrupt controller (“IC”) 207 that can generate regular interrupts (IRQ 207A) or a fast interrupt (FIQ 207B) toMP 240. In one aspect of the present invention,IC 207 is an embedded system that can generate interrupts and arbitrates between plural interrupts.IC 207 is described below in detail. -
System 200 includes a serial interface (“UART”) 201 that receives information viachannel 203 and transmits information via channel 204. -
System 200 includesregisters 209 that include configuration, system control, clock and power management information. -
System 200 also includes an address break point and history module (also referred to as “history module” or “history stack”) 234 that monitors activity onbusses system 200.History module 234 is discussed below in detail. -
System 200 also includes atimer module 206 that controlled byMP 240 and includes various timers, for example, the “Watchdog timer”. -
System 200 is provided with a general purpose input/output (“GPIO”)module 202 that allows GPIO access to external modules (not shown). -
System 200 is also provided with a digital signal processor (“DSP”) 229 that controls and monitors various servo functions through DSP interface module (“DSPIM”) 210 andservo controller interface 212 operationally coupled to aservo controller 216. -
DSPIM 109interfaces DSP 229 withMP 240 and updates a tightly coupled memory module (TCM) 212 (also referred to as “memory module” 212) with servo related information.MP 240 can accessTCM 212 viaDSPIM 210. - Servo controller interface (“SCI”) 211 includes an
APB interface 214 that allowsSCI 211 to interface withAPB bus 208 and allowsSC 216 to interface withMP 240 andDSP 229.SCI 211 also includesDSPAHB interface 215 that allows access toDSPAHB bus 233.SCI 211 is provided with a digital to analog/analog todigital converter 213 that converts data from analog to digital domain and vice-versa.Analog data 223 entersmodule 213 and leaves asdata 222 to aservo drive 221. -
SC 212 has a read channel device (RDC) interface 217, a spindle motor control (“SVC”) interface 219, a head integrated circuit (HDIC)interface 218 and servo data (“SVD”)interface 219A. -
System 200 also includes ahard disk controller 101A that is similar to theHDC 101 and includes acode cache 101B. - In one aspect of the present invention, because
system 200 includes, dual embedded processors (MP 240 and DSP 229) withdedicated history module 234,IC module 207, servo controller andEBC 228, it can perform various functions independently. This not only saves the resources ofMP 240 but also improves communication between a host and an external device. - In another aspect, embedded processors (
MP 240 and DSP 229) provide independent real time control, with one processor as the system control processor (MP 240) and the second processor (DSP 229) as a slave to the first for real time control of the disk servo mechanism.DSP 229 as a slave also provides real time control for positioning a disk actuator. This includes analyzing error positioning data and outputting error correction data. - Dual processors also provide a real time overlap for processing host commands. For example, one processor may move the actuator while the other processor translates the LBA into physical information and queue host requests.
- The dual processors also improve overall performance for the host. It also allows data recovery when ECC cannot correct data failures. Using unique data recovery algorithms and error recovery information data may be recovered if the
ECC module 109 fails to dynamically correct the data. - The following describes the various components of
system 200 in detail, according to various aspects of the present invention. -
EBC 228 is a slave onAHB bus 236 and adapts the high performance ofAHB bus 236 to a slower external bus (not shown) that can support external memory (including without limitation, flash memory, ROM, and static memory (not shown)).FIG. 3 shows a block diagram ofEBC 228 with various input signals (300-313) and output signals (314-323).FIG. 4 provides a table describing signals 300-313 andFIG. 5 provides a table describing signals 314-323. - In one aspect of the present invention,
MP 240 viaEBC 228 may access multiple devices with different timing characteristics or data width. At least a Segment Descriptor register is provided, which specifies the timing characteristic of each external device. Also provided is at least a device range register, which specifies the size of the external device address space. Depending on the external bus data width,EBC 228 may convertAHB bus 236 transactions into multiple external bus transactions. -
FIG. 6 provides aregister map 600 forEBC 228, according to one aspect of the present invention.Register map 600 includes segment descriptor registers 601, device range registers 602, andEBC 228configuration register 603. - Each device segment descriptor register 601 may be formatted the same way with the same fields. Segment descriptor registers 601 allow firmware to program timing characteristics for an external memory device on an external memory bus. For example, as shown in the table of
FIG. 6 , four segment descriptor registers 601 may include timing intervals for four different devices. It is noteworthy that the example inFIG. 6 is only to illustrate the adaptive aspects of the present invention and not to limit the number of devices to just four. Any number of devices may be used. -
FIG. 7 provides a description of thesegment register 601 values.MP 240 writes the values in segment registers 601 during initialization. Register(s) 601 includes various values (601A-601G) that allow the firmware to program timing characteristics for an external memory device. Values include a Write Hold Wait State (WHW) 601A, TransactionRecovery Wait States 601B,Setup 2 Wait States (SW2) 601C,Setup 1 Wait States (SW1) 601D, Data Width (DW) 601E, Write Wait States (WW) 601F and Read Wait State (RW) 601G, as described inFIG. 7 . -
DW 601E specifies the data width of an external bus device (not shown). A state machine may be used byEBC 228 to use thevarious register 601 values, as shown by the state machine diagram inFIG. 15 and discussed below. It is noteworthy that the invention is not limited to the command terminology ofFIG. 7 . -
FIG. 8 provides a description of device range registers 602. An enable (“EN”) bit 602A is set to access the address range of a device, while the device range (DvRng) 602B specifies the number of blocks that may be addressed within the device address space.MP 240 to allow access to the address space within a particular device address initializesdevice range register 602. -
FIG. 9 shows the plural fields (603A and 603B) used for configuringEBC 228.Device allocation bit 603B specifies the number of devices allocated on the external bus (not shown) andfield 603A is used to read the external bus width as supported byEBC 228. -
FIG. 14 shows a functional block diagram ofsystem 1400 used inEBC 228 for supporting plural external devices. Input signals 302 and 307 fromAHB bus 236 are sent to avalidation module 1401 that validates the incoming signals. A valid signal is then sent tostate machine logic 1402. -
System 1400 includes a set of registers, for example,HaddrReg 1408,HwriteReg 1411 andHsizeReg 1412 register and their usage is described below. - [0105]
FIG. 15 shows a state machine diagram of process steps used bystate machine logic 1402. The following provides a description of the plural states used bystate machine logic 1402 to implement the adaptive aspects of the present invention. - State S0: This is an idle state, until a valid operation on the bus is received.
- State S1: This is a first stage for decoding an address in
HaddreReg 1408 to determine which external device if any, is the target for a read or write cycle. After determining the target external device, various counter values, as shown inFIG. 15 , are loaded during this state. - State S2: This is a second state during which
state machine 1402 remains in this stage until theSW1 601D andTRW 601B values expire to avoid data contention on the external bus. - State S3: The state machine stays in this state for at least one clock cycle with all external bus controls as being inactive. This state is only used for sequential write operations.
- State S4: During this state the appropriate chip select signal (XCS 317) is asserted while the write enable (XWEn 319) or output enable (XOEn 318) are deasserted, until
SW2 601C expires. - State S5: The
state machine logic 1402 stays in this state until a current read or write operation is completed. During this state the chip select, write enable or out enable signals are asserted. For write commands,EBC 228 writes data and for read operation,EBC 228 reads data. - State S6: This state is entered only during write operations and is used to provide write data hold time. During this state,
EBC 228 continues to drive the write data on the external bus while it keeps the write enable signal de-asserted. - State S7: During this state, registers within
EBC 228 are read or written. - The relationship between the various states is shown in
FIG. 15 . -
FIGS. 10-13 show various timing diagrams using input signals 300-313 and output signals 314-323 with respect to the functional block diagram ofsystem 1400 and the state diagram ofFIG. 15 . -
FIG. 10 shows a diagram for a half word read access to a 16 bit external bus. -
FIG. 11 shows a diagram for a word read access to a 16 bit external bus. -
FIG. 12 shows a diagram for a half word write access to a 16 bit external bus. -
FIG. 13 shows a diagram for a word write access to a 16 bit external bus. -
IC 207 synchronizes and prioritizes interrupt signals as a slave on theAPB bus 208.IC 207 handles two types of interrupts, Fast Interrupt Request (“FIQ”) and Interrupt Request (“IRQ”). The interrupts are sent toMP 240. TheFIQ 207B is used for critical interrupts as defined by a user or firmware.IRQs 207A are provided for routine interrupts.IC 207 provides the interrupts toMP 240 that interrogatesIC 207 to retrieve a particular interrupt with an interrupt vector, as described below.MP 240 may clear the interrupt after retrieving the interrupt information. - In one aspect of the present invention,
IC module 207, providesFIQ 207B for critical interrupts, scans interrupts for priority, prevents interrupt source lockout (interlock) in the interrupt service and allows a user to change various interrupt options using firmware. -
FIG. 16 showsIC 207 with various input signals (1601-1609) and output signals (1610-1614).FIGS. 17 and 18 provide a description of signals 1601-1609 and 1610-1614, respectively. -
IC module 207 uses plural registers for controlling interrupts. The base address ofIC module 207 is specified inAPB Bridge 235. When signalPSELIC 1604 fromAPB bridge 235 is sent toIC module 207, the base address ofIC module 207 is detected byAPB bridge 235 andIC module 207 decodes signalsPADDR 1605 and PWRITE 1606 to select the appropriate register address.IC module 207 examines signalPADDR 1605 for exceptions. An access to an undefined or reserved register address results inIC module 207 asserting thePADREXCPT signal 1610 toAPB Bridge 235. It is noteworthy that this does not change the state ofIC module 207. Also, access to an undefined “read” address results inPADREXCPT signal 1610 toAPB Bridge 235. -
FIG. 19 shows a register map 1900 forIC module 207. Register map 1900 includes a set ofregisters 1901 for IRQ control and aregister 1904 for FIQ control.Register 1902 stores a current FIQ interrupt and register 1903 is used to mask/unmask FIQ ability, via firmware. -
FIG. 20 shows details ofregister 1905 that provides status for an IRQ interrupt.Register 1905 includesfield 1905A value for IRQValid. When the bit value for IRQValid is valid (for example, 1) then it indicates thatIC module 207 has resolved an IRQ interrupt and theVector Address field 1905B is valid. -
FIG. 21 shows details ofregister 1903 that allows firmware to mask the Interrupt ability. FIQ interrupt ability may be enabled or disabled by setting upFIQInt Mask field 1903B. In addition, by settingfield 1903A, IRQ interrupt sources may be masked. -
FIG. 22 shows details of various fields used inregister 1904, which is an interrupt control register for FIQ source. MK-Read onlyfield 1904A is a copy of the mask bit fromregister 1903. Interrupt Request Sent (“IRS”)-ReadOnly field 1904B is set whenMP 240 reads the corresponding interrupt source as the prioritized interrupt fromregister 1902. - Interrupt Request Pending (“IRP”)-Read
Only field 1904C is set when a corresponding interrupt source is asserted. WhenIRS 1904B is set,IRP 1904C is cleared. In addition, when the source interrupt is masked,IRP 1904C may be cleared. Polarity (“PLR”) 1904D is used to specify the polarity of an interrupt source. -
Register 1904 also includes a triggermode TM value 1904E that specifies the mode of an interrupt source signal.Field 1904E specifies whether the interrupt signal is edge triggered or level sensitive. Use ofTM 1904E inregister 1904 is discussed below in detail. -
FIG. 23 provides various fields that are used in IRQ control register(s) 1901, which are interrupt control registers for IRQ sources. MK-Read only fields 1901A and 1901G are copies of the mask bits fromregister 1903. Interrupt Request Sent (“IRS”)-ReadOnly fields 1901B and 1901I are set whenMP 240 reads the corresponding interrupt source as the prioritized interrupt fromregister 1905. Interrupt Request Pending (“IRP”)-ReadOnly fields IRS 1901B or 1901I are set,IRP IRP - Register(s) 1901 also include trigger mode TM values 1901E and 1901K that specify the mode of the interrupt source signals.
Field TM -
Fields MP 240 to a corresponding interrupt source. This field specifies a vector address to firmware and specifies the priority of the interrupt with the interrupt source. The vector field in 1905B is updated when an entry in the interrupt control register array (described below) that corresponds to an active interrupt is seen as having a higher priority while the register array is being scanned. -
FIG. 24 shows the field used byregister 1902.Field 1902A, when valid indicates that there is a fast interrupt request asserted toMP 240.Field 1902A is cleared whenregister 1902 is read. -
FIG. 25 shows the fields used inregister 1907.Register 1907 is a control register showing when an interrupt has been sent.Field 1907A is used for a FIQ source andfield 1907B is used for IRQ sources, as described below. -
FIG. 26 shows the fields forregister 1906 used for pending interrupts.Field 1906A is used for an FIQ source andfield 1906B is used for IRQ sources, as described below. -
FIG. 27 shows a functional block diagram ofsystem 2000 used byIC module 207, in various adaptive aspects of the present invention. -
Input signal 1608 from a FIQ source is sent tomodule 2005.Module 2005 selects either the FIQ source signal, or a TestSource signal depending on the state ofICIntTestControl 2017. If the FIQ source signal is selected, then it is synchronized by raw interruptsynchronization module 2006. The synchronized signal is sent for FIQ registration toFIQ registration module 2007.Module 2007 includesregisters -
Signal 1607 is sent to mask module 2004 (that includes register 1903) and toFIQ IC module 2008.Mask module 2004 sends the mask (1903A) toFIQ IC module 2008, which then sends a signal to interruptgeneration module 2009. Interruptgeneration module 2009 also receives input fromIRQ Scanner 2011 and based upon the priority of the request, an interrupt is generated, forexample FIQn 1611,SysInt 1614 andIRQn 1613. - When
FIQIRP 1904C is set, then a fast interrupt is asserted. The interrupt request signal remains asserted untilMP 240 readsregister 1902. Whenregister 1902 is read,FIQn signal 1611 is de-asserted by settingFIQIRS 1904B and clearingFIQIRP 1904C. - In one aspect, another interrupt request cannot be made until
FIQIRS 1904B is cleared as follows: - If FIQ interrupt source as defined by
TM 1904E is level sensitive then the firmware ensures that the FIQ interrupt source is de-asserted and then an end of interrupt (“EOI”) is sent toIC 207 to clear theFIQIRS 1904B state; or - If the FIQ interrupt source as defined by
TM 1904E is edge triggered, the firmware need only readregister 1902,FIQIRP 1904C is cleared andFIQIRS 1904B is set. In edge triggered mode, FIQIRS clears when the interrupt source de-asserts. The next interrupt does not occur until the interrupt source signal de-asserts, and asserts again. - Incoming IRQESOURCE signals 1609 is received by
module 2002.Module 2002 selects either the IRQESOURCE signal, or TestSource signals depending on the state ofICTestControl 2015. If the IRQESOURCE signals are selected, then they are synchronized by raw interruptsynchronization module 2003. The synchronized signals are sent for IRQ registration toIRQ registration module 2013. IRQ interruptregistration module 2013 sets thefield 1906B inregister 1906.Signal 1607 is sent to mask module 2004 (that includes register 1903) and to IRQ InterruptRegistration Module 2013.Mask module 2004 sends the mask (1903A) to IRQ InterruptRegistration module 2013, which then sends signals to the IRQ Priority Evaluation And Scanner module 2011 (also referred herein as “IRQ Scanner 2011”). It is noteworthy that firmware may mask an interrupt before it is sent toMP 240. This de-registers the interrupt by clearingfield 1906B. - For each possible interrupt input, information regarding that interrupt is stored in IRQ
register control array 1901.Register control array 1901 includes vector values (1901F and 1901L), TM values (1901E and 1901K) and PLR values (1901D and 1901J) for each interrupt source, i.e. even and odd source.MP 240 may write the foregoing values inregister control array 1901. Vector values 1901F and 1901L provide the offset for firmware to access the interrupt handler (Not shown) and establish the priority of the interrupt within plural interrupt sources, for example, 16 IRQ sources. It is noteworthy that the invention is not limited to 16 IRQ sources. In one aspect, the highest vector value is given the highest priority. When one of the registers inregister control array 1901 is read then, the mask, IRS, IRP, Vector, TM and PLR values are also read at the same time.Output 2012 fromregister control array 1901 is sent toIRQ scanner 2011 that scans the vector values, as described below.IRQ scanner 2011 provides aninput 2011A to interruptgenerator 2009 that generatesIRQn 1613. - When
MP 240 retrieves the IRQ interrupt fromIC module 207 it readsregister 1905 which sets the IRQIRS bit (1901B or 1901I) associated with the interrupt source inregister 1905, which prevents the same interrupt source from generating another interrupt until the IRQIRS bit is cleared. - In one aspect, another interrupt from the same source cannot be made until IRQIRS (1901B or 1901I) is cleared as follows:
- If the IRQ interrupt source is defined by
TM IC 207 to clear theIRQIRS 1901B or 1901I state; or - If the IRQ interrupt source is defined by
TM register 1905.IRQIRP IRQIRS 1901B or 1901I is set. In edge triggered mode, IRQIRS clears when the interrupt source de-asserts. The next interrupt does not occur until the interrupt source signal de-asserts, and asserts again. -
FIG. 28 is a flow diagram for IRQ generation with respect to the functional diagram ofFIG. 27 and the various registers described above. - In step S2800, an
IRQ signal 1609 is received from an interrupt source. - In step S2801,
IRQ signal 1609 is selected bylogic 2002. - In step S2802, valid IRQ signal 1609A is synchronized by
synchronization module 2003. - In step S2803, synchronized IRQ signal 1609B is registered by IRQ interrupt
registration module 2013. - In step S2804, registers in
register control array 1901 are read. - In step S2805, vector values are scanned (discussed below with respect to
FIG. 29 ). - In step S2806, based on the vector values, output interrupt
signal 1613 is sent toMP 240. -
FIG. 29 is a flow diagram showing executable process steps used byIRQ scanner 2011. - In step S2900,
IRQ scanner 2011 receivesregister values 2012 fromregister control array 1901 andIRQESOURCE 2013A from IRQ interruptregistration module 2013.IRQ scanner 2011 receives vector values fromregister control array 1901.IRQ scanner 2011 examines each interrupt during every interrupt cycle - In step S2901, the process determines if an interrupt is being sent sent as used here includes “pending” interrupts). If an interrupt is being sent (or pending), then in step S2902,
IRQ scanner 2011 compares the vector values of the interrupt being sent (or pending) with the scanned vector values of every other active interrupt input in a given interrupt cycle. - In step S2903,
IRQ scanner 2011 replaces the previous vector values if the most current vector values have higher priority. - If an interrupt is not being sent (or pending) in step S2901, then in step S2904,
IRQ scanner 2011 loads the current vector values from an active interrupt input from S2901 and the process moves to step S2902. -
FIG. 30 shows a state diagram for interrupt control, according to one aspect of the present invention. It is noteworthy, that although the state diagram ofFIG. 30 shows that it is for IRQ interrupts, the same will also apply for FIQ interrupts. State diagram includes threestates State 3000 is for receiving an interrupt request.State 3001 is an interrupt pending state andstate 3002 is an interrupt sent state. Based on the foregoing discussions regardingFIGS. 16-29 , the state transitions of state diagram inFIG. 30 are self-explanatory. - In one aspect of the present invention, a fast interrupt scheme is provided so that for critical interrupts,
MP 240 does not have to wait. - In another aspect of the present invention, interrupt priority is established efficiently by a scanning process.
- In yet another aspect of the present invention, firmware can change priority and mask interrupts from any source, providing flexibility to a user and also optimizes
MP 240 usage. - In another aspect of the present invention, use of TM values prevents interlocking of interrupt service by
MP 240. -
History module 234 is a peripheral onAPB Bus 208 that records transaction information over eitherAHB Bus 236 and/orAPB Bus 208. The recorded information may be used for debugging and analyzing firmware and hardware problems.History module 234 is set up and initiated throughAPB Bridge 235 and information fromHistory module 234 is extracted throughAPB Bridge 235.History module 234 includes a buffer(s) (not shown) for reading and writing recorded information. -
FIG. 31 shows a top-level block diagram ofHistory Module 234 with plural input and output signals. -
FIGS. 32A-1 , 32A-2, 32A-3, 32A-4 and 32B provide a description of the input and output signals, respectively. -
FIG. 33 provides a listing of aregister map 3309 used byHistory Module 234.Register map 3309 includes various registers that are used for setting upHistory Module 234 recording and control conditions. The base address ofHistory Module 234 is specified inAPB bridge 235 and whenPSELABPHS 3108 is asserted toHistory Module 234, the base address has been detected byAPB bridge 235.History Module 234 decodesPADDR 1605 and PWRITE 1606 to select accessed memory mapped registers. -
FIG. 34 provides a table forregister 3300 with the various fields (3300A-3300J) to control and set upHistory Module 234.SelectMask 3300A field if set isolates certain components in system for monitoring and recording byHistory Module 234. Firmware can also filter read and/or write operations. By settingfields History Module 234. -
Field 3300J defines break point conditions forHistory Module 234. Break point conditions are those, which stop recording/monitoring byHistory Module 234. Field 3300I enables break points, while break point testing stops after a break point is detected, iffield 3300E is set. -
Trigger mode field 3300G specifies the number of entries made in aHistory Module 234 buffer after a break point condition is detected. -
FIG. 35 shows register 3500 that stores a history stack pointer (referred to as “HstryStkPtr” or “HSP”) 3501.HSP 3501 provides the address of the next entry at a given time, for either reading from, or writing to, thehistory module 234 buffer. -
HSP 3501 may be zero at the beginning of a recording session. Firmware has the flexibility to changeHSP 3501 values. In one aspect, firmware may set this value to zero.HSP 3501 allows the firmware to recover a recording regardless of the reason why a recording session stopped.HSP 3501 is incremented each time an entry is accessed from the history stack buffer. -
FIG. 36A showsregister 3603 that provides the address break point pattern for address break point testing.Field 3602 provides the address break point pattern for such break point testing. -
FIG. 36B shows a data/address break point pattern register 3600 (DataAdrBPPReg 3600) that stores break point data pattern (“BPData”)field 3601.BPDATA field 3601 is compared against a data and address break point condition. Based on the selected break point condition and the comparison a break point sets and recording byHistory Module 234 stops when the trigger mode is satisfied. -
FIG. 37 shows register 3700 that includes recordedAHB bus 236 information inhistory module 234 buffer. Whenregister 3700 is read,history stack pointer 3501 is incremented. -
FIG. 38 shows register 3800 that includes recordedAPB bus 208 address information (similar to register 3700).Register 3500 is incremented afterregister 3800 is read. -
FIG. 39 shows acontrol history register 3900 that includes recordedAHB bus 236 information.Register 3500 is incremented afterregister 3900 is read. -
FIG. 40 shows acontrol history register 4000 that includes recordedAPB bus 208 information.Register 3500 is incremented afterregister 4000 is read. -
FIG. 41 shows register 4100, which includesAHB bus 236 orAPB bus 208 data specified by the pointer value inregister 3500.Register 3500 is incremented afterregister 4100 is read. -
FIG. 42 shows register 4200 that includes a Clear History Stack Buffer (“CHSB”)field 4201. SettingCHSB field 4201 clearsHSP 3501.CHSB 4201 is set while zero data is being written tobuffers 4313 to 4315. -
FIG. 43 shows register 4300 that includes a “Set EnableRecord”field 4300A that may be set by firmware. Whenfield 4300A is set,History module 234 starts recording and the recording stops whenfield 4300A is cleared. -
FIG. 44 is a functional block diagram, ofhistory module 234 that will be described below with respective to various inventive aspects of the present inventions.History module 234 may be setup by firmware to perform its various function. Control information is written to register 3300. If a break point is desired for address and/or data, or address range, thenMP 240sets registers - To start
history module 234,field 4300A ofregister 4300 is set, that allows recording when signalsHREADY 307 orPENABLE 1607 are asserted. In one aspect of the present invention,history module 234 may record data simultaneously forbuses history module 234 to write inbuffers FIG. 44 shows three buffers for address, control and data information, the invention is not limited to the number of buffers used byhistory module 234. For example, only one or more buffers may be used to implement the adaptive aspects of the present invention. -
History module 234 continues to make entries until a break point (or event) is reached as defined by fields 3300I and 3330J inregister 3300 orfield 4300A is cleared by firmware, as discussed below in detail. - Valid Recorded Entry: Before recording, buffers 4313, 4314 and 4315 are cleared by firmware issuing a “clear History
stack Buffer Access 4201 command. All valid entries inbuffer 4314 are cleared. When recording,field 4201 is toggled each time an entry is made in buffers 4313-4315. - Break Point and Break Point Interrupt: Firmware can set field 3300I to enable a break point defined by break
point condition field 3300J.Event control module 4336 generatesfield 4300A value that is sent to flip-flop module 4323. Firmware can setfield 4300A value that enables flip-flop module 4323.History module 234 tests forbreak point condition 3300J in every clock cycle as defined by firmware. - When
history module 234 detects the defined break point condition then it stops recording bus transactions based onTM value 3300G and an interrupt may be generated, as discussed below. After a break point is detected,history module 234 stops recording and based onfield 3300E setting either continues to test for the break condition or stops testing for the break point condition. - An interrupt is generated based on the detection of the break point condition and if
field 3300F is set, after the interrupt source is enabled inIC module 207. - Break points may be set for address and/or data or address range based on
fields field 4300A to trigger a firmware break point, if a firmware break point condition is set in 3300J. - Clock Slam: When a break point condition is detected, and if
field 3300D is enabled (Enable clock Slam),history module 234 assertssignal ClkSlam 4343 to clock control via flip-flop module 4340.Break point condition 3300J′, which indicates that a break point condition has occurred, is sent toevent control module 4336 withtrigger mode value 3300G. This stops all the clocks insystem 200. This signal remains asserted untilsystem 200 is reset. This allowssystem 200 component information to be scanned out for analysis and diagnosis using standard debugging tools. - Filter Control:
History module 234 can selectively filter outsystem 200 components based onfilter control command 4324.Filter control command 4324 is based onselect mask field 3300A inregister 3300. Iffield 3300A is set then transactions related to, a specific peripheral(s) or slave (depending on the bus) is not recorded. -
Trigger mode field 3300G specifies the number of entries that are made in buffers 4313-4315 after a break point condition has been detected. In one aspect,field 3300G may be set so thathistory module 207 stops recording within a single clock cycle, or may continue to record a pre-defined amount of data before stopping. -
History module 234 starts and stops recording based onregister 4300 fields.Field 4300A when set to “EnableRcrdReg”, allowshistory module 234 to record. Setting “Clear Enable Record and Status” bit infield 4300A stopshistory module 234 from recording and break point testing, unless specified otherwise by firmware. - Bus (208 and 236) transactions are recorded when EnableRcrdReg is set.
Mux 4324 samples signalsHREADY 307 andPENABLE 1603. The signals indicate that a valid transaction is on the bus that may be recorded unless masked byfield 3300A. -
History stack pointer 3500, as shown inFIG. 35 , keeps track of where the next entry in buffer 4313-4315 will be made whilehistory module 234 is recording. When an entry is made in buffers 4313-4315,pointer 3501 is updated. Whenhistory module 234 stops making entries in buffers 4313-4315, the value of 3501 points to the last entry plus one. - As stated above, when recording stops,
history stack pointer 3501 points to the “oldest recorded entry”.MP 240 bus master (not shown) reads thehistory address buffer 4313 andhistory module 234 places the recorded entry into register 4300 (FIG. 43 ) and history stack pointer now pointing to the last entry read is incremented by one.APB bridge 235 returns the recorded entry toMP 240 bus master and it increments it's read count. Afterbuffer 4313 is read, the same process is applied tobuffers -
FIG. 45 shows a flow diagram of executable process steps inhistory module 207 for recording bus transactions insystem 200, according to one aspect of the present invention. - Turning in detail to
FIG. 45 , is step S4500, the process sets up registers for recording.Field 4300A is set to “EnableRcrdReg” (also referred to as “EnRcrdReg” inFIG. 43 ) to record transactions. - In step S4501, the process determines if
field 3300E is set to enable any break point testing.Field 3300J inregister 3300 may be used to specify break point conditions. - In step S4502, transactions are recorded. Bus (208 and 236) transactions are recorded when
EnableRcrdReg field 4300 is set. SignalsHREADY 307 andPENABLE 1603 are sampled byMux 4324. The signals indicate that a valid transaction is on the bus that may be recorded unless masked byfield 3300A. When an entry is made in buffers 4313-4315,pointer 3501 is updated. Whenhistory module 234 stops making entries in buffers 4313-4315, the value of 3501 points to the last entry plus one. - In step S4503, based on whether break point condition testing is enabled,
history module 234 tests for break point conditions. Based on the setting ofEnBPStp 3300E,history module 234 may continue or stop break point condition testing after a particular break point is encountered. - In step S4504, the process determines the value of
TM field 3300G. This sets the amount of data that is to be recorded after a break point condition is detected. It is noteworthy that steps S4502-4504 may occur simultaneously. - In step S4505, recording is stopped and
field 4300A is cleared. - In step S4506, recorded information is extracted.
MP 240 bus master (not shown) reads thehistory address buffer 4313 andhistory module 234 places the recorded entry into register 4327 (FIG. 44A ) andhistory stack pointer 3501 is incremented by one.APB bridge 235 returns the recorded entry toMP 240 bus master and it increments its' read count. Afterbuffer 4313 is read, the same process is applied tobuffers - In one aspect of the present invention,
history module 234 provides visibility to transactions on theinternal AHB Bus 236 orAPB Bus 208. - In one aspect of the present invention,
history module 234 selects specific slave or peripheral transactions for recording based on a slave or peripheral mask. This allows selective monitoring ofsystem 200 components. - In yet another aspect of the present invention, the process described above provides break point conditions for stopping
History module 234 recording. However, external break point signal may be continually provided after recording stops. In addition, break point conditions may be provided for an Address/Data break point and an Address Range break point. - In another aspect of the present invention, an external analyzer is not required to record bus transactions. This saves pins and the effort required connecting
system 200 to an external device so that its components can be monitored. -
DSPIM 210 provides an interface for communication betweenMP 240 andDSP 229 as a bridge betweenAPB bus 208 andDSPAHB bus 233.DSPIM 210 provides an IN/OUT register file for passing command and status parameters betweenMP 240 andDSP 229.FIGS. 46 and 47 show registers that are used forMP 240 andDSP 210 to communicate with each other.Register APB bus 208 andDSPAHB bus 233.Registers MP 240 andDSP 229.Register 4600 can be read and written byMP 240.MP 240 can only readregister 4700, whileDSP 229 may read or write. An attempt byMP 240 to write intoregister 4700 results in declaration of “address exception” byDSPIM 210. Contents ofregisters -
MP 240 writes inregister 4600 and interrupt is sent toDSP 229.MP 240 setsfield 4900C instatus register 4900, which generates an interrupt toDSP 229. -
FIG. 50 shows a flow diagram of communication between MP240 andDSP 229 using IN/Outregisters - In step S5000,
MP 240 send information toDSP 229. - In step S5001, MP240 writes the information (or address of the information) in
register 4600. - In step S5002,
MP 240 setsfield 4900C and generates an interrupt forDSP 229. - In step S5003,
DSP 229 services the interrupt by readingregister 4600 and clearsfield 4900C. - In step S5004,
register 4600 is again available forMP 240 to write intoregister 4600. -
DSPIM 210 is operationally coupled tomemory module 212 viainterface 230. MP240 andDSP 229 for storing firmware control instructions and any other information may usememory module 212.Interface 230 allowsAPB bus 208 to accessmemory module 212 whileDSPIM 210 executes firmware instructions. -
Memory module 212 is shared usingregisters semaphore register 5100 shown inFIG. 51 .Semaphore register 5100field 5100A provides firmware interlock whenMP 240 acquires the semaphore.Semaphore register 5100field 5100B provides hardware interlock whenMP 240 acquires the semaphore.DSP 229 cannot execute a write access to any register exceptregister 5100 or a status register. -
Memory module 212 uses anindirect access register 5200 that facilitates communication betweenDSP 229 andMP 240 without using any counters.Memory module 212 uses at least a FIFO buffer from where data may be read and/or written.Memory module 212 uses register 5300 (FIG. 53 ) that includes FIFO data.MP 240 sets upfield 5200A that allows indirect access. Field 5200G indicates the starting address ofmemory module 212. Each access to register 5300 updates field 5200G. - An indirect read transaction may be initiated by setting up
field time register 5300 is accessed, the address infield 5200F is updated. Iffield 5200C is set then it indicates that the read access is a sequence of continual read accesses that keepsmemory module 212 FIFO (not shown) full. - An indirect write access may be initiated by setting
field register 5300 is updated with data that is written intomemory module 212. Each time data is written intoregister 5300,DSPIM 210 writes data intomemory module 212. - One advantage of providing the mail-box” concept is that no write conflict occurs between
MP 240 andDSP 229. - In one aspect,
MP 240 and/orDSP 229 do not have to gain ownership and then relinquish ownership (clear) of any registers to communicate with each other. This saves performance time and improves overall efficiency, because the registers are dedicated. - In another aspect of the present invention, indirect access is available to access
memory module 212. - In another aspect of the present invention, the IN/Out mailbox environment may be used to efficiently run test cases.
MP 240 using Assembler or any other language may run test cases. A sub-set of test instructions may be executed byDSP 229. The mailboxes have a buffer (not shown) that keeps a real-time picture of a test case. When the test is complete, mail-boxes are unloaded and a report may be generated that can be used for bug fixing and analysis. - Although the present invention has been described with reference to specific embodiments, these embodiments are illustrative only and not limiting. Many other applications and embodiments of the present invention will be apparent in light of this disclosure and the following claims.
Claims (12)
1. An embedded disk controller, comprising:
a main processor in communication with a first bus;
a second processor in communication with a second bus;
an external bus controller (EBC) in communication with the first bus and in communication with external devices via an external bus interface; and
a history module that is located in the embedded disk controller, that communicates with the first bus and the second bus, and that at least one of monitors transaction information of one of said external devices and masks information of one of said external devices via the EBC based on setup information,
wherein the EBC and the history module are located on at least one of an integrated circuit (IC) and a system on a chip (SOC) with the embedded disk controller.
2. The embedded disk controller of claim 1 further comprising an interrupt controller module that generates a fast interrupt to the main processor based on a fast interrupt request (FIQ).
3. The embedded disk controller of claim 1 wherein the EBC includes at least one of a segment descriptor register and a device range register, wherein the embedded disk controller programs timing characteristics of the external devices via the segment descriptor register and the main processor accesses address space of the external devices via the device range register.
4. The embedded disk controller of claim 1 wherein the history module records transaction information on at least one of the first bus and the second bus based on a register map.
5. The embedded disk controller of claim 4 wherein the register map stores a break point condition value that is set by the first processor and the history module stops recording the transaction information based on the break point condition value.
6. The embedded disk controller of claim 5 wherein the history module stores a trigger mode field value, wherein the history module records a predetermined number of entries after the break point condition value reaches a threshold based on the trigger mode field value.
7. The embedded disk controller of claim 1 wherein the history module at least one of:
stores a read mask field value and stops reading operations based on the read mask field value; and
stores a write mask field value and stops write operations based on the write mask field value.
8. The embedded disk controller of claim 1 wherein the history module stores an enable clock slam field value and the history module generates a signal that stops clocks in the embedded disk controller based on the enable clock slam field value.
9. The embedded disk controller of claim 1 further comprising a servo controller that communicates with the second processor via a servo controller interface and provides real time servo controller information to the second processor.
10. The embedded disk controller of claim 1 wherein the second processor is a digital signal processor (DSP) that communicates with the first main processor via an interface.
11. The embedded disk controller of claim 2 wherein the interrupt controller module generates a regular interrupt based on a regular interrupt request (IRQ).
12. The embedded disk controller of claim 11 wherein the interrupt controller module includes an interrupt generation module that generates a fast interrupt when an FIQ is pending and processes an IRQ based on priority when an FIQ is not pending.
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US20040199718A1 (en) | 2004-10-07 |
WO2004081738A2 (en) | 2004-09-23 |
US7080188B2 (en) | 2006-07-18 |
US20040199695A1 (en) | 2004-10-07 |
US7853747B2 (en) | 2010-12-14 |
US7219182B2 (en) | 2007-05-15 |
US7870320B1 (en) | 2011-01-11 |
WO2004081738A3 (en) | 2005-12-15 |
US7457903B2 (en) | 2008-11-25 |
US20070226392A1 (en) | 2007-09-27 |
US20040199711A1 (en) | 2004-10-07 |
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