US20060119382A1 - Apparatus and methods for adjusting performance characteristics of programmable logic devices - Google Patents

Apparatus and methods for adjusting performance characteristics of programmable logic devices Download PDF

Info

Publication number
US20060119382A1
US20060119382A1 US11/006,420 US642004A US2006119382A1 US 20060119382 A1 US20060119382 A1 US 20060119382A1 US 642004 A US642004 A US 642004A US 2006119382 A1 US2006119382 A1 US 2006119382A1
Authority
US
United States
Prior art keywords
pld
circuit
programmable logic
logic device
supply voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/006,420
Inventor
Sergey Shumarayev
Rakesh Patel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tahoe Research Ltd
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US11/006,420 priority Critical patent/US20060119382A1/en
Assigned to ALTERA CORPORATION reassignment ALTERA CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PATEL, RAKESH, SHUMARAYEV, SERGEY Y.
Priority to EP05026293A priority patent/EP1670140A3/en
Priority to JP2005352310A priority patent/JP2006166458A/en
Priority to CNA2005101310699A priority patent/CN1797951A/en
Priority to US11/420,737 priority patent/US7986160B2/en
Priority to US11/420,736 priority patent/US20060202713A1/en
Publication of US20060119382A1 publication Critical patent/US20060119382A1/en
Priority to JP2011256197A priority patent/JP2012075168A/en
Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ALTERA CORPORATION
Assigned to TAHOE RESEARCH, LTD. reassignment TAHOE RESEARCH, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTEL CORPORATION
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008Arrangements for reducing power consumption
    • H03K19/0016Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/34Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003Modifications for increasing the reliability for protection
    • H03K19/00369Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724Structural details of logic blocks
    • H03K19/17732Macroblocks
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748Structural details of configuration resources
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778Structural details for adapting physical parameters
    • H03K19/17784Structural details for adapting physical parameters for supply voltage
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778Structural details for adapting physical parameters
    • H03K19/17792Structural details for adapting physical parameters for operating speed
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12Timing analysis or timing optimisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the inventive concepts relate generally to adjusting the performance of programmable logic devices (PLDs). More particularly, the invention concerns adjusting the supply voltage/power consumption of PLDs, as well as noise reduction and isolation in PLDs.
  • PLDs programmable logic devices
  • PLDs are ubiquitous electronic devices that provide flexibility to not only designers, but also end-users.
  • a designer may perform a relatively large number of design iterations by simply re-programming the PLD for each design.
  • the length and expense of the design cycle decreases compared to other alternatives.
  • the end-user may have a desired level of control over the functionality of a design that includes PLD(s).
  • PLDs include a relatively large number of transistors.
  • users demand ever higher performance, which results in larger operating frequencies. Consequently, the power consumption, power dissipation, die temperatures and, hence, power density (power dissipation in various circuits or blocks), of PLDs has tended to increase.
  • the upward march of the power density may make PLDs design and implementation impractical or failure-prone.
  • a PLD includes a circuit that controls a supply voltage of another circuit within the PLD.
  • the controlling circuit further filters noise within the PLD.
  • a PLD in another embodiment, includes a circuit that resides in a deep n-well in the PLD.
  • the circuit in the deep n-well couples to a variable impedance device.
  • the variable impedance device adjusts the supply voltage of the circuit in the deep n-well, thus adjusting its performance.
  • a method of configuring a PLD to implement an electronic circuit includes mapping the electronic circuit to functional resources within the PLD to generate a circuit to be implemented by the PLD. The method further includes identifying at least one critical circuit path in the circuit to be implemented by the PLD, and setting the supply voltage level of at least a portion of the critical circuit path.
  • a method of operating a PLD includes setting the supply voltage level of a circuit in the PLD to a voltage level, and determining whether a performance measure of the PLD meets a particular criterion. The method further includes adjusting the supply voltage level of the circuit depending on whether the performance measure of the PLD meets the criterion.
  • Another embodiment relates to a method of operating a PLD that is configured to function in a desired or prescribed operating environment. More specifically, the method includes setting the supply voltage level of a circuit in the PLD to a voltage level, and adjusting the supply voltage level of the first circuit depending on at least one characteristic of the operating environment of the programmable logic device (PLD).
  • PLD programmable logic device
  • FIG. 1 shows a general block diagram of a PLD according to an illustrative embodiment of the invention.
  • FIG. 2 illustrates a floor-plan of a PLD according to an exemplary embodiment of the invention.
  • FIG. 3 depicts a block diagram of an exemplary embodiment of programmable logic in a PLD according to the invention.
  • FIG. 4 shows a circuit arrangement for adjusting the supply voltage of a desired circuit in a PLD according to an exemplary embodiment of the invention.
  • FIG. 5 illustrates another circuit arrangement for adjusting the supply voltage of a desired circuit in a PLD according to an exemplary embodiment of the invention.
  • FIG. 6 depicts a circuit arrangement for reducing the noise level in a PLD according to an exemplary embodiment of the invention.
  • FIG. 7 shows another circuit arrangement for reducing the noise level in a PLD according to an exemplary embodiment of the invention.
  • FIG. 8 illustrates an arrangement for providing a flexible mechanism for adjusting the performance of the various parts of a PLD according to an exemplary embodiment of the invention.
  • FIGS. 9A-9C depict circuit arrangements for distributing and generating power supply voltages in PLDs according to exemplary embodiments of the invention.
  • FIG. 10 shows an example of using n-wells to isolate noise-sensitive circuits in a PLD according to an illustrative embodiment of the invention.
  • FIG. 11 illustrates various software modules that PLD computer-aided design (CAD) software according to illustrative embodiments of the invention uses.
  • CAD computer-aided design
  • FIG. 12 depicts a flow diagram for a PLD CAD software according to an exemplary embodiment of the invention.
  • FIG. 13 shows a block diagram of circuitry within a PLD according to exemplary embodiments of the invention to adjust, program, or set the supply voltage levels of desired parts of the PLD.
  • FIG. 14 illustrates a circuit arrangement according to exemplary embodiments of the invention for adjusting supply voltage levels within a PLD in response to an external source.
  • FIG. 15 depicts a circuit arrangement for adjusting supply voltage level(s) within a PLD according to exemplary embodiments of the invention.
  • inventive concepts contemplate apparatus and associated methods for PLDs that feature adjustable supply voltage (and, hence, power consumption and performance), reduced noise levels, and noise isolation.
  • the inventive concepts help to overcome excessive power density levels that conventional PLDs suffer.
  • one may adjust the performance level of a desired portion, circuit, or block (or all circuits and blocks), of a PLD according to the invention.
  • one may adjust the performance by programming the supply voltage and the attendant power dissipation of the circuitry within the PLD with a desired level of granularity, ranging from individual circuit blocks, all the way to the entire PLD circuitry.
  • the inventive concepts contemplate controlling the supply voltage and power consumption of one or more circuits or blocks of circuits within the PLD by using a variable impedance circuit.
  • a variable impedance circuit may use the variable impedance circuit to form a filter that, simultaneously with the adjustment of the power consumption, tend to reduce the noise levels present within the PLD.
  • the reduced noise levels help to protect sensitive circuitry within the PLD from adverse effects of electrical noise.
  • noise-sensitive circuitry within the PLD by using deep n-well structures within the PLD that help to isolate the sensitive circuitry from sources of electrical noise.
  • the inventive concepts provide the following benefits over traditional implementations. First, they allow trading off performance and power consumption or optimizing the performance-power consumption tradeoff. Second, one may selectively set, program, or adjust the supply voltage and power consumption in critical circuit paths or parts of the PLD so as to increase their performance as desired. Conversely, one may selectively set, program, or adjust the supply voltage and power consumption in non-critical circuit paths or parts of the PLD to levels commensurate with their desired performance.
  • FIG. 1 shows a general block diagram of a PLD 103 according to an illustrative embodiment of the invention.
  • PLD 103 includes configuration circuitry 130 , configuration memory 133 , control circuitry 136 , programmable logic 106 , programmable interconnect 109 , and I/O circuitry 112 .
  • PLD 103 may include test/debug circuitry 115 , one or more processors 118 , one or more communication circuitry 121 , one or more memories 124 , one or more controllers 127 , as desired.
  • FIG. 1 shows a simplified block diagram of PLD 103 .
  • PLD 103 may include other blocks and circuitry, as persons of ordinary skill in the art understand. Examples of such circuitry include clock generation and distribution circuits, redundancy circuits, and the like. Furthermore, PLD 103 may include, analog circuitry, other digital circuitry, and/or mixed-mode circuitry, as desired.
  • Programmable logic 106 includes blocks of configurable or programmable logic circuitry, such as look-up tables (LUTs), product-term logic, multiplexers, logic gates, registers, memory, and the like.
  • Programmable interconnect 109 couples to programmable logic 106 and provides configurable interconnects (coupling mechanisms) between various blocks within programmable logic 106 and other circuitry within or outside PLD 103 .
  • Control circuitry 136 controls various operations within PLD 103 .
  • PLD configuration circuitry 130 uses configuration data (which it obtains from an external source, such as a storage device, a host, etc.) to program or configure the functionality of PLD 103 .
  • the configuration data typically reside in configuration memory 133 .
  • the configuration data determine the functionality of PLD 103 by programming programmable logic 106 and programmable interconnect 109 , as persons skilled in the art with the benefit of the description of the invention understand.
  • I/O circuitry 112 may constitute a wide variety of I/O devices or circuits, as persons of ordinary skill in the art who have the benefit of the description of the invention understand. I/O circuitry 112 may couple to various parts of PLD 103 , for example, programmable logic 106 and programmable interconnect 109 . I/O circuitry 112 provides a mechanism and circuitry for various blocks within PLD 103 to communicate with external circuitry or devices.
  • Test/debug circuitry 115 facilitates the testing and troubleshooting of various blocks and circuits within PLD 103 .
  • Test/debug circuitry 115 may include a variety of blocks or circuits known to persons of ordinary skill in the art who have the benefit of the description of the invention.
  • test/debug circuitry 115 may include circuits for performing tests after PLD 103 powers up or resets, as desired.
  • Test/debug circuitry 115 may also include coding and parity circuits, as desired.
  • PLD 103 may include one or more processors 118 .
  • Processor 118 may couple to other blocks and circuits within PLD 103 .
  • Processor 118 may receive data and information from circuits within or external to PLD 103 and process the information in a wide variety of ways, as persons skilled in the art with the benefit of the description of the invention appreciate.
  • One or more of processor(s) 118 may constitute a digital signal processor (DSP). DSPs allow performing a wide variety of signal processing tasks, such as compression, decompression, audio processing, video processing, filtering, and the like, as desired.
  • DSP digital signal processor
  • PLD 103 may also include one or more communication circuitry 121 .
  • Communication circuitry 121 may facilitate data and information exchange between various circuits within PLD 103 and circuits external to PLD 103 , as persons of ordinary skill in the art who have the benefit of the description of the invention understand.
  • communication circuitry 121 may provide various protocol functionality (e.g., Transmission Control Protocol/Internet Protocol (TCP/IP), User Datagram Protocol (UDP) etc.), as desired.
  • communication circuitry 121 may include network (e.g., Ethernet, token ring, etc.) or bus interface circuitry, as desired.
  • PLD 103 may further include one or more memories 124 and one or more controller(s) 127 .
  • Memory 124 allows the storage of various data and information (such as user-data, intermediate results, calculation results, etc.) within PLD 103 .
  • Memory 124 may have a granular or block form, as desired.
  • Controller 127 allows interfacing to, and controlling the operation and various functions of circuitry outside the PLD.
  • controller 127 may constitute a memory controller that interfaces to and controls an external synchronous dynamic random access memory (SDRAM), as desired.
  • SDRAM synchronous dynamic random access memory
  • PLD 103 may include analog or mixed-mode circuitry 139 , sometimes known as analog or mixed-mode intellectual property (IP) blocks.
  • PLD 103 may include amplifiers, digital-to-analog converters, analog-to-digital converters, filters, and the like.
  • analog/mixed-mode circuits tend to exhibit sensitivity to noise.
  • inventive concepts help to isolate noise-sensitive circuitry from noise-generating circuitry.
  • inventive concepts include techniques that tend to reduce the noise levels present in PLDs.
  • FIG. 2 shows a floor-plan of a PLD 103 according to an exemplary embodiment of the invention.
  • PLD 103 includes programmable logic 106 arranged as a two-dimensional array.
  • Programmable interconnect 109 arranged as horizontal interconnect and vertical interconnect, couples the blocks of programmable logic 106 to one another.
  • PLDs according to the invention have a hierarchical architecture.
  • each block of programmable logic 106 in FIG. 2 may in turn include smaller or more granular programmable logic blocks or circuits.
  • One may adjust the supply voltage and power consumption or dissipation in each level of the hierarchical architecture of the PLD, as desired.
  • FIG. 3 shows a block diagram of an exemplary embodiment of programmable logic 106 in a PLD according to the invention.
  • Programmable logic 106 includes logic elements or programmable logic circuits 250 , local interconnect 253 , interface circuit 256 , and interface circuit 259 .
  • Logic elements 250 provide configurable or programmable logic functions, for example, LUTs, registers, product-term logic, etc., as persons of ordinary skill in the art who have the benefit of the description of the invention understand.
  • Local interconnect 253 provides a configurable or programmable mechanism for logic elements 250 to couple to one another or to programmable interconnect 109 (sometimes called “global interconnect”), as desired.
  • Interface circuit 256 and interface circuit 259 provide a configurable or programmable way for programmable logic 106 block of circuitry to couple to programmable interconnect 109 (and hence to other programmable logic 106 , as FIG. 2 shows).
  • Interface circuit 256 and interface circuit 259 may include multiplexers (MUXs), registers, buffers, drivers, and the like, as persons of ordinary skill in the art who have the benefit of the description of the invention understand.
  • MUXs multiplexers
  • the blocks in FIG. 1 e.g., programmable logic 106 , programmable interconnect 109 , etc.
  • one or more logic elements 250 within one or more programmable logic blocks 106 e.g., one or more interface circuits 256 and/or 259 , within one or more programmable logic blocks 106 ;
  • FIG. 4 shows a circuit arrangement for adjusting the supply voltage and, hence, the power consumption of a desired circuit in a PLD according to an exemplary embodiment of the invention. More specifically, the circuit arrangement in FIG. 4 shows a controlled PLD circuit 300 that includes control circuit 303 , PLD circuit 306 , and variable impedance device 309 .
  • circuit 303 In response to one or more signals not shown explicitly in FIG. 4 (such as a bias signal and configuration signals, described in connection with FIG. 13 ) circuit 303 applies a corresponding control signal (or signals, depending on the nature of variable impedance device 309 ) so as to cause adjustment of the supply voltage that variable impedance device 309 provides to PLD circuit 306 . Consequently, control circuit 303 can cause the adjustment of the power consumption (and other performance criteria, such as operating speed) of PLD circuit 306 .
  • signals not shown explicitly in FIG. 4 such as a bias signal and configuration signals, described in connection with FIG. 13
  • control circuit 303 applies a corresponding control signal (or signals, depending on the nature of variable impedance device 309 ) so as to cause adjustment of the supply voltage that variable impedance device 309 provides to PLD circuit 306 . Consequently, control circuit 303 can cause the adjustment of the power consumption (and other performance criteria, such as operating speed) of PLD circuit 306 .
  • Variable impedance device 309 couples the supply voltage, V DD , to PLD circuit 306 .
  • V DD supply voltage
  • PLD circuit 306 When variable impedance device 309 has a relatively high impedance, PLD circuit 306 conducts relatively little current, and has a nearly zero supply voltage. Thus, PLD circuit 306 effectively shuts down or enters an OFF state or sleep mode. In this state, PLD circuit 306 consumes nearly zero power.
  • variable impedance device 309 when variable impedance device 309 has a relatively low impedance, PLD circuit 306 receives nearly the voltage V DD as its supply voltage (minus any drop across variable impedance device 309 ). In this state, PLD circuit 306 typically has higher power consumption, but also higher speed. Thus, by varying the effective supply voltage of PLD circuit 306 between the two extremes of near-zero and near-VDD supply voltages, one may trade off its various performance measures, such as power consumption and speed.
  • PLD circuit 306 may constitute any desired region, block, circuitry, sub-block, or collection of each of those parts, of a PLD.
  • PLD circuit 306 may constitute one or more of the elements shown in FIGS. 1-3 , such as programmable interconnect 109 , logic elements 250 , etc., as desired.
  • control circuit 303 may operate under the supervision of one or more other parts of the PLD, or under the control of an external source, or a combination of internal and external sources, as desired.
  • Control circuit 303 causes the impedance of the variable impedance device to change.
  • the effective supply voltage provided to PLD circuit 306 varies.
  • the effective supply voltage of PLD circuit 306 affects its characteristics, such as operating speed, power consumption, and the like. By adjusting the supply voltage level for PLD circuit 306 , one may trade off its various characteristics, such as speed versus power consumption.
  • Variable impedance device 309 may constitute a desired type of device, depending on factors such as the particular PLD implementation, circuit and process technology, and the like, as persons of ordinary skill in the art who have the benefit of the description of the invention understand.
  • variable impedance device 309 may constitute a transistor.
  • FIG. 5 illustrates another circuit arrangement for adjusting the supply voltage of a desired circuit in a PLD according to an exemplary embodiment of the invention.
  • the circuit arrangement in FIG. 5 is similar to the circuit in FIG. 4 .
  • FIG. 5 uses a transistor 320 and, more particularly, a metal oxide semiconductor field effect transistor (MOSFET) transistor, as a particular type of variable impedance device.
  • MOSFET metal oxide semiconductor field effect transistor
  • transistor 320 may constitute a variety of devices, such as bipolar junction transistors (BJTs), bipolar hetero-junction transistor (BHT), and the like.
  • BJTs bipolar junction transistors
  • BHT bipolar hetero-junction transistor
  • transistor 320 may constitute a native transistor, as desired.
  • Native transistors may have a negative or small threshold voltage, V T , thus making biasing or driving transistor 320 easier in situations where a relatively small V DD results in a small headroom in the output voltage of control circuit 303 .
  • PLDs according to the invention may include noise-sensitive analog or mixed-mode circuitry.
  • One may use filtering techniques to help reduce the overall noise in the PLD or the noise level that the analog or mixed-mode circuitry experiences.
  • FIG. 6 depicts a circuit arrangement for reducing the noise level in a PLD according to an exemplary embodiment of the invention.
  • Controlled PLD circuit 300 in FIG. 6 is analogous to the circuit shown in FIG. 4 , and provides similar benefits.
  • the circuitry in FIG. 6 provides the capability of controlling the supply voltage and, hence, the performance, of PLD circuit 306 , as described above in detail.
  • PLD circuit 306 constitutes a circuit with relatively high sensitivity to noise, such as an analog or mixed-mode circuit.
  • the circuit arrangement in FIG. 6 includes capacitor 323 and capacitor 326 . Together with various impedances present in the circuit, each of those capacitors forms a filter. For example, capacitor 326 , together with the parallel impedance of variable impedance device 309 and PLD circuit 306 , forms a low-pass filter. By filtering higher frequencies, the low-pass filters tend to reduce the overall noise level that PLD circuit 306 experiences. Note that one may omit one of capacitors 323 and 326 , depending on factors such as the desired level of filtering, the size and value of components, and the like, as persons of ordinary skill in the art who have the benefit of the description of the invention understand.
  • FIG. 7 shows another circuit arrangement for reducing the noise level in a PLD according to an exemplary embodiment of the invention.
  • the circuit arrangement in FIG. 7 constitutes a more specific implementation of the circuit in FIG. 6 . More specifically, rather than a general variable impedance device 309 in FIG. 6 , the circuit arrangement in FIG. 7 uses transistor 320 .
  • Transistor 320 may generally constitute any of the devices described above with respect to FIG. 5 , as desired. Note that, as described above, one may omit one of capacitors 323 and 326 , depending on factors such as the desired level of filtering, the size and value of components, and the like, as persons of ordinary skill in the art who have the benefit of the description of the invention understand.
  • FIG. 8 shows an arrangement for providing a flexible mechanism for adjusting the performance of the various parts of a PLD 103 according to an exemplary embodiment of the invention.
  • PLD 103 includes one or more PLD circuit regions or “islands” 400 A- 400 C.
  • Each PLD circuit region 400 A- 400 C includes one or more controlled PLD circuits 300 , as described above.
  • Each of PLD circuit regions 400 A- 400 C may receive one or more power supply voltages, labeled as V DD1 -V DDN .
  • PLD circuit region 400 A receives V DD1
  • circuit region 400 B receives V DD1 -V DD3
  • circuit region 400 C receives V DDN .
  • Each of controlled PLD circuits 300 can adjust the supply voltage provided to its respective PLD circuit 306 (see, for example, FIG. 4 ), as described above in detail.
  • each of PLD circuit regions 400 A- 400 C By assigning a desired set of power supply voltages to each of PLD circuit regions 400 A- 400 C, one may adjust the supply voltage and power consumption of circuitry within the circuit regions. Furthermore, by including a desired set of controlled PLD circuits 300 within a given circuit region 400 A- 400 C, one may match the type of supply voltage adjustment in each circuit region 40 OA- 400 C with one or more suitable controlled PLD circuits 300 .
  • the arrangement in FIG. 8 provides a flexible mechanism for allocating various PLD resources to implementing an appropriate part of the user's design or system so as to provide an efficient implementation with improved performance adjustment capabilities and better overall performance. (e.g., speed-power consumption tradeoff).
  • PLD 103 may generate power supply voltages internally, as desired.
  • FIGS. 9A-9C show circuit arrangements for distributing and generating power supply voltages in PLDs according to exemplary embodiments of the invention.
  • PLD 103 simply uses the external power supply voltages that it receives, e.g., V DD1 -V DDN .
  • PLD 103 may use a power distribution and supply voltage adjustment scheme, such as the arrangement in FIG. 8 .
  • PLD 103 receives power supply voltages V DD1 -V DDN .
  • PLD 103 may regulate one or more of the power supply voltages to generate one or more internal power supply voltages.
  • PLD 103 may then use the external and the internally generated powers supply voltages in a power distribution and supply voltage adjustment scheme, e.g., as shown in FIG. 8 .
  • PLD 103 uses voltage regulator 450 to generate internal power supply voltage V DD2 ′ from external power supply voltage V DD2 .
  • PLD 103 receives power supply voltages V DD1 -V DDN .
  • PLD 103 may use one or more charge pumps 453 to generate one or more internal power supply voltages.
  • PLD 103 may then use the external and the internally generated powers supply voltages in a power distribution and supply voltage adjustment scheme, e.g., as shown in FIG. 8 .
  • PLD 103 uses charge pump 453 to generate internal power supply voltage V DD1 ′ from external power supply voltage V DD1 .
  • Internal power supply voltage V DD1 ′ has a higher voltage level than V DD1 .
  • the inventive concepts include techniques for isolating noise-sensitive circuits from noise-generating circuitry with the PLD. More particularly, in PLDs fabricated using CMOS technology, various PLD circuits typically reside in a number of deep n-wells. By strategically placing noise-sensitive circuits in isolated n-wells, one may shield or isolate the noise-sensitive circuits from sources of noise. Thus, one may provide islands within the PLD, each with its own supply voltage, power consumption, noise generation, and noise isolation characteristics. The islands provide a mechanism in PLDs according to the invention for providing a flexible implementation of a user's design or system.
  • FIG. 10 shows an example of using n-wells to isolate noise-sensitive circuits in a PLD according to an illustrative embodiment of the invention.
  • the PLD resides in substrate 500 .
  • Substrate 500 includes deep n-wells 503 , 506 , and 509 .
  • Each of deep n-wells 503 , 506 , and 509 may include a variety of PLD circuitry, such as the circuits shown in FIGS. 1-3 .
  • circuitry with relatively high noise sensitivity labeled as 506 A
  • a PLD that includes circuits that generate moderate amounts of noise
  • 506 C circuits that produce relatively high levels of noise
  • circuits 506 A, 506 B, and 506 C in deep n-wells 503 , 506 , and 509 , respectively.
  • Noise and interference tends to decrease by the virtue of placing noise-sensitive circuit 506 A farthest from the relatively high levels of noise that circuit 506 C generates, but nearer to the moderate levels of noise that circuit 506 B produces.
  • deep n-wells represent an illustrative construct in a PLD fabrication technology.
  • the factors include the type and characteristics of the technology and the devices and constructs available, the desired design and performance specifications, cost, complexity, area efficiency, and the like.
  • SOI circuits tend to provide isolation between transistors because of the insulator layer (typically silicon dioxide).
  • SOI circuits provide a mechanism for isolating noise-sensitive circuits from noise-generating circuits of the PLD.
  • FIG. 11 depicts various software modules that PLD computer-aided design (CAD) software according to illustrative embodiments of the invention uses.
  • the modules include design-entry module 550 , synthesis module 553 , place-and-route module 556 , and verification module 559 .
  • Design-entry module 550 allows the integration of multiple design files.
  • the user may generate the design files by using design-entry module 550 or by using a variety of electronic design automation (EDA) or CAD tools (such as industry-standard EDA tools), as desired.
  • EDA electronic design automation
  • CAD tools such as industry-standard EDA tools
  • the user may enter the design in a graphic format, a waveform-based format, a schematic format, in a text or binary format, or as a combination of those formats, as desired.
  • Synthesis module 553 accepts the output of design-entry module 550 . Based on the user-provided design, synthesis module 553 generates appropriate logic circuitry that realizes the user-provided design. One or more PLDs (not shown explicitly) implement the synthesized overall design or system.
  • Synthesis module 553 may also generate any glue logic that allows integration and proper operation and interfacing of various modules in the user's designs. For example, synthesis module 553 provides appropriate hardware so that an output of one block properly interfaces with an input of another block. Synthesis module 553 may provide appropriate hardware so as to meet the specifications of each of the modules in the overall design or system.
  • synthesis module 553 may include algorithms and routines for optimizing the synthesized design. Through optimization, synthesis module 553 seeks to more efficiently use the resources of the one or more PLDs that implement the overall design or system. In some embodiments, synthesis module 553 may identify critical paths within the synthesized design or system. Synthesis module 553 provides its output to place-and-route module 556 .
  • Place-and-route module 556 uses the designer's timing specifications to perform optimal logic mapping and placement.
  • the logic mapping and placement determine the use of routing resources within the PLD(s). In other words, by use of particular programmable interconnects with the PLD(s) for certain parts of the design, place-and-route module 556 helps optimize the performance of the overall design or system.
  • place-and-route module 556 helps to meet the critical timing paths of the overall design or system.
  • Place-and-route module 556 optimizes the critical timing paths to help provides timing closure faster in a manner known to persons of ordinary skill in the art with the benefit of the description of the invention.
  • the overall design or system can achieve faster performance (i.e., operate at a higher clock rate or have higher throughput).
  • place-and-route module 556 adjusts the supply voltage and power consumption and the noise performance or exposure of a portion of or all of the PLD(s) that implement the design or system. Place-and-route module 556 may do so automatically, according to user-specified criteria, or a combination of the two. Place-and-route module 556 may use the user-specified criteria (for example, performance specifications, such as power dissipation, noise exposure or performance, speed, and/or current-drive capability). In addition, or instead, place-and-route module 556 may use the information about critical paths within the design or system to adjust the supply voltage(s), physical placement so as to reduce noise generation and exposure, and power consumption of parts or all of the design or system, as desired.
  • performance specifications such as power dissipation, noise exposure or performance, speed, and/or current-drive capability
  • place-and-route module 556 may adjust the supply voltage and power consumption of the critical parts of the design or system so as to achieve higher performance.
  • Place-and-route module 556 may take into account power dissipation criteria (e.g., maximum power density) so as to trade off power and performance, as desired.
  • Place-and-route module 556 provides the optimized design to verification module 559 .
  • Verification module 559 performs simulation and verification of the design.
  • the simulation and verification seek in part to verify that the design complies with the user's prescribed specifications.
  • the simulation and verification also aim at detecting and correcting any design problems before prototyping the design.
  • verification module 559 helps the user to reduce the overall cost and time-to-market of the overall design or system.
  • Verification module 559 may support and perform a variety of verification and simulation options, as desired.
  • the options may include design-rule checking, functional verification, test-bench generation, static timing analysis, timing simulation, hardware/software simulation, in-system verification, board-level timing analysis, signal integrity analysis and electromagnetic compatibility (EMC), formal netlist verification, noise generation and exposure, and power-consumption estimation, as desired.
  • EMC electromagnetic compatibility
  • FIG. 12 illustrates a flow diagram for a PLD CAD software according to an exemplary embodiment of the invention.
  • the PLD CAD shown in FIG. 12 incorporates the choice of supply voltage and power consumption for each region of the PLD into a timing-driven place-and-route CAD system. Note that, as desired, one may include criteria for noise generation, noise exposure, and/or noise isolation into the PLD CAD in FIG. 12 by making modifications that fall within the knowledge of persons of ordinary skill in the art who have the benefit of the description of the invention.
  • the PLD CAD sets initial supply voltage levels (corresponding to estimated power consumption levels).
  • the software generates an initial placement. Then, at 609 it analyzes the timing of the circuitry using delay estimates that reflect the various settings, such as supply voltage settings.
  • the software determines whether it has met the user's various criteria, such as timing and power goals. If so, at 615 it records the placement and supply voltage selections. If not, the software checks at 618 to determine whether it has reached the iteration limit. If so, it proceeds to 615 to record the current placement and supply voltage selections.
  • the software If the software has not reached the iteration limit, it increments the iteration count (not shown explicitly), and at 621 changes the settings of at least some regions, circuits, blocks, or parts of the PLD. At 624 it analyzes the timing of the circuitry using delay estimates that reflect the changed settings. At 356 it improves the placement of the circuit, and jumps to 612 to determine whether it has met the user's timing and power goals.
  • the PLD CAD has implemented a design (i.e., synthesized, placed and routed the design), the CAD software should automatically provide data for programming the PLD that set the supply voltages of various parts of the PLD.
  • FIG. 13 shows a block diagram of circuitry within a PLD according to exemplary embodiments of the invention to adjust, program, or set the supply voltage levels of desired parts of the PLD.
  • the circuitry includes bias circuit 703 , a plurality of configuration memory (configuration random-access memory, or CRAM, or other implementations of the memory) cells 709 , and controlled PLD circuits 300 .
  • configuration memory configuration random-access memory, or CRAM, or other implementations of the memory
  • Bias circuit 703 generates one or more signals 706 and provides those signal(s) to controlled PLD circuits 300 (more particularly, to control circuit 303 , as shown, for example, in FIG. 4 ). In other word, bias circuit 703 provides one or more global bias signals to controlled PLD circuits 300 . Furthermore, each of CRAM cells 709 provides to a respective one of controlled PLD circuits 300 (more particularly, to control circuit 303 ). The signals from CRAM cells 709 represent configuration data for the various circuits within the PLD, as provided by the PLD CAD program described above.
  • control circuit (not shown explicitly) in each of controlled PLD circuits 300 In response to configuration data from CRAM cells 709 , the control circuit (not shown explicitly) in each of controlled PLD circuits 300 generates one or more signals to control the impedance of the variable impedance device (not shown explicitly) as a function of signal(s) 706 .
  • each of CRAM cells 709 may provide configuration data to more than one controlled PLD circuit, as desired. Conversely, one may modify the control circuit within controlled PLD circuits 300 so as to make it responsive to configuration data from more than one CRAM cell 709 , as desired.
  • FIG. 14 shows a circuit arrangement according to exemplary embodiments of the invention for adjusting supply voltage levels within PLD 103 in response to an external source 753 .
  • the circuit arrangement includes external source 753 , communication/interface circuit 762 , and bias circuit 703 (see FIG. 13 ).
  • Communication/interface circuit 762 provides a mechanism for external source 753 and bias circuit 703 to communicate and exchange information.
  • External source 753 may provide one or more control signal(s) 756 to communication/interface circuit 762 within PLD 103 .
  • Communication/interface circuit 762 provides the information received from external source 753 to bias circuit 703 .
  • bias circuit 703 generates one or more signals 706 , with levels corresponding to control signal(s) 756 .
  • Communication/interface circuit 762 may provide information, such as status signals, from bias circuit 703 (or PLD 103 generally) to external source 753 .
  • External source 753 may constitute a variety of devices, structures, or arrangements, as persons of ordinary skill in the art with the benefit of the description of the invention understand.
  • external source 753 may constitute a computer network (e.g., the Internet), a telephone-line communication link, a wireless communication link, a bus, etc., as desired.
  • external source 753 may update or modify control signal(s) 756 that it provides to PLD 103 .
  • Bias circuit 703 responds accordingly to the updated or modified signal(s) 756 .
  • FIG. 15 shows a circuit arrangement for modifying supply voltage level(s) within a PLD according to exemplary embodiments of the invention.
  • the circuit arrangement includes one or more sensor(s) 803 , one or more reference source(s) 806 , subtracter 818 , and bias circuit 703 .
  • Sensor(s) 803 sense a desired parameter (e.g., temperature, noise, etc.) in one or more areas, circuits, or blocks within PLD 103 and provide signal(s) 809 to subtracter 818 .
  • Reference source(s) 806 provide reference signal(s) 812 to subtracter 818 .
  • Reference signal(s) 812 may have values that correspond to various levels of the sensed parameter.
  • Subtracter 818 subtracts reference signal(s) 812 from signal(s) 809 and provides difference signal(s) 815 to bias circuit 703 .
  • Difference signal(s) 815 may constitute the difference between actual sensed value(s) and the desired value(s) in one or more parts of PLD 103 .
  • bias circuit 703 In response to difference signal(s) 815 , bias circuit 703 generates signal(s) 706 (see also FIG. 13 ).
  • Bias circuit 703 may use difference signal(s) 815 to generate signal(s) 706 that ultimately affect various aspects of the performance of PLD 103 . For example, if difference signal(s) 815 indicate a lower sensed value (say, speed) than a threshold or maximum value, bias circuit 703 may generate signal(s) that increase supply voltage level(s) to increase operating speed of the desired parts of PLD 103 . In contrast, if difference signal(s) 815 indicate a sensed level higher than a safe or maximum level, bias circuit 703 may generate signal(s) that decrease supply voltage level(s) to safe or desired levels (albeit with a decreased resulting speed).
  • difference signal(s) 815 indicate a lower sensed value (say, speed) than a threshold or maximum value
  • bias circuit 703 may generate signal(s) that increase supply voltage level(s) to increase operating speed of the desired parts of PLD 103 .
  • bias circuit 703 may generate signal(s) that decrease supply voltage level(s) to safe or desired levels (albeit with
  • Such circuitry include devices known as complex programmable logic device (CPLD), programmable gate array (PGA), and field programmable gate array (FPGA).
  • CPLD complex programmable logic device
  • PGA programmable gate array
  • FPGA field programmable gate array
  • circuit implementation may or may not contain separately identifiable hardware for the various functional blocks and may or may not use the particular circuitry shown.
  • the choice of circuit implementation depends on various factors, such as particular design and performance specifications for a given implementation, as persons of ordinary skill in the art who have the benefit of the description of the invention understand.
  • Other modifications and alternative embodiments of the invention in addition to those described here will be apparent to persons of ordinary skill in the art who have the benefit of the description of the invention. Accordingly, this description teaches those skilled in the art the manner of carrying out the invention and are to be construed as illustrative only.

Abstract

A programmable logic device (PLD) includes a circuit that controls a supply voltage of at least a portion of the circuitry within the PLD (such as a block, a sub-block, or a region). The circuit also filters noise within the PLD. Controlling the supply voltage allows trading off various performance characteristics, such as speed and power consumption.

Description

    TECHNICAL FIELD
  • The inventive concepts relate generally to adjusting the performance of programmable logic devices (PLDs). More particularly, the invention concerns adjusting the supply voltage/power consumption of PLDs, as well as noise reduction and isolation in PLDs.
  • BACKGROUND
  • PLDs are ubiquitous electronic devices that provide flexibility to not only designers, but also end-users. During the design cycle of an electronic circuit or system, a designer may perform a relatively large number of design iterations by simply re-programming the PLD for each design. Thus, the length and expense of the design cycle decreases compared to other alternatives. Similarly, the end-user may have a desired level of control over the functionality of a design that includes PLD(s). By programming the PLD(s) in the field or even on a real-time basis, the user can change the way the circuit or system behaves.
  • To accommodate increasingly complex designs, modern PLDs include a relatively large number of transistors. Furthermore, users demand ever higher performance, which results in larger operating frequencies. Consequently, the power consumption, power dissipation, die temperatures and, hence, power density (power dissipation in various circuits or blocks), of PLDs has tended to increase. The upward march of the power density, however, may make PLDs design and implementation impractical or failure-prone. A need exists for PLDs that feature adjustable performance, such as adjustable power consumption in various PLD blocks and circuits.
  • SUMMARY
  • The disclosed novel concepts relate to apparatus and methods for adjusting the performance of PLDs, including adjusting the supply voltage/power consumption of PLDs, as well as noise reduction and isolation in PLDs. One aspect of the invention relates to apparatus for adjusting the performance of PLDs. In one embodiment, a PLD includes a circuit that controls a supply voltage of another circuit within the PLD. The controlling circuit further filters noise within the PLD.
  • In another embodiment, a PLD includes a circuit that resides in a deep n-well in the PLD. The circuit in the deep n-well couples to a variable impedance device. The variable impedance device adjusts the supply voltage of the circuit in the deep n-well, thus adjusting its performance.
  • Another aspect of the invention relates to methods of configuring, operating, and adjusting the performance of PLDs. In one embodiment, a method of configuring a PLD to implement an electronic circuit includes mapping the electronic circuit to functional resources within the PLD to generate a circuit to be implemented by the PLD. The method further includes identifying at least one critical circuit path in the circuit to be implemented by the PLD, and setting the supply voltage level of at least a portion of the critical circuit path.
  • In another embodiment, a method of operating a PLD includes setting the supply voltage level of a circuit in the PLD to a voltage level, and determining whether a performance measure of the PLD meets a particular criterion. The method further includes adjusting the supply voltage level of the circuit depending on whether the performance measure of the PLD meets the criterion.
  • Another embodiment relates to a method of operating a PLD that is configured to function in a desired or prescribed operating environment. More specifically, the method includes setting the supply voltage level of a circuit in the PLD to a voltage level, and adjusting the supply voltage level of the first circuit depending on at least one characteristic of the operating environment of the programmable logic device (PLD).
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The appended drawings illustrate only exemplary embodiments of the invention and therefore should not be considered as limiting its scope. Persons of ordinary skill in the art who have the benefit of the description of the invention appreciate that the disclosed inventive concepts lend themselves to other equally effective embodiments. In the drawings, the same numeral designators used in more than one drawing denote the same, similar, or equivalent functionality, components, or blocks.
  • FIG. 1 shows a general block diagram of a PLD according to an illustrative embodiment of the invention.
  • FIG. 2 illustrates a floor-plan of a PLD according to an exemplary embodiment of the invention.
  • FIG. 3 depicts a block diagram of an exemplary embodiment of programmable logic in a PLD according to the invention.
  • FIG. 4 shows a circuit arrangement for adjusting the supply voltage of a desired circuit in a PLD according to an exemplary embodiment of the invention.
  • FIG. 5 illustrates another circuit arrangement for adjusting the supply voltage of a desired circuit in a PLD according to an exemplary embodiment of the invention.
  • FIG. 6 depicts a circuit arrangement for reducing the noise level in a PLD according to an exemplary embodiment of the invention.
  • FIG. 7 shows another circuit arrangement for reducing the noise level in a PLD according to an exemplary embodiment of the invention.
  • FIG. 8 illustrates an arrangement for providing a flexible mechanism for adjusting the performance of the various parts of a PLD according to an exemplary embodiment of the invention.
  • FIGS. 9A-9C depict circuit arrangements for distributing and generating power supply voltages in PLDs according to exemplary embodiments of the invention.
  • FIG. 10 shows an example of using n-wells to isolate noise-sensitive circuits in a PLD according to an illustrative embodiment of the invention.
  • FIG. 11 illustrates various software modules that PLD computer-aided design (CAD) software according to illustrative embodiments of the invention uses.
  • FIG. 12 depicts a flow diagram for a PLD CAD software according to an exemplary embodiment of the invention.
  • FIG. 13 shows a block diagram of circuitry within a PLD according to exemplary embodiments of the invention to adjust, program, or set the supply voltage levels of desired parts of the PLD.
  • FIG. 14 illustrates a circuit arrangement according to exemplary embodiments of the invention for adjusting supply voltage levels within a PLD in response to an external source.
  • FIG. 15 depicts a circuit arrangement for adjusting supply voltage level(s) within a PLD according to exemplary embodiments of the invention.
  • DETAILED DESCRIPTION
  • The inventive concepts contemplate apparatus and associated methods for PLDs that feature adjustable supply voltage (and, hence, power consumption and performance), reduced noise levels, and noise isolation. The inventive concepts help to overcome excessive power density levels that conventional PLDs suffer. Moreover, one may adjust the performance level of a desired portion, circuit, or block (or all circuits and blocks), of a PLD according to the invention. Put another way, one may adjust the performance by programming the supply voltage and the attendant power dissipation of the circuitry within the PLD with a desired level of granularity, ranging from individual circuit blocks, all the way to the entire PLD circuitry.
  • More specifically, and as described below in detail, the inventive concepts contemplate controlling the supply voltage and power consumption of one or more circuits or blocks of circuits within the PLD by using a variable impedance circuit. In addition, one may use the variable impedance circuit to form a filter that, simultaneously with the adjustment of the power consumption, tend to reduce the noise levels present within the PLD. The reduced noise levels help to protect sensitive circuitry within the PLD from adverse effects of electrical noise. Furthermore, one may protect noise-sensitive circuitry within the PLD by using deep n-well structures within the PLD that help to isolate the sensitive circuitry from sources of electrical noise.
  • The inventive concepts provide the following benefits over traditional implementations. First, they allow trading off performance and power consumption or optimizing the performance-power consumption tradeoff. Second, one may selectively set, program, or adjust the supply voltage and power consumption in critical circuit paths or parts of the PLD so as to increase their performance as desired. Conversely, one may selectively set, program, or adjust the supply voltage and power consumption in non-critical circuit paths or parts of the PLD to levels commensurate with their desired performance.
  • One may also employ the inventive concepts to prevent (or reduce the probability of) thermal runaway. More specifically, in a traditional PLD, circuits operating at relatively high speeds tend to consume more power, resulting in temperature increase of the PLD. The increased power consumption may in turn cause those circuits to consume more power. This positive feedback mechanism may increase the power densities to unsafe or destructive levels. In PLDs according to the invention, one may adjust or control the supply voltage and power consumption levels of various blocks and, hence, reduce the likelihood of thermal runaway. Furthermore, the inventive concepts help to provide better performance by reducing the noise levels within the PLD and to isolate noise-sensitive circuitry from the undesirable effects of noise.
  • FIG. 1 shows a general block diagram of a PLD 103 according to an illustrative embodiment of the invention. PLD 103 includes configuration circuitry 130, configuration memory 133, control circuitry 136, programmable logic 106, programmable interconnect 109, and I/O circuitry 112. In addition, PLD 103 may include test/debug circuitry 115, one or more processors 118, one or more communication circuitry 121, one or more memories 124, one or more controllers 127, as desired.
  • Note that FIG. 1 shows a simplified block diagram of PLD 103. Thus, PLD 103 may include other blocks and circuitry, as persons of ordinary skill in the art understand. Examples of such circuitry include clock generation and distribution circuits, redundancy circuits, and the like. Furthermore, PLD 103 may include, analog circuitry, other digital circuitry, and/or mixed-mode circuitry, as desired.
  • Programmable logic 106 includes blocks of configurable or programmable logic circuitry, such as look-up tables (LUTs), product-term logic, multiplexers, logic gates, registers, memory, and the like. Programmable interconnect 109 couples to programmable logic 106 and provides configurable interconnects (coupling mechanisms) between various blocks within programmable logic 106 and other circuitry within or outside PLD 103.
  • Control circuitry 136 controls various operations within PLD 103. Under the supervision of control circuitry 136, PLD configuration circuitry 130 uses configuration data (which it obtains from an external source, such as a storage device, a host, etc.) to program or configure the functionality of PLD 103. The configuration data typically reside in configuration memory 133. The configuration data determine the functionality of PLD 103 by programming programmable logic 106 and programmable interconnect 109, as persons skilled in the art with the benefit of the description of the invention understand.
  • I/O circuitry 112 may constitute a wide variety of I/O devices or circuits, as persons of ordinary skill in the art who have the benefit of the description of the invention understand. I/O circuitry 112 may couple to various parts of PLD 103, for example, programmable logic 106 and programmable interconnect 109. I/O circuitry 112 provides a mechanism and circuitry for various blocks within PLD 103 to communicate with external circuitry or devices.
  • Test/debug circuitry 115 facilitates the testing and troubleshooting of various blocks and circuits within PLD 103. Test/debug circuitry 115 may include a variety of blocks or circuits known to persons of ordinary skill in the art who have the benefit of the description of the invention. For example, test/debug circuitry 115 may include circuits for performing tests after PLD 103 powers up or resets, as desired. Test/debug circuitry 115 may also include coding and parity circuits, as desired.
  • As noted above, PLD 103 may include one or more processors 118. Processor 118 may couple to other blocks and circuits within PLD 103. Processor 118 may receive data and information from circuits within or external to PLD 103 and process the information in a wide variety of ways, as persons skilled in the art with the benefit of the description of the invention appreciate. One or more of processor(s) 118 may constitute a digital signal processor (DSP). DSPs allow performing a wide variety of signal processing tasks, such as compression, decompression, audio processing, video processing, filtering, and the like, as desired.
  • PLD 103 may also include one or more communication circuitry 121. Communication circuitry 121 may facilitate data and information exchange between various circuits within PLD 103 and circuits external to PLD 103, as persons of ordinary skill in the art who have the benefit of the description of the invention understand. As an example, communication circuitry 121 may provide various protocol functionality (e.g., Transmission Control Protocol/Internet Protocol (TCP/IP), User Datagram Protocol (UDP) etc.), as desired. As another example, communication circuitry 121 may include network (e.g., Ethernet, token ring, etc.) or bus interface circuitry, as desired.
  • PLD 103 may further include one or more memories 124 and one or more controller(s) 127. Memory 124 allows the storage of various data and information (such as user-data, intermediate results, calculation results, etc.) within PLD 103. Memory 124 may have a granular or block form, as desired. Controller 127 allows interfacing to, and controlling the operation and various functions of circuitry outside the PLD. For example, controller 127 may constitute a memory controller that interfaces to and controls an external synchronous dynamic random access memory (SDRAM), as desired.
  • In addition to the circuitry that FIG. 1 shows, PLD 103 may include analog or mixed-mode circuitry 139, sometimes known as analog or mixed-mode intellectual property (IP) blocks. For example, PLD 103 may include amplifiers, digital-to-analog converters, analog-to-digital converters, filters, and the like. By their nature, analog/mixed-mode circuits tend to exhibit sensitivity to noise. As described below in detail, the inventive concepts help to isolate noise-sensitive circuitry from noise-generating circuitry. Furthermore, the inventive concepts include techniques that tend to reduce the noise levels present in PLDs.
  • FIG. 2 shows a floor-plan of a PLD 103 according to an exemplary embodiment of the invention. PLD 103 includes programmable logic 106 arranged as a two-dimensional array. Programmable interconnect 109, arranged as horizontal interconnect and vertical interconnect, couples the blocks of programmable logic 106 to one another.
  • One may adjust the supply voltage and, hence, the power dissipation level, of each block of programmable logic 106, each segment of programmable interconnect 109, or both, as desired. Furthermore, one may adjust the supply voltage and the power dissipation level of a portion of one or more blocks of programmable logic 106, a portion of programmable interconnect 109, or both, as desired.
  • In illustrative embodiments, PLDs according to the invention have a hierarchical architecture. In other words, each block of programmable logic 106 in FIG. 2 may in turn include smaller or more granular programmable logic blocks or circuits. One may adjust the supply voltage and power consumption or dissipation in each level of the hierarchical architecture of the PLD, as desired.
  • FIG. 3 shows a block diagram of an exemplary embodiment of programmable logic 106 in a PLD according to the invention. Programmable logic 106 includes logic elements or programmable logic circuits 250, local interconnect 253, interface circuit 256, and interface circuit 259. Logic elements 250 provide configurable or programmable logic functions, for example, LUTs, registers, product-term logic, etc., as persons of ordinary skill in the art who have the benefit of the description of the invention understand. Local interconnect 253 provides a configurable or programmable mechanism for logic elements 250 to couple to one another or to programmable interconnect 109 (sometimes called “global interconnect”), as desired.
  • Interface circuit 256 and interface circuit 259 provide a configurable or programmable way for programmable logic 106 block of circuitry to couple to programmable interconnect 109 (and hence to other programmable logic 106, as FIG. 2 shows). Interface circuit 256 and interface circuit 259 may include multiplexers (MUXs), registers, buffers, drivers, and the like, as persons of ordinary skill in the art who have the benefit of the description of the invention understand.
  • One may adjust the supply voltage and power consumption of each portion or block of circuitry within PLD 103 (see FIGS. 1-3), as desired. Furthermore, one may adjust the supply voltage and power consumption of each portion or block of circuitry independently of others, on an individual or collective basis, as desired. Within each portion or block of circuitry, one may adjust the supply voltage and power consumption of each sub-block, or groups of sub-blocks, as desired.
  • For example, one may adjust the supply voltage and power consumption of all or a portion of the following circuitry within a PLD according to exemplary embodiments of the invention: one or more of the blocks in FIG. 1 (e.g., programmable logic 106, programmable interconnect 109, etc.); one or more logic elements 250 within one or more programmable logic blocks 106; one or more interface circuits 256 and/or 259, within one or more programmable logic blocks 106; one or more local interconnect within one or more programmable logic 106; and one or more MUXs, drivers, buffers, etc., within one or more interface circuits 256 and/or 259.
  • As noted above, one may make the supply voltage and power consumption adjustments in any desired level of granularity. In other words, one may make the adjustments applicable to sub-blocks, blocks, regions, or the entire PLD, as desired, and as applicable. For example, one may make supply voltage and power consumption adjustments to one or more of such elements of the PLD independently of one or more of other elements within the PLD, as desired. As persons of ordinary skill in the art with the benefit of the description of the invention understand, one may adjust the supply voltage and power consumption of some parts of a PLD and yet provide a fixed or default supply voltage and power consumption for other parts of the PLD, as desired.
  • FIG. 4 shows a circuit arrangement for adjusting the supply voltage and, hence, the power consumption of a desired circuit in a PLD according to an exemplary embodiment of the invention. More specifically, the circuit arrangement in FIG. 4 shows a controlled PLD circuit 300 that includes control circuit 303, PLD circuit 306, and variable impedance device 309.
  • The circuit operates as follows: In response to one or more signals not shown explicitly in FIG. 4 (such as a bias signal and configuration signals, described in connection with FIG. 13) circuit 303 applies a corresponding control signal (or signals, depending on the nature of variable impedance device 309) so as to cause adjustment of the supply voltage that variable impedance device 309 provides to PLD circuit 306. Consequently, control circuit 303 can cause the adjustment of the power consumption (and other performance criteria, such as operating speed) of PLD circuit 306.
  • Variable impedance device 309 couples the supply voltage, VDD, to PLD circuit 306. When variable impedance device 309 has a relatively high impedance, PLD circuit 306 conducts relatively little current, and has a nearly zero supply voltage. Thus, PLD circuit 306 effectively shuts down or enters an OFF state or sleep mode. In this state, PLD circuit 306 consumes nearly zero power.
  • At the other extreme, when variable impedance device 309 has a relatively low impedance, PLD circuit 306 receives nearly the voltage VDD as its supply voltage (minus any drop across variable impedance device 309). In this state, PLD circuit 306 typically has higher power consumption, but also higher speed. Thus, by varying the effective supply voltage of PLD circuit 306 between the two extremes of near-zero and near-VDD supply voltages, one may trade off its various performance measures, such as power consumption and speed.
  • PLD circuit 306 may constitute any desired region, block, circuitry, sub-block, or collection of each of those parts, of a PLD. For example, PLD circuit 306 may constitute one or more of the elements shown in FIGS. 1-3, such as programmable interconnect 109, logic elements 250, etc., as desired.
  • As described below in detail, control circuit 303 may operate under the supervision of one or more other parts of the PLD, or under the control of an external source, or a combination of internal and external sources, as desired. Control circuit 303 causes the impedance of the variable impedance device to change. As a result, the effective supply voltage provided to PLD circuit 306 varies. The effective supply voltage of PLD circuit 306 affects its characteristics, such as operating speed, power consumption, and the like. By adjusting the supply voltage level for PLD circuit 306, one may trade off its various characteristics, such as speed versus power consumption.
  • Variable impedance device 309 may constitute a desired type of device, depending on factors such as the particular PLD implementation, circuit and process technology, and the like, as persons of ordinary skill in the art who have the benefit of the description of the invention understand. As one example, variable impedance device 309 may constitute a transistor.
  • FIG. 5 illustrates another circuit arrangement for adjusting the supply voltage of a desired circuit in a PLD according to an exemplary embodiment of the invention. The circuit arrangement in FIG. 5 is similar to the circuit in FIG. 4. FIG. 5, however, uses a transistor 320 and, more particularly, a metal oxide semiconductor field effect transistor (MOSFET) transistor, as a particular type of variable impedance device.
  • Depending on factors such as the particular PLD implementation, circuit and process technology, and the like, as persons of ordinary skill in the art who have the benefit of the description of the invention understand, transistor 320 may constitute a variety of devices, such as bipolar junction transistors (BJTs), bipolar hetero-junction transistor (BHT), and the like.
  • In one embodiment implemented using metal oxide semiconductor (MOS) or complementary MOS (CMOS) technology, transistor 320 may constitute a native transistor, as desired. Native transistors may have a negative or small threshold voltage, VT, thus making biasing or driving transistor 320 easier in situations where a relatively small VDD results in a small headroom in the output voltage of control circuit 303.
  • As noted above, PLDs according to the invention may include noise-sensitive analog or mixed-mode circuitry. One may use filtering techniques to help reduce the overall noise in the PLD or the noise level that the analog or mixed-mode circuitry experiences.
  • FIG. 6 depicts a circuit arrangement for reducing the noise level in a PLD according to an exemplary embodiment of the invention. Controlled PLD circuit 300 in FIG. 6 is analogous to the circuit shown in FIG. 4, and provides similar benefits. Thus, the circuitry in FIG. 6 provides the capability of controlling the supply voltage and, hence, the performance, of PLD circuit 306, as described above in detail. In the circuit of FIG. 6, PLD circuit 306 constitutes a circuit with relatively high sensitivity to noise, such as an analog or mixed-mode circuit.
  • In addition to the elements shown in FIG. 4, the circuit arrangement in FIG. 6 includes capacitor 323 and capacitor 326. Together with various impedances present in the circuit, each of those capacitors forms a filter. For example, capacitor 326, together with the parallel impedance of variable impedance device 309 and PLD circuit 306, forms a low-pass filter. By filtering higher frequencies, the low-pass filters tend to reduce the overall noise level that PLD circuit 306 experiences. Note that one may omit one of capacitors 323 and 326, depending on factors such as the desired level of filtering, the size and value of components, and the like, as persons of ordinary skill in the art who have the benefit of the description of the invention understand.
  • FIG. 7 shows another circuit arrangement for reducing the noise level in a PLD according to an exemplary embodiment of the invention. The circuit arrangement in FIG. 7 constitutes a more specific implementation of the circuit in FIG. 6. More specifically, rather than a general variable impedance device 309 in FIG. 6, the circuit arrangement in FIG. 7 uses transistor 320. Transistor 320 may generally constitute any of the devices described above with respect to FIG. 5, as desired. Note that, as described above, one may omit one of capacitors 323 and 326, depending on factors such as the desired level of filtering, the size and value of components, and the like, as persons of ordinary skill in the art who have the benefit of the description of the invention understand.
  • Using controlled PLD circuit 300 described above, one may adjust the supply voltage and power consumption and thus performance of various parts of PLDs. FIG. 8 shows an arrangement for providing a flexible mechanism for adjusting the performance of the various parts of a PLD 103 according to an exemplary embodiment of the invention. PLD 103 includes one or more PLD circuit regions or “islands” 400A-400C. Each PLD circuit region 400A-400C includes one or more controlled PLD circuits 300, as described above.
  • Each of PLD circuit regions 400A-400C may receive one or more power supply voltages, labeled as VDD1-VDDN. As examples, PLD circuit region 400A receives VDD1, whereas circuit region 400B receives VDD1-VDD3, and circuit region 400C receives VDDN. Each of controlled PLD circuits 300 can adjust the supply voltage provided to its respective PLD circuit 306 (see, for example, FIG. 4), as described above in detail.
  • By assigning a desired set of power supply voltages to each of PLD circuit regions 400A-400C, one may adjust the supply voltage and power consumption of circuitry within the circuit regions. Furthermore, by including a desired set of controlled PLD circuits 300 within a given circuit region 400A-400C, one may match the type of supply voltage adjustment in each circuit region 40OA-400C with one or more suitable controlled PLD circuits 300. Thus, the arrangement in FIG. 8 provides a flexible mechanism for allocating various PLD resources to implementing an appropriate part of the user's design or system so as to provide an efficient implementation with improved performance adjustment capabilities and better overall performance. (e.g., speed-power consumption tradeoff).
  • Note that, in addition to, or rather than, receiving external power supply voltages (e.g., VDD1-VDDN in FIG. 8), PLD 103 may generate power supply voltages internally, as desired. FIGS. 9A-9C show circuit arrangements for distributing and generating power supply voltages in PLDs according to exemplary embodiments of the invention.
  • In FIG. 9A, PLD 103 simply uses the external power supply voltages that it receives, e.g., VDD1-VDDN. In this scenario, PLD 103 may use a power distribution and supply voltage adjustment scheme, such as the arrangement in FIG. 8.
  • In FIG. 9B, PLD 103 receives power supply voltages VDD1-VDDN. PLD 103 may regulate one or more of the power supply voltages to generate one or more internal power supply voltages. PLD 103 may then use the external and the internally generated powers supply voltages in a power distribution and supply voltage adjustment scheme, e.g., as shown in FIG. 8. In the particular example shown, PLD 103 uses voltage regulator 450 to generate internal power supply voltage VDD2′ from external power supply voltage VDD2.
  • In FIG. 9C, PLD 103 receives power supply voltages VDD1-VDDN. PLD 103 may use one or more charge pumps 453 to generate one or more internal power supply voltages. PLD 103 may then use the external and the internally generated powers supply voltages in a power distribution and supply voltage adjustment scheme, e.g., as shown in FIG. 8. In the particular example shown, PLD 103 uses charge pump 453 to generate internal power supply voltage VDD1′ from external power supply voltage VDD1. Internal power supply voltage VDD1′ has a higher voltage level than VDD1.
  • As noted above, the inventive concepts include techniques for isolating noise-sensitive circuits from noise-generating circuitry with the PLD. More particularly, in PLDs fabricated using CMOS technology, various PLD circuits typically reside in a number of deep n-wells. By strategically placing noise-sensitive circuits in isolated n-wells, one may shield or isolate the noise-sensitive circuits from sources of noise. Thus, one may provide islands within the PLD, each with its own supply voltage, power consumption, noise generation, and noise isolation characteristics. The islands provide a mechanism in PLDs according to the invention for providing a flexible implementation of a user's design or system.
  • FIG. 10 shows an example of using n-wells to isolate noise-sensitive circuits in a PLD according to an illustrative embodiment of the invention. The PLD resides in substrate 500. Substrate 500 includes deep n- wells 503, 506, and 509. Each of deep n- wells 503, 506, and 509 may include a variety of PLD circuitry, such as the circuits shown in FIGS. 1-3.
  • As noted, one may place the various circuits in deep n- wells 503, 506, and 509 so as to reduce interference and noise. For example, one may place circuitry with relatively high noise sensitivity (labeled as 506A) in a PLD that includes circuits that generate moderate amounts of noise (labeled as 506B) as well as circuits that produce relatively high levels of noise (labeled as 506C). As the example in FIG. 10 illustrates, one may place circuits 506A, 506B, and 506C in deep n- wells 503, 506, and 509, respectively. Noise and interference tends to decrease by the virtue of placing noise-sensitive circuit 506A farthest from the relatively high levels of noise that circuit 506C generates, but nearer to the moderate levels of noise that circuit 506B produces.
  • Note that deep n-wells represent an illustrative construct in a PLD fabrication technology. Depending on a number of factors, one may use other constructs and devices in current and future fabrication technologies, as persons of ordinary skill in the art who have the benefit of the description of the invention understand. The factors include the type and characteristics of the technology and the devices and constructs available, the desired design and performance specifications, cost, complexity, area efficiency, and the like.
  • As an example, one may use silicon-on-insulator (SOI) technology to provide noise isolation and control within PLDs. More specifically, and as persons of ordinary skill in the art who have the benefit of the description of the invention understand, SOI circuits tend to provide isolation between transistors because of the insulator layer (typically silicon dioxide). Thus, SOI circuits provide a mechanism for isolating noise-sensitive circuits from noise-generating circuits of the PLD.
  • As noted above, the user may adjust the supply voltage and power consumption and noise exposure or performance of various portions of PLDs according to the invention. The user may do so by using the software used to map a design to a PLD. FIG. 11 depicts various software modules that PLD computer-aided design (CAD) software according to illustrative embodiments of the invention uses. The modules include design-entry module 550, synthesis module 553, place-and-route module 556, and verification module 559.
  • Design-entry module 550 allows the integration of multiple design files. The user may generate the design files by using design-entry module 550 or by using a variety of electronic design automation (EDA) or CAD tools (such as industry-standard EDA tools), as desired. The user may enter the design in a graphic format, a waveform-based format, a schematic format, in a text or binary format, or as a combination of those formats, as desired.
  • Synthesis module 553 accepts the output of design-entry module 550. Based on the user-provided design, synthesis module 553 generates appropriate logic circuitry that realizes the user-provided design. One or more PLDs (not shown explicitly) implement the synthesized overall design or system.
  • Synthesis module 553 may also generate any glue logic that allows integration and proper operation and interfacing of various modules in the user's designs. For example, synthesis module 553 provides appropriate hardware so that an output of one block properly interfaces with an input of another block. Synthesis module 553 may provide appropriate hardware so as to meet the specifications of each of the modules in the overall design or system.
  • Furthermore, synthesis module 553 may include algorithms and routines for optimizing the synthesized design. Through optimization, synthesis module 553 seeks to more efficiently use the resources of the one or more PLDs that implement the overall design or system. In some embodiments, synthesis module 553 may identify critical paths within the synthesized design or system. Synthesis module 553 provides its output to place-and-route module 556.
  • Place-and-route module 556 uses the designer's timing specifications to perform optimal logic mapping and placement. The logic mapping and placement determine the use of routing resources within the PLD(s). In other words, by use of particular programmable interconnects with the PLD(s) for certain parts of the design, place-and-route module 556 helps optimize the performance of the overall design or system.
  • By proper use of PLD routing resources, place-and-route module 556 helps to meet the critical timing paths of the overall design or system. Place-and-route module 556 optimizes the critical timing paths to help provides timing closure faster in a manner known to persons of ordinary skill in the art with the benefit of the description of the invention. As a result, the overall design or system can achieve faster performance (i.e., operate at a higher clock rate or have higher throughput).
  • Furthermore, place-and-route module 556 adjusts the supply voltage and power consumption and the noise performance or exposure of a portion of or all of the PLD(s) that implement the design or system. Place-and-route module 556 may do so automatically, according to user-specified criteria, or a combination of the two. Place-and-route module 556 may use the user-specified criteria (for example, performance specifications, such as power dissipation, noise exposure or performance, speed, and/or current-drive capability). In addition, or instead, place-and-route module 556 may use the information about critical paths within the design or system to adjust the supply voltage(s), physical placement so as to reduce noise generation and exposure, and power consumption of parts or all of the design or system, as desired.
  • For example, place-and-route module 556 may adjust the supply voltage and power consumption of the critical parts of the design or system so as to achieve higher performance. Place-and-route module 556 may take into account power dissipation criteria (e.g., maximum power density) so as to trade off power and performance, as desired. Place-and-route module 556 provides the optimized design to verification module 559.
  • Verification module 559 performs simulation and verification of the design. The simulation and verification seek in part to verify that the design complies with the user's prescribed specifications. The simulation and verification also aim at detecting and correcting any design problems before prototyping the design. Thus, verification module 559 helps the user to reduce the overall cost and time-to-market of the overall design or system.
  • Verification module 559 may support and perform a variety of verification and simulation options, as desired. The options may include design-rule checking, functional verification, test-bench generation, static timing analysis, timing simulation, hardware/software simulation, in-system verification, board-level timing analysis, signal integrity analysis and electromagnetic compatibility (EMC), formal netlist verification, noise generation and exposure, and power-consumption estimation, as desired. Note that one may perform other or additional verification techniques as desired and as persons of ordinary skill in the art who have the benefit of the description of the invention understand.
  • FIG. 12 illustrates a flow diagram for a PLD CAD software according to an exemplary embodiment of the invention. The PLD CAD shown in FIG. 12 incorporates the choice of supply voltage and power consumption for each region of the PLD into a timing-driven place-and-route CAD system. Note that, as desired, one may include criteria for noise generation, noise exposure, and/or noise isolation into the PLD CAD in FIG. 12 by making modifications that fall within the knowledge of persons of ordinary skill in the art who have the benefit of the description of the invention.
  • Starting the process, at 603 the PLD CAD sets initial supply voltage levels (corresponding to estimated power consumption levels). At 606 the software generates an initial placement. Then, at 609 it analyzes the timing of the circuitry using delay estimates that reflect the various settings, such as supply voltage settings. At 612 the software determines whether it has met the user's various criteria, such as timing and power goals. If so, at 615 it records the placement and supply voltage selections. If not, the software checks at 618 to determine whether it has reached the iteration limit. If so, it proceeds to 615 to record the current placement and supply voltage selections.
  • If the software has not reached the iteration limit, it increments the iteration count (not shown explicitly), and at 621 changes the settings of at least some regions, circuits, blocks, or parts of the PLD. At 624 it analyzes the timing of the circuitry using delay estimates that reflect the changed settings. At 356 it improves the placement of the circuit, and jumps to 612 to determine whether it has met the user's timing and power goals. Once the PLD CAD has implemented a design (i.e., synthesized, placed and routed the design), the CAD software should automatically provide data for programming the PLD that set the supply voltages of various parts of the PLD.
  • FIG. 13 shows a block diagram of circuitry within a PLD according to exemplary embodiments of the invention to adjust, program, or set the supply voltage levels of desired parts of the PLD. The circuitry includes bias circuit 703, a plurality of configuration memory (configuration random-access memory, or CRAM, or other implementations of the memory) cells 709, and controlled PLD circuits 300.
  • Bias circuit 703 generates one or more signals 706 and provides those signal(s) to controlled PLD circuits 300 (more particularly, to control circuit 303, as shown, for example, in FIG. 4). In other word, bias circuit 703 provides one or more global bias signals to controlled PLD circuits 300. Furthermore, each of CRAM cells 709 provides to a respective one of controlled PLD circuits 300 (more particularly, to control circuit 303). The signals from CRAM cells 709 represent configuration data for the various circuits within the PLD, as provided by the PLD CAD program described above. In response to configuration data from CRAM cells 709, the control circuit (not shown explicitly) in each of controlled PLD circuits 300 generates one or more signals to control the impedance of the variable impedance device (not shown explicitly) as a function of signal(s) 706.
  • In other variations, each of CRAM cells 709 may provide configuration data to more than one controlled PLD circuit, as desired. Conversely, one may modify the control circuit within controlled PLD circuits 300 so as to make it responsive to configuration data from more than one CRAM cell 709, as desired.
  • Note that one may adjust, program, or set supply voltage levels in response to sources external to the PLD. For example, one may communicate supply voltage levels to a PLD to adjust or modify its performance. FIG. 14 shows a circuit arrangement according to exemplary embodiments of the invention for adjusting supply voltage levels within PLD 103 in response to an external source 753. The circuit arrangement includes external source 753, communication/interface circuit 762, and bias circuit 703 (see FIG. 13).
  • Communication/interface circuit 762 provides a mechanism for external source 753 and bias circuit 703 to communicate and exchange information. External source 753 may provide one or more control signal(s) 756 to communication/interface circuit 762 within PLD 103. Communication/interface circuit 762 provides the information received from external source 753 to bias circuit 703. In response, bias circuit 703 generates one or more signals 706, with levels corresponding to control signal(s) 756. Communication/interface circuit 762 may provide information, such as status signals, from bias circuit 703 (or PLD 103 generally) to external source 753.
  • External source 753 may constitute a variety of devices, structures, or arrangements, as persons of ordinary skill in the art with the benefit of the description of the invention understand. For example, external source 753 may constitute a computer network (e.g., the Internet), a telephone-line communication link, a wireless communication link, a bus, etc., as desired.
  • Note that one may adjust, program, or set the supply voltage levels in PLDs on a dynamic or time-varying basis, as desired, to take into account or respond to changing conditions (for example, changes in performance specifications). As one example, referring to FIG. 14, external source 753 may update or modify control signal(s) 756 that it provides to PLD 103. Bias circuit 703 responds accordingly to the updated or modified signal(s) 756.
  • As another example, one may change or adjust supply levels in response to changes within PLD 103 itself, for instance, a change in temperature, noise, power consumption, and the like, in one or more circuits or areas of PLD 103. FIG. 15 shows a circuit arrangement for modifying supply voltage level(s) within a PLD according to exemplary embodiments of the invention.
  • The circuit arrangement includes one or more sensor(s) 803, one or more reference source(s) 806, subtracter 818, and bias circuit 703. Sensor(s) 803 sense a desired parameter (e.g., temperature, noise, etc.) in one or more areas, circuits, or blocks within PLD 103 and provide signal(s) 809 to subtracter 818. Reference source(s) 806 provide reference signal(s) 812 to subtracter 818. Reference signal(s) 812 may have values that correspond to various levels of the sensed parameter.
  • Subtracter 818 subtracts reference signal(s) 812 from signal(s) 809 and provides difference signal(s) 815 to bias circuit 703. Difference signal(s) 815 may constitute the difference between actual sensed value(s) and the desired value(s) in one or more parts of PLD 103. In response to difference signal(s) 815, bias circuit 703 generates signal(s) 706 (see also FIG. 13).
  • Bias circuit 703 may use difference signal(s) 815 to generate signal(s) 706 that ultimately affect various aspects of the performance of PLD 103. For example, if difference signal(s) 815 indicate a lower sensed value (say, speed) than a threshold or maximum value, bias circuit 703 may generate signal(s) that increase supply voltage level(s) to increase operating speed of the desired parts of PLD 103. In contrast, if difference signal(s) 815 indicate a sensed level higher than a safe or maximum level, bias circuit 703 may generate signal(s) that decrease supply voltage level(s) to safe or desired levels (albeit with a decreased resulting speed).
  • More generally, one may implement a feedback loop that generates supply voltage level(s) so as to target specific performance criteria. Put another way, one may compare actual performance measures of a PLD to desired or specified measures or criteria and adjust, program, or set supply voltage levels accordingly.
  • Note that one may apply the inventive concepts effectively to various programmable logic circuitry or ICs known by other names in the art, as desired, and as persons skilled in the art with the benefit of the description of the invention understand. Such circuitry include devices known as complex programmable logic device (CPLD), programmable gate array (PGA), and field programmable gate array (FPGA).
  • Referring to the figures, persons of ordinary skill in the art will note that the various blocks shown may depict mainly the conceptual functions and signal flow. The actual circuit implementation may or may not contain separately identifiable hardware for the various functional blocks and may or may not use the particular circuitry shown. For example, one may combine the functionality of various blocks into one circuit block, as desired. Furthermore, one may realize the functionality of a single block in several circuit blocks, as desired. The choice of circuit implementation depends on various factors, such as particular design and performance specifications for a given implementation, as persons of ordinary skill in the art who have the benefit of the description of the invention understand. Other modifications and alternative embodiments of the invention in addition to those described here will be apparent to persons of ordinary skill in the art who have the benefit of the description of the invention. Accordingly, this description teaches those skilled in the art the manner of carrying out the invention and are to be construed as illustrative only.
  • The forms of the invention shown and described should be taken as the presently preferred or illustrative embodiments. Persons skilled in the art may make various changes in the shape, size and arrangement of parts without departing from the scope of the invention described in this document. For example, persons skilled in the art may substitute equivalent elements for the elements illustrated and described here. Moreover, persons skilled in the art who have the benefit of this description of the invention may use certain features of the invention independently of the use of other features, without departing from the scope of the invention.

Claims (49)

1. A programmable logic device (PLD), comprising a first circuit configured to control a supply voltage of a second circuit, the first circuit further configured to filter noise within the programmable logic device (PLD).
2. The programmable logic device (PLD) according to claim 1, wherein the first circuit comprises a variable impedance device, the variable impedance device configured to provide the supply voltage of the second circuit.
3. The programmable logic device (PLD) according to claim 1, wherein the transistor comprises a native transistor of the programmable logic device.
4. The programmable logic device (PLD) according to claim 2, wherein the variable impedance device is further configured to provide the supply voltage of the second circuit in response to a programmable logic device (PLD) configuration datum.
5. The programmable logic device (PLD) according to claim 2, wherein the variable impedance device comprises a transistor.
6. The programmable logic device (PLD) according to claim 3, wherein the first circuit further comprises a control circuit coupled to a gate terminal of the transistor.
7. The programmable logic device (PLD) according to claim 6, wherein the transistor adjusts the supply voltage of the second circuit in response to an output signal of the control circuit.
8. The programmable logic device (PLD) according to claim 4, wherein the first circuit further comprises a first capacitor coupled to a gate terminal of the transistor.
9. The programmable logic device (PLD) according to claim 4, wherein the first circuit further comprises a second capacitor coupled to a source terminal of the transistor.
10. The programmable logic device (PLD) according to claim 7, wherein the output signal of the control circuit is derived from information received from an information source external to the programmable logic device (PLD).
11. The programmable logic device (PLD) according to claim 6, wherein the output signal of the control circuit depends on a power consumption of a circuit within the programmable logic device (PLD).
12. The programmable logic device (PLD) according to claim 1, wherein the second circuit comprises a programmable logic circuit.
13. The programmable logic device (PLD) according to claim 12, wherein the programmable logic circuit comprises one of a plurality of programmable logic circuits arranged as a two-dimensional array.
14. The programmable logic device (PLD) according to claim 12, wherein the programmable logic circuit comprises a logic element.
15. The programmable logic device (PLD) according to claim 14, wherein the programmable logic circuit comprises local interconnect circuitry.
16. The programmable logic device (PLD) according to claim 1, wherein the second circuit comprises programmable interconnect circuitry.
17. The programmable logic device (PLD) according to claim 1, wherein the second circuit comprises configuration memory configured to store configuration data of the programmable logic device (PLD).
18. A programmable logic device (PLD), comprising:
a first circuit, the first circuit residing in a first deep n-well; and
a first variable impedance device coupled to the first circuit, the first variable impedance device configured to adjust a supply voltage of the first circuit.
19. The programmable logic device (PLD) according to claim 18, further comprising a first capacitor coupled to the first variable impedance device.
20. The programmable logic device (PLD) according to claim 18, comprising:
a second circuit, the second circuit residing in a second deep n-well; and
a second variable impedance device coupled to the second circuit, the second variable impedance device configured to adjust a supply voltage of the second circuit.
21. The programmable logic device (PLD) according to claim 20, further comprising a second capacitor coupled to the second variable impedance device.
22. The programmable logic device (PLD) according to claim 20, wherein the first circuit is relatively sensitive to noise.
23. The programmable logic device (PLD) according to claim 20, wherein the first circuit comprises analog circuitry.
24. The programmable logic device (PLD) according to claim 20, wherein the first circuit comprises mixed-mode circuitry.
25. The programmable logic device (PLD) according to claim 22, wherein the second circuit generates relatively high levels of noise.
26. The programmable logic device (PLD) according to claim 20, wherein the first variable impedance device derives the supply voltage of the first circuit from a first voltage supplied to the programmable logic device (PLD).
27. The programmable logic device (PLD) according to claim 20, wherein the first variable impedance device derives the supply voltage of the first circuit from a first voltage, wherein the first voltage is derived within the programmable logic device (PLD) from a second voltage supplied to the programmable logic device (PLD).
28. A method of configuring a programmable logic device (PLD) to implement an electronic circuit, the method comprising:
mapping the electronic circuit to functional resources within the programmable logic device (PLD) to generate a circuit to be implemented by the programmable logic device (PLD);
identifying at least one critical circuit path in the circuit to be implemented by the programmable logic device (PLD); and
setting a supply voltage level of at least a portion of the critical circuit path.
29. The method according to claim 28, wherein setting a supply voltage level of at least a portion of the critical circuit path further comprises programming a configuration memory (CRAM) of the programmable logic device (PLD).
30. The method according to claim 29, wherein setting a supply voltage level of at least a portion of the critical circuit path further comprises adjusting an impedance of a variable impedance device depending on a value programmed in the configuration memory (CRAM).
31. The method according to claim 28, further comprising adjusting the supply voltage level of at least a portion of the critical circuit path.
32. The method according to claim 31, wherein adjusting the supply voltage level of at least a portion of the critical circuit path further comprises trading off speed and power consumption of the at least a portion of the critical circuit path.
33. The method according to claim 28, wherein setting a supply voltage level of at least a portion of the critical circuit path further comprises using an output signal of a control circuit.
34. The method according to claim 33, wherein setting a supply voltage level of at least a portion of the critical path further comprises adjusting an impedance of a variable impedance device by using the output signal of the control circuit.
35. A method of operating a programmable logic device (PLD), the method comprising:
setting a supply voltage level of a first circuit in the programmable logic device (PLD) to a first level;
determining whether a performance measure of the programmable logic device (PLD) meets a criterion; and
adjusting the supply voltage level of the first circuit depending on whether the performance measure of the programmable logic device (PLD) meets the criterion.
36. The method according to claim 35, wherein determining whether a performance measure of the programmable logic device (PLD) meets a criterion further comprises obtaining the performance measure.
37. The method according to claim 36, wherein obtaining the performance measure further comprises sensing a quantity within the programmable logic device (PLD).
38. The method according to claim 37, wherein sensing a quantity within the programmable logic device (PLD) further comprises sensing a temperature.
39. The method according to claim 35, wherein adjusting the supply voltage level of the first circuit further comprises:
leaving the supply voltage level of the first circuit unchanged if the performance measure of the programmable logic device (PLD) meets the criterion; and
changing the supply voltage level of the first circuit to a second level if the performance measure of the programmable logic device (PLD) fails to meet the criterion.
40. The method according to claim 35, wherein the performance measure comprises a speed of operation of the first circuit.
41. The method according to claim 35, wherein the performance measure comprises a power consumption of the first circuit.
42. The method according to claim 35, wherein setting a supply voltage level of a first circuit in the programmable logic device (PLD) to a first level further comprises setting the supply voltage to a level derived from information received from a source external to the programmable logic device.
43. The method according to claim 35, wherein setting a supply voltage level of a first circuit in the programmable logic device (PLD) to a first level further comprises setting the supply voltage to a level specified by configuration data of the programmable logic device (PLD).
44. The method according to claim 35, further comprising using a feedback circuit to determine if the performance measure of the programmable logic device (PLD) meets the criterion.
45. A method of operating a programmable logic device (PLD) configured to function in an operating environment, the method comprising:
setting a supply voltage level of a first circuit in the programmable logic device (PLD) to a first level; and
adjusting the supply voltage level of the first circuit depending on at least one characteristic of the operating environment of the programmable logic device (PLD).
46. The method according to claim 45, wherein adjusting the supply voltage level of the first circuit further comprises adjusting the supply voltage level of the first circuit to a second level if the at least one characteristic of the operating environment indicates that a performance of the first circuit should be changed.
47. The method according to claim 46, wherein adjusting the supply voltage level of the first circuit further comprises increasing an operating speed of the first circuit if the at least one characteristic of the operating environment indicates that a performance of the first circuit should be increased.
48. The method according to claim 47, wherein adjusting the supply voltage level of the first circuit further comprises trading off the operating speed of the first circuit with a power consumption of the first circuit.
49. The method according to claim 46, wherein adjusting the body-bias level of the at least one transistor further comprises decreasing an operating speed of the first circuit if the at least one characteristic of the operating environment indicates that a performance of the first circuit should be decreased.
US11/006,420 2004-12-07 2004-12-07 Apparatus and methods for adjusting performance characteristics of programmable logic devices Abandoned US20060119382A1 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
US11/006,420 US20060119382A1 (en) 2004-12-07 2004-12-07 Apparatus and methods for adjusting performance characteristics of programmable logic devices
EP05026293A EP1670140A3 (en) 2004-12-07 2005-12-02 Apparatus and method for adjusting performance characteristics of programmable logic devices
JP2005352310A JP2006166458A (en) 2004-12-07 2005-12-06 Apparatus and methods for adjusting performance characteristics of programmable logic device
CNA2005101310699A CN1797951A (en) 2004-12-07 2005-12-07 Apparatus and method for adjusting performance characteristics of programmable logic devices
US11/420,736 US20060202713A1 (en) 2004-12-07 2006-05-27 Apparatus and methods for adjusting performance characteristics of circuitry in programmable logic devices
US11/420,737 US7986160B2 (en) 2004-12-07 2006-05-27 Apparatus and methods for adjusting performance characteristics and power consumption of programmable logic devices
JP2011256197A JP2012075168A (en) 2004-12-07 2011-11-24 Apparatus and method for adjusting performance characteristics of programmable logic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/006,420 US20060119382A1 (en) 2004-12-07 2004-12-07 Apparatus and methods for adjusting performance characteristics of programmable logic devices

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US11/420,736 Continuation-In-Part US20060202713A1 (en) 2004-12-07 2006-05-27 Apparatus and methods for adjusting performance characteristics of circuitry in programmable logic devices
US11/420,737 Continuation-In-Part US7986160B2 (en) 2004-12-07 2006-05-27 Apparatus and methods for adjusting performance characteristics and power consumption of programmable logic devices

Publications (1)

Publication Number Publication Date
US20060119382A1 true US20060119382A1 (en) 2006-06-08

Family

ID=36076773

Family Applications (3)

Application Number Title Priority Date Filing Date
US11/006,420 Abandoned US20060119382A1 (en) 2004-12-07 2004-12-07 Apparatus and methods for adjusting performance characteristics of programmable logic devices
US11/420,737 Active US7986160B2 (en) 2004-12-07 2006-05-27 Apparatus and methods for adjusting performance characteristics and power consumption of programmable logic devices
US11/420,736 Abandoned US20060202713A1 (en) 2004-12-07 2006-05-27 Apparatus and methods for adjusting performance characteristics of circuitry in programmable logic devices

Family Applications After (2)

Application Number Title Priority Date Filing Date
US11/420,737 Active US7986160B2 (en) 2004-12-07 2006-05-27 Apparatus and methods for adjusting performance characteristics and power consumption of programmable logic devices
US11/420,736 Abandoned US20060202713A1 (en) 2004-12-07 2006-05-27 Apparatus and methods for adjusting performance characteristics of circuitry in programmable logic devices

Country Status (4)

Country Link
US (3) US20060119382A1 (en)
EP (1) EP1670140A3 (en)
JP (2) JP2006166458A (en)
CN (1) CN1797951A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060209944A1 (en) * 2005-03-15 2006-09-21 Carballo Juan A Altering power consumption in communication links based on measured noise
US20070205802A1 (en) * 2006-03-06 2007-09-06 Srinivas Perisetty Adjustable transistor body bias generation circuitry with latch-up prevention
US20070205824A1 (en) * 2006-03-06 2007-09-06 Srinivas Perisetty Adjustable transistor body bias circuitry
US20070205801A1 (en) * 2006-03-06 2007-09-06 Srinivas Perisetty Latch-up prevention circuitry for integrated circuits with transistor body biasing
US7295036B1 (en) * 2005-11-30 2007-11-13 Altera Corporation Method and system for reducing static leakage current in programmable logic devices
US20080219079A1 (en) * 2007-03-08 2008-09-11 Samsung Electronics Co., Ltd. Semiconductor memory device and output drive circuit thereof
US20080263490A1 (en) * 2005-08-16 2008-10-23 Altera Corporation Apparatus and methods for optimizing the performance of programmable logic devices
US20090267588A1 (en) * 2008-04-23 2009-10-29 Schmitz Michael J Method and apparatus to dynamically control impedance to maximize power supply
US20090273361A1 (en) * 2008-05-02 2009-11-05 Texas Instruments Incorporated Localized calibration of programmable digital logic cells
US8823405B1 (en) 2010-09-10 2014-09-02 Xilinx, Inc. Integrated circuit with power gating
US20170116363A1 (en) * 2015-10-23 2017-04-27 Dspace Digital Signal Processing And Control Engineering Gmbh Method for determining the power consumption of a programmable logic device
US20180254778A1 (en) * 2015-09-25 2018-09-06 Intel Corporation Local cell-level power gating switch

Families Citing this family (72)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7504854B1 (en) 2003-09-19 2009-03-17 Xilinx, Inc. Regulating unused/inactive resources in programmable logic devices for static power reduction
US7498836B1 (en) 2003-09-19 2009-03-03 Xilinx, Inc. Programmable low power modes for embedded memory blocks
US7581124B1 (en) 2003-09-19 2009-08-25 Xilinx, Inc. Method and mechanism for controlling power consumption of an integrated circuit
US7098689B1 (en) 2003-09-19 2006-08-29 Xilinx, Inc. Disabling unused/inactive resources in programmable logic devices for static power reduction
US7549139B1 (en) 2003-09-19 2009-06-16 Xilinx, Inc. Tuning programmable logic devices for low-power design implementation
US7622947B1 (en) * 2003-12-18 2009-11-24 Nvidia Corporation Redundant circuit presents connections on specified I/O ports
US7498839B1 (en) * 2004-10-22 2009-03-03 Xilinx, Inc. Low power zones for programmable logic devices
US8209524B2 (en) 2005-08-29 2012-06-26 The Invention Science Fund I, Llc Cross-architecture optimization
US7539852B2 (en) 2005-08-29 2009-05-26 Searete, Llc Processor resource management
US8255745B2 (en) 2005-08-29 2012-08-28 The Invention Science Fund I, Llc Hardware-error tolerant computing
US20070050608A1 (en) * 2005-08-29 2007-03-01 Searete Llc, A Limited Liability Corporatin Of The State Of Delaware Hardware-generated and historically-based execution optimization
US7627739B2 (en) * 2005-08-29 2009-12-01 Searete, Llc Optimization of a hardware resource shared by a multiprocessor
US7653834B2 (en) 2005-08-29 2010-01-26 Searete, Llc Power sparing synchronous apparatus
US7647487B2 (en) * 2005-08-29 2010-01-12 Searete, Llc Instruction-associated processor resource optimization
US7877584B2 (en) * 2005-08-29 2011-01-25 The Invention Science Fund I, Llc Predictive processor resource management
US7739524B2 (en) 2005-08-29 2010-06-15 The Invention Science Fund I, Inc Power consumption management
US8516300B2 (en) 2005-08-29 2013-08-20 The Invention Science Fund I, Llc Multi-votage synchronous systems
US8375247B2 (en) 2005-08-29 2013-02-12 The Invention Science Fund I, Llc Handling processor computational errors
US8214191B2 (en) * 2005-08-29 2012-07-03 The Invention Science Fund I, Llc Cross-architecture execution optimization
US8423824B2 (en) 2005-08-29 2013-04-16 The Invention Science Fund I, Llc Power sparing synchronous apparatus
US8181004B2 (en) * 2005-08-29 2012-05-15 The Invention Science Fund I, Llc Selecting a resource management policy for a resource available to a processor
US7725693B2 (en) * 2005-08-29 2010-05-25 Searete, Llc Execution optimization using a processor resource management policy saved in an association with an instruction group
US7779213B2 (en) * 2005-08-29 2010-08-17 The Invention Science Fund I, Inc Optimization of instruction group execution through hardware resource management policies
US8112286B2 (en) 2005-10-31 2012-02-07 Panasonic Corporation Stereo encoding device, and stereo signal predicting method
US7498835B1 (en) 2005-11-04 2009-03-03 Xilinx, Inc. Implementation of low power standby modes for integrated circuits
US7345944B1 (en) 2006-01-11 2008-03-18 Xilinx, Inc. Programmable detection of power failure in an integrated circuit
US7936184B2 (en) * 2006-02-24 2011-05-03 Altera Corporation Apparatus and methods for adjusting performance of programmable logic devices
US7903679B1 (en) * 2006-04-11 2011-03-08 Altera Corporation Power supply filtering for programmable logic device having heterogeneous serial interface architecture
US8001407B2 (en) 2006-10-31 2011-08-16 Hewlett-Packard Development Company, L.P. Server configured for managing power and performance
WO2009063584A1 (en) * 2007-11-13 2009-05-22 Panasonic Corporation Programmable device, control method of device and information processing system
US9043617B2 (en) * 2008-01-30 2015-05-26 Kyocera Corporation Device incorporating data communication function
US7472362B1 (en) 2008-03-31 2008-12-30 International Business Machines Corporation Method of minimizing phase noise
US7926015B2 (en) * 2008-03-31 2011-04-12 International Business Machines Corporation Optimization method for fractional-N phased-lock-loop (PLL) system
US7750697B2 (en) 2008-03-31 2010-07-06 International Business Machines Corporation Fractional-N phased-lock-loop (PLL) system
US8086974B2 (en) * 2008-03-31 2011-12-27 International Business Machines Corporation Structure for fractional-N phased-lock-loop (PLL) system
US8112734B2 (en) * 2008-09-29 2012-02-07 Lsi Corporation Optimization with adaptive body biasing
GB2464510B (en) * 2008-10-17 2013-09-04 Advanced Risc Mach Ltd Power control of an integrated circuit including an array of interconnected configurable logic elements
US8341582B2 (en) * 2009-01-30 2012-12-25 Active-Semi, Inc. Programmable analog tile configuration tool
US9003340B2 (en) * 2009-01-30 2015-04-07 Active-Semi, Inc. Communicating configuration information across a programmable analog tile to another tile
US8225260B2 (en) 2009-01-30 2012-07-17 Active-Semi, Inc. Programmable analog tile placement tool
US8079007B2 (en) * 2009-01-30 2011-12-13 Active-Semi, Inc. Programmable analog tile programming tool
US8219956B2 (en) * 2009-01-30 2012-07-10 Active-Semi, Inc. Analog tile selection, placement, configuration and programming tool
US9735779B1 (en) * 2009-07-07 2017-08-15 Altera Corporation Apparatus and methods for on-die temperature sensing to improve FPGA performance
US8971833B2 (en) * 2010-09-28 2015-03-03 Apple Inc. Electronic device with dynamic drive strength adjustment to mitigate impact of system noise on wireless performance
US8612789B2 (en) * 2011-01-13 2013-12-17 Xilinx, Inc. Power management within an integrated circuit
KR101318423B1 (en) * 2011-06-24 2013-10-15 위니맥스 주식회사 Water filter assembly and refrigerator and water purifier having the same
US8461869B1 (en) * 2011-08-19 2013-06-11 Altera Corporation Apparatus for configuring performance of field programmable gate arrays and associated methods
US8698516B2 (en) * 2011-08-19 2014-04-15 Altera Corporation Apparatus for improving performance of field programmable gate arrays and associated methods
US8705605B1 (en) 2011-11-03 2014-04-22 Altera Corporation Technique for providing loopback testing with single stage equalizer
US9436250B1 (en) * 2011-12-19 2016-09-06 Altera Corporation Apparatus for improving power consumption of communication circuitry and associated methods
US9647668B2 (en) 2012-01-13 2017-05-09 Altera Corporation Apparatus for flexible electronic interfaces and associated methods
US8797106B2 (en) 2012-03-28 2014-08-05 Micron Technology, Inc. Circuits, apparatuses, and methods for oscillators
US9348959B1 (en) * 2012-06-29 2016-05-24 Xilinx, Inc. Optimizing supply voltage and threshold voltage
US9223384B2 (en) 2012-07-31 2015-12-29 Qualcomm Incorporated Synthesizing intermediate performance levels in integrated circuits, and related processor systems, methods, and computer-readable media
KR102112364B1 (en) * 2012-12-06 2020-05-18 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device
US8836372B1 (en) * 2013-03-01 2014-09-16 Raytheon Company Minimizing power consumption in asynchronous dataflow architectures
US9281820B2 (en) 2013-03-01 2016-03-08 Raytheon Company Minimizing power consumption in asynchronous dataflow architectures
US9525571B2 (en) 2013-03-05 2016-12-20 Lattice Semiconductor Corporation Calibration of single-ended high-speed interfaces
US9372520B2 (en) * 2013-08-09 2016-06-21 Globalfoundries Inc. Reverse performance binning
CN103983856B (en) * 2014-05-09 2017-03-01 京东方科技集团股份有限公司 A kind of Low Voltage Differential Signal Interface Matching resistance automatic checkout equipment and method
US9496871B1 (en) * 2014-08-18 2016-11-15 Xilinx, Inc. Programmable power reduction technique using transistor threshold drops
US9569577B2 (en) * 2014-10-15 2017-02-14 Freescale Semiconductor, Inc. Identifying noise couplings in integrated circuit
US9419624B2 (en) 2014-11-12 2016-08-16 Xilinx, Inc. Power management system for integrated circuits
US9917507B2 (en) 2015-05-28 2018-03-13 Sandisk Technologies Llc Dynamic clock period modulation scheme for variable charge pump load currents
US9647536B2 (en) 2015-07-28 2017-05-09 Sandisk Technologies Llc High voltage generation using low voltage devices
US9520776B1 (en) 2015-09-18 2016-12-13 Sandisk Technologies Llc Selective body bias for charge pump transfer switches
KR102287074B1 (en) 2016-07-29 2021-08-06 애플 인크. Touch sensor panel with multi-power domain chip configuration
CN109565280B (en) 2016-08-19 2023-02-17 株式会社半导体能源研究所 Power supply control method for semiconductor device
WO2019067268A1 (en) 2017-09-29 2019-04-04 Apple Inc. Multi modal touch controller
US10990221B2 (en) * 2017-09-29 2021-04-27 Apple Inc. Multi-power domain touch sensing
US10863600B2 (en) 2018-06-19 2020-12-08 Power Integrations, Inc. Power converter with current matching
US11016616B2 (en) 2018-09-28 2021-05-25 Apple Inc. Multi-domain touch sensing with touch and display circuitry operable in guarded power domain

Citations (75)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US677978A (en) * 1900-06-23 1901-07-09 Eugene T Granbery Machine for transferring mail-bags.
US5332929A (en) * 1993-04-08 1994-07-26 Xilinx, Inc. Power management for programmable logic devices
US5341034A (en) * 1993-02-11 1994-08-23 Benchmarq Microelectronics, Inc. Backup battery power controller having channel regions of transistors being biased by power supply or battery
US5422591A (en) * 1994-01-03 1995-06-06 Sgs-Thomson Microelectronics, Inc. Output driver circuit with body bias control for multiple power supply operation
US5610533A (en) * 1993-11-29 1997-03-11 Mitsubishi Denki Kabushiki Kaisha Switched substrate bias for logic circuits
US5689144A (en) * 1996-05-15 1997-11-18 Siliconix Incorporated Four-terminal power MOSFET switch having reduced threshold voltage and on-resistance
US5734275A (en) * 1996-07-18 1998-03-31 Advanced Micro Devices, Inc. Programmable logic device having a sense amplifier with virtual ground
US5744996A (en) * 1992-07-01 1998-04-28 International Business Machines Corporation CMOS integrated semiconductor circuit
US5781062A (en) * 1995-08-21 1998-07-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit
US5841694A (en) * 1997-07-30 1998-11-24 Programmable Silicon Solutions High performance programmable interconnect
US5852552A (en) * 1996-06-27 1998-12-22 Hyundai Electronics Industries Co.Ltd High voltage generator with a latch-up prevention function
US5905402A (en) * 1996-06-01 1999-05-18 Lg Semicon Co., Ltd Voltage pump circuit having an independent well-bias voltage
US5942784A (en) * 1996-07-16 1999-08-24 Kabushiki Kaisha Toshiba Semiconductor device
US6147508A (en) * 1998-08-20 2000-11-14 International Business Machines Corp. Power consumption control mechanism and method therefor
US6157691A (en) * 1998-04-14 2000-12-05 Lsi Logic Corporation Fully integrated phase-locked loop with resistor-less loop filer
US20010002796A1 (en) * 1998-12-31 2001-06-07 El-Ayat Khaled Ahmad Programmable multi-standard I/O architecture for FPGAs
US6271713B1 (en) * 1999-05-14 2001-08-07 Intel Corporation Dynamic threshold source follower voltage driver circuit
US20010012673A1 (en) * 2000-01-31 2001-08-09 Samsung Electronics Co., Ltd. Mos transistor having self-aligned well bias area and method of fabricating the same
US6292639B1 (en) * 1999-07-21 2001-09-18 Sharp Kabushiki Kaisha Contact charging device, process cartridge and image forming device having the same
US20010047506A1 (en) * 1998-12-15 2001-11-29 Houston Theodore W. System and method for controlling current in an integrated circuit
US20020005750A1 (en) * 1999-11-30 2002-01-17 James T. Kao Adaptive body biasing circuit and method
US6343044B1 (en) * 2000-10-04 2002-01-29 International Business Machines Corporation Super low-power generator system for embedded applications
US6351176B1 (en) * 1998-09-14 2002-02-26 Texas Instruments Incorporated Pulsing of body voltage for improved MOS integrated circuit performance
US20020024378A1 (en) * 1998-02-26 2002-02-28 Micron Technology, Inc. Threshold voltage compensation circuits for low voltage and low power CMOS integrated circuits
US20020029352A1 (en) * 1998-12-30 2002-03-07 Shekhar Y. Borkar Software control of transistor body bias in controlling chip parameters
US20020030533A1 (en) * 1997-06-20 2002-03-14 De Vivek K. Circuit including forward body bias from supply voltage and ground nodes
US20020033730A1 (en) * 2000-09-15 2002-03-21 Chi-Tai Yao Preset circuit and method for n-well bias of a CMOS circuit
US6366482B1 (en) * 1999-12-31 2002-04-02 Hyundai Electronics Industries Co., Ltd. Voltage conversion circuit
US20020041531A1 (en) * 1997-06-16 2002-04-11 Hitoshi Tanaka Semiconductor integrated circuit device
US6373281B1 (en) * 2001-01-22 2002-04-16 International Business Machines Corporation Tri-state dynamic body charge modulation for sensing devices in SOI RAM applications
US20020044076A1 (en) * 2000-08-30 2002-04-18 Chi-Tai Yao Current-steering D/A converter and unit cell
US6384674B2 (en) * 1999-01-04 2002-05-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having hierarchical power supply line structure improved in operating speed
US20020079951A1 (en) * 1997-06-20 2002-06-27 Shekhar Y. Borkar Employing transistor body bias in controlling chip parameters
US6429726B1 (en) * 2001-03-27 2002-08-06 Intel Corporation Robust forward body bias generation circuit with digital trimming for DC power supply variation
US20020118569A1 (en) * 2000-12-28 2002-08-29 Samsung Electronics Co., Ltd. Method of programming non-volatile semiconductor memory device
US20020140496A1 (en) * 2000-02-16 2002-10-03 Ali Keshavarzi Forward body biased transistors with reduced temperature
US20020155671A1 (en) * 2001-04-18 2002-10-24 International Business Machines Corporation SOI CMOS device with body to gate connection
US6476372B2 (en) * 1998-08-20 2002-11-05 Foveon, Inc. CMOS active pixel sensor using native transistors
US20020163377A1 (en) * 2001-03-28 2002-11-07 Bruneau David W. Forward body bias generation circuits based on diode clamps
US20020171461A1 (en) * 2001-05-18 2002-11-21 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with multiple power sources
US20020171468A1 (en) * 2001-04-26 2002-11-21 International Business Machines Corporation Apparatus for biasing ultra-low voltage logic circuits
US20020179876A1 (en) * 2001-05-30 2002-12-05 Pang Rick Wei-Shou Plug valve having seal segments with booster springs
US20030001658A1 (en) * 2000-11-28 2003-01-02 Koichi Matsumoto Semiconductor device
US20030001663A1 (en) * 2001-06-28 2003-01-02 Zhang Kevin X. Method and apparatus for dynamic leakage control
US20030005378A1 (en) * 2001-06-28 2003-01-02 Intel Corporation Body bias using scan chains
US20030001633A1 (en) * 2001-05-09 2003-01-02 Mitel Knowledge Corporation Master slave frame lock method
US20030016078A1 (en) * 2001-07-19 2003-01-23 Gene Hinterscher Bias generator and method for improving output skew voltage
US6525559B1 (en) * 2002-04-22 2003-02-25 Pericom Semiconductor Corp. Fail-safe circuit with low input impedance using active-transistor differential-line terminators
US20030038668A1 (en) * 2001-06-28 2003-02-27 Zhang Kevin X. Low power operation mechanism and method
US6535034B1 (en) * 1997-07-30 2003-03-18 Programmable Silicon Solutions High performance integrated circuit devices adaptable to use lower supply voltages with smaller device geometries
US20030053335A1 (en) * 2001-09-18 2003-03-20 Xilinx, Inc. Structures and methods for selectively applying a well bias to portions of a programmable device
US20030067042A1 (en) * 2001-10-05 2003-04-10 Gary Kaatz Stacked NMOS device biasing on MOS integrated circuits and methods therefor
US6549032B1 (en) * 2000-08-22 2003-04-15 Altera Corporation Integrated circuit devices with power supply detection circuitry
US20030080802A1 (en) * 2001-11-01 2003-05-01 Hitachi, Ltd. Semiconductor integrated circuit device
US20030117174A1 (en) * 1996-05-28 2003-06-26 Altera Corporation, A Corporation Of Delaware Programmable logic with lower internal voltage circuitry
US6590440B1 (en) * 1994-12-30 2003-07-08 Siliconix, Incorporated Low-side bidirectional battery disconnect switch
US6597203B2 (en) * 2001-03-14 2003-07-22 Micron Technology, Inc. CMOS gate array with vertical transistors
US20030141929A1 (en) * 2002-01-31 2003-07-31 Intel Corporation Differential amplifier offset adjustment
US20030151428A1 (en) * 2002-02-12 2003-08-14 Ouyang Paul H. 5 Volt tolerant input/output buffer
US20030208611A1 (en) * 2002-05-03 2003-11-06 Sonics, Inc. On -chip inter-network performance optimization using configurable performance parameters
US20030209752A1 (en) * 2002-05-10 2003-11-13 Jin Cai EEPROM device with substrate hot-electron injector for low-power
US6650141B2 (en) * 2001-12-14 2003-11-18 Lattice Semiconductor Corporation High speed interface for a programmable interconnect circuit
US20030218478A1 (en) * 2002-05-24 2003-11-27 Sani Mehdi Hamidi Regulation of crowbar current in circuits employing footswitches/headswitches
US20040056679A1 (en) * 2002-09-20 2004-03-25 Saroj Pathak High speed zero DC power programmable logic device (PLD) architecture
US6731158B1 (en) * 2002-06-13 2004-05-04 University Of New Mexico Self regulating body bias generator
US6744301B1 (en) * 2000-11-07 2004-06-01 Intel Corporation System using body-biased sleep transistors to reduce leakage power while minimizing performance penalties and noise
US20040123170A1 (en) * 2002-12-23 2004-06-24 Tschanz James W. Method and apparatus for reducing power consumption through dynamic control of supply voltage and body bias
US6757196B1 (en) * 2001-03-22 2004-06-29 Aplus Flash Technology, Inc. Two transistor flash memory cell for use in EEPROM arrays with a programmable logic device
US20040189412A1 (en) * 2003-03-25 2004-09-30 Murata Manufacturing Co., Ltd. Temperature compensated piezoelectric oscillator and electronic device using the same
US20050231274A1 (en) * 2004-04-14 2005-10-20 Broadcom Corporation Low-noise, fast-settling bias circuit and method
US20050258862A1 (en) * 2004-05-19 2005-11-24 Irfan Rahim Apparatus and methods for adjusting performance of programmable logic devices
US6972599B2 (en) * 2002-08-27 2005-12-06 Micron Technology Inc. Pseudo CMOS dynamic logic with delayed clocks
US20060038605A1 (en) * 2002-08-08 2006-02-23 Koninklijke Philips Electronics N.V. Circuit and method for controlling the threshold voltage of trransistors
US7098689B1 (en) * 2003-09-19 2006-08-29 Xilinx, Inc. Disabling unused/inactive resources in programmable logic devices for static power reduction
US7112997B1 (en) * 2004-05-19 2006-09-26 Altera Corporation Apparatus and methods for multi-gate silicon-on-insulator transistors

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0783254B2 (en) * 1989-03-22 1995-09-06 株式会社東芝 Semiconductor integrated circuit
JP3251735B2 (en) * 1992-09-25 2002-01-28 株式会社東芝 Semiconductor integrated circuit device
JPH08162884A (en) * 1994-11-30 1996-06-21 Sony Corp Noise elimination circuit
JPH08181598A (en) * 1994-12-27 1996-07-12 Oki Electric Ind Co Ltd Semiconductor device
US5594368A (en) * 1995-04-19 1997-01-14 Kabushiki Kaisha Toshiba Low power combinational logic circuit
US5631606A (en) * 1995-08-01 1997-05-20 Information Storage Devices, Inc. Fully differential output CMOS power amplifier
JP3042761B2 (en) * 1995-08-07 2000-05-22 株式会社日立製作所 Program data generation method for programmable device in logic emulation system and program data generation device for programmable device
US5661685A (en) * 1995-09-25 1997-08-26 Xilinx, Inc. Programmable logic device with configurable power supply
US5787294A (en) * 1995-10-13 1998-07-28 Vlsi Technology, Inc. System for reducing the power consumption of a computer system and method therefor
US5600264A (en) * 1995-10-16 1997-02-04 Xilinx, Inc. Programmable single buffered six pass transistor configuration
JPH11195967A (en) * 1997-12-26 1999-07-21 Nec Corp Semiconductor integrated circuit and method for its delay time control
WO2000045437A1 (en) * 1999-01-26 2000-08-03 Hitachi, Ltd. Method of setting back bias of mos circuit, and mos integrated circuit
US6271679B1 (en) * 1999-03-24 2001-08-07 Altera Corporation I/O cell configuration for multiple I/O standards
US6425086B1 (en) * 1999-04-30 2002-07-23 Intel Corporation Method and apparatus for dynamic power control of a low power processor
JP3579633B2 (en) * 2000-05-19 2004-10-20 株式会社ルネサステクノロジ Semiconductor integrated circuit
JP2001345423A (en) * 2000-06-01 2001-12-14 Seiko Epson Corp Semiconductor integrated circuit device and manufacturing method thereof
GB2366709A (en) * 2000-06-30 2002-03-13 Graeme Roy Smith Modular software definable pre-amplifier
US6366128B1 (en) * 2000-09-05 2002-04-02 Xilinx, Inc. Circuit for producing low-voltage differential signals
US6952112B2 (en) * 2000-11-30 2005-10-04 Renesas Technology Corporation Output buffer circuit with control circuit for modifying supply voltage and transistor size
GB0103837D0 (en) * 2001-02-16 2001-04-04 Nallatech Ltd Programmable power supply for field programmable gate array modules
JP2004070805A (en) * 2002-08-08 2004-03-04 Fujitsu Ltd Semiconductor integrated circuit with controlled internal power source voltage
JP3986393B2 (en) * 2002-08-27 2007-10-03 富士通株式会社 Integrated circuit device having nonvolatile data storage circuit
US7051306B2 (en) * 2003-05-07 2006-05-23 Mosaid Technologies Corporation Managing power on integrated circuits using power islands
US7026840B1 (en) * 2004-03-02 2006-04-11 Altera Corporation Programmable logic device
EP1745344A1 (en) * 2004-05-05 2007-01-24 Koninklijke Philips Electronics N.V. A mobile apparatus comprising integrated circuit and method of powering down such circuit
US7479803B1 (en) * 2004-10-06 2009-01-20 Altera Corporation Techniques for debugging hard intellectual property blocks
US7529958B2 (en) * 2004-11-15 2009-05-05 Charles Roth Programmable power transition counter
KR101054946B1 (en) * 2005-02-23 2011-08-08 삼성전자주식회사 How to adjust the system on chip and voltage level with voltage level adjustment
US7548091B1 (en) * 2005-07-29 2009-06-16 Altera Corporation Method and apparatus to power down unused configuration random access memory cells

Patent Citations (85)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US677978A (en) * 1900-06-23 1901-07-09 Eugene T Granbery Machine for transferring mail-bags.
US5744996A (en) * 1992-07-01 1998-04-28 International Business Machines Corporation CMOS integrated semiconductor circuit
US5341034A (en) * 1993-02-11 1994-08-23 Benchmarq Microelectronics, Inc. Backup battery power controller having channel regions of transistors being biased by power supply or battery
US5332929A (en) * 1993-04-08 1994-07-26 Xilinx, Inc. Power management for programmable logic devices
US5610533A (en) * 1993-11-29 1997-03-11 Mitsubishi Denki Kabushiki Kaisha Switched substrate bias for logic circuits
US5703522A (en) * 1993-11-29 1997-12-30 Mitsubishi Denki Kabushiki Kaisha Switched substrate bias for MOS-DRAM circuits
US6232793B1 (en) * 1993-11-29 2001-05-15 Mitsubishi Denki Kabushiki Kaisha Switched backgate bias for FET
US5854561A (en) * 1993-11-29 1998-12-29 Mitsubishi Denki Kabushiki Kaisha Switched substrate bias for MOS DRAM circuits
US5422591A (en) * 1994-01-03 1995-06-06 Sgs-Thomson Microelectronics, Inc. Output driver circuit with body bias control for multiple power supply operation
US6590440B1 (en) * 1994-12-30 2003-07-08 Siliconix, Incorporated Low-side bidirectional battery disconnect switch
US5781062A (en) * 1995-08-21 1998-07-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit
US5689144A (en) * 1996-05-15 1997-11-18 Siliconix Incorporated Four-terminal power MOSFET switch having reduced threshold voltage and on-resistance
US20030117174A1 (en) * 1996-05-28 2003-06-26 Altera Corporation, A Corporation Of Delaware Programmable logic with lower internal voltage circuitry
US5905402A (en) * 1996-06-01 1999-05-18 Lg Semicon Co., Ltd Voltage pump circuit having an independent well-bias voltage
US5852552A (en) * 1996-06-27 1998-12-22 Hyundai Electronics Industries Co.Ltd High voltage generator with a latch-up prevention function
US5942784A (en) * 1996-07-16 1999-08-24 Kabushiki Kaisha Toshiba Semiconductor device
US5734275A (en) * 1996-07-18 1998-03-31 Advanced Micro Devices, Inc. Programmable logic device having a sense amplifier with virtual ground
US20020041531A1 (en) * 1997-06-16 2002-04-11 Hitoshi Tanaka Semiconductor integrated circuit device
US20020030533A1 (en) * 1997-06-20 2002-03-14 De Vivek K. Circuit including forward body bias from supply voltage and ground nodes
US20020079951A1 (en) * 1997-06-20 2002-06-27 Shekhar Y. Borkar Employing transistor body bias in controlling chip parameters
US6535034B1 (en) * 1997-07-30 2003-03-18 Programmable Silicon Solutions High performance integrated circuit devices adaptable to use lower supply voltages with smaller device geometries
US5841694A (en) * 1997-07-30 1998-11-24 Programmable Silicon Solutions High performance programmable interconnect
US20020024378A1 (en) * 1998-02-26 2002-02-28 Micron Technology, Inc. Threshold voltage compensation circuits for low voltage and low power CMOS integrated circuits
US20020031028A1 (en) * 1998-02-26 2002-03-14 Micron Technology, Inc. Threshold voltage compensation circuits for low voltage and low power CMOS integrated circuits
US6157691A (en) * 1998-04-14 2000-12-05 Lsi Logic Corporation Fully integrated phase-locked loop with resistor-less loop filer
US6147508A (en) * 1998-08-20 2000-11-14 International Business Machines Corp. Power consumption control mechanism and method therefor
US6476372B2 (en) * 1998-08-20 2002-11-05 Foveon, Inc. CMOS active pixel sensor using native transistors
US6351176B1 (en) * 1998-09-14 2002-02-26 Texas Instruments Incorporated Pulsing of body voltage for improved MOS integrated circuit performance
US20010047506A1 (en) * 1998-12-15 2001-11-29 Houston Theodore W. System and method for controlling current in an integrated circuit
US6484265B2 (en) * 1998-12-30 2002-11-19 Intel Corporation Software control of transistor body bias in controlling chip parameters
US20020029352A1 (en) * 1998-12-30 2002-03-07 Shekhar Y. Borkar Software control of transistor body bias in controlling chip parameters
US20010002796A1 (en) * 1998-12-31 2001-06-07 El-Ayat Khaled Ahmad Programmable multi-standard I/O architecture for FPGAs
US6384674B2 (en) * 1999-01-04 2002-05-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having hierarchical power supply line structure improved in operating speed
US6271713B1 (en) * 1999-05-14 2001-08-07 Intel Corporation Dynamic threshold source follower voltage driver circuit
US6292639B1 (en) * 1999-07-21 2001-09-18 Sharp Kabushiki Kaisha Contact charging device, process cartridge and image forming device having the same
US20020005750A1 (en) * 1999-11-30 2002-01-17 James T. Kao Adaptive body biasing circuit and method
US6366482B1 (en) * 1999-12-31 2002-04-02 Hyundai Electronics Industries Co., Ltd. Voltage conversion circuit
US20010012673A1 (en) * 2000-01-31 2001-08-09 Samsung Electronics Co., Ltd. Mos transistor having self-aligned well bias area and method of fabricating the same
US20020140496A1 (en) * 2000-02-16 2002-10-03 Ali Keshavarzi Forward body biased transistors with reduced temperature
US6549032B1 (en) * 2000-08-22 2003-04-15 Altera Corporation Integrated circuit devices with power supply detection circuitry
US20020044076A1 (en) * 2000-08-30 2002-04-18 Chi-Tai Yao Current-steering D/A converter and unit cell
US20020033730A1 (en) * 2000-09-15 2002-03-21 Chi-Tai Yao Preset circuit and method for n-well bias of a CMOS circuit
US6343044B1 (en) * 2000-10-04 2002-01-29 International Business Machines Corporation Super low-power generator system for embedded applications
US6744301B1 (en) * 2000-11-07 2004-06-01 Intel Corporation System using body-biased sleep transistors to reduce leakage power while minimizing performance penalties and noise
US20030001658A1 (en) * 2000-11-28 2003-01-02 Koichi Matsumoto Semiconductor device
US20020118569A1 (en) * 2000-12-28 2002-08-29 Samsung Electronics Co., Ltd. Method of programming non-volatile semiconductor memory device
US6614688B2 (en) * 2000-12-28 2003-09-02 Samsung Electronic Co. Ltd. Method of programming non-volatile semiconductor memory device
US6373281B1 (en) * 2001-01-22 2002-04-16 International Business Machines Corporation Tri-state dynamic body charge modulation for sensing devices in SOI RAM applications
US6597203B2 (en) * 2001-03-14 2003-07-22 Micron Technology, Inc. CMOS gate array with vertical transistors
US6757196B1 (en) * 2001-03-22 2004-06-29 Aplus Flash Technology, Inc. Two transistor flash memory cell for use in EEPROM arrays with a programmable logic device
US6429726B1 (en) * 2001-03-27 2002-08-06 Intel Corporation Robust forward body bias generation circuit with digital trimming for DC power supply variation
US20020163377A1 (en) * 2001-03-28 2002-11-07 Bruneau David W. Forward body bias generation circuits based on diode clamps
US20020155671A1 (en) * 2001-04-18 2002-10-24 International Business Machines Corporation SOI CMOS device with body to gate connection
US6670655B2 (en) * 2001-04-18 2003-12-30 International Business Machines Corporation SOI CMOS device with body to gate connection
US20020171468A1 (en) * 2001-04-26 2002-11-21 International Business Machines Corporation Apparatus for biasing ultra-low voltage logic circuits
US6605981B2 (en) * 2001-04-26 2003-08-12 International Business Machines Corporation Apparatus for biasing ultra-low voltage logic circuits
US20030001633A1 (en) * 2001-05-09 2003-01-02 Mitel Knowledge Corporation Master slave frame lock method
US20020171461A1 (en) * 2001-05-18 2002-11-21 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with multiple power sources
US20020179876A1 (en) * 2001-05-30 2002-12-05 Pang Rick Wei-Shou Plug valve having seal segments with booster springs
US20030038668A1 (en) * 2001-06-28 2003-02-27 Zhang Kevin X. Low power operation mechanism and method
US20030001663A1 (en) * 2001-06-28 2003-01-02 Zhang Kevin X. Method and apparatus for dynamic leakage control
US20030005378A1 (en) * 2001-06-28 2003-01-02 Intel Corporation Body bias using scan chains
US20030016078A1 (en) * 2001-07-19 2003-01-23 Gene Hinterscher Bias generator and method for improving output skew voltage
US20030053335A1 (en) * 2001-09-18 2003-03-20 Xilinx, Inc. Structures and methods for selectively applying a well bias to portions of a programmable device
US20040025135A1 (en) * 2001-09-18 2004-02-05 Xilinx, Inc. Structures and methods for selectively applying a well bias to portions of a programmable device
US20030067042A1 (en) * 2001-10-05 2003-04-10 Gary Kaatz Stacked NMOS device biasing on MOS integrated circuits and methods therefor
US20030080802A1 (en) * 2001-11-01 2003-05-01 Hitachi, Ltd. Semiconductor integrated circuit device
US6650141B2 (en) * 2001-12-14 2003-11-18 Lattice Semiconductor Corporation High speed interface for a programmable interconnect circuit
US20030141929A1 (en) * 2002-01-31 2003-07-31 Intel Corporation Differential amplifier offset adjustment
US20030151428A1 (en) * 2002-02-12 2003-08-14 Ouyang Paul H. 5 Volt tolerant input/output buffer
US6525559B1 (en) * 2002-04-22 2003-02-25 Pericom Semiconductor Corp. Fail-safe circuit with low input impedance using active-transistor differential-line terminators
US20030208611A1 (en) * 2002-05-03 2003-11-06 Sonics, Inc. On -chip inter-network performance optimization using configurable performance parameters
US20030209752A1 (en) * 2002-05-10 2003-11-13 Jin Cai EEPROM device with substrate hot-electron injector for low-power
US20030218478A1 (en) * 2002-05-24 2003-11-27 Sani Mehdi Hamidi Regulation of crowbar current in circuits employing footswitches/headswitches
US6731158B1 (en) * 2002-06-13 2004-05-04 University Of New Mexico Self regulating body bias generator
US20060038605A1 (en) * 2002-08-08 2006-02-23 Koninklijke Philips Electronics N.V. Circuit and method for controlling the threshold voltage of trransistors
US6972599B2 (en) * 2002-08-27 2005-12-06 Micron Technology Inc. Pseudo CMOS dynamic logic with delayed clocks
US6980033B2 (en) * 2002-08-27 2005-12-27 Micron Technology, Inc. Pseudo CMOS dynamic logic with delayed clocks
US20040056679A1 (en) * 2002-09-20 2004-03-25 Saroj Pathak High speed zero DC power programmable logic device (PLD) architecture
US20040123170A1 (en) * 2002-12-23 2004-06-24 Tschanz James W. Method and apparatus for reducing power consumption through dynamic control of supply voltage and body bias
US20040189412A1 (en) * 2003-03-25 2004-09-30 Murata Manufacturing Co., Ltd. Temperature compensated piezoelectric oscillator and electronic device using the same
US7098689B1 (en) * 2003-09-19 2006-08-29 Xilinx, Inc. Disabling unused/inactive resources in programmable logic devices for static power reduction
US20050231274A1 (en) * 2004-04-14 2005-10-20 Broadcom Corporation Low-noise, fast-settling bias circuit and method
US20050258862A1 (en) * 2004-05-19 2005-11-24 Irfan Rahim Apparatus and methods for adjusting performance of programmable logic devices
US7112997B1 (en) * 2004-05-19 2006-09-26 Altera Corporation Apparatus and methods for multi-gate silicon-on-insulator transistors

Cited By (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7418032B2 (en) * 2005-03-15 2008-08-26 International Business Machines Corporation Altering power consumption in communication links based on measured noise
US7567614B2 (en) 2005-03-15 2009-07-28 International Business Machines Corporation Altering power consumption in communication links based on measured noise
US20060209944A1 (en) * 2005-03-15 2006-09-21 Carballo Juan A Altering power consumption in communication links based on measured noise
US20080232530A1 (en) * 2005-03-15 2008-09-25 International Business Machines Corporation Altering power consumption in communication links based on measured noise
US20120089958A1 (en) * 2005-08-16 2012-04-12 Altera Corporation Apparatus and Methods for Optimizing the Performance of Programmable Logic Devices
US8103975B2 (en) * 2005-08-16 2012-01-24 Altera Corporation Apparatus and methods for optimizing the performance of programmable logic devices using multiple supply voltage
US20080263490A1 (en) * 2005-08-16 2008-10-23 Altera Corporation Apparatus and methods for optimizing the performance of programmable logic devices
US7295036B1 (en) * 2005-11-30 2007-11-13 Altera Corporation Method and system for reducing static leakage current in programmable logic devices
US7501849B2 (en) 2006-03-06 2009-03-10 Altera Corporation Latch-up prevention circuitry for integrated circuits with transistor body biasing
US7514953B2 (en) 2006-03-06 2009-04-07 Altera Corporation Adjustable transistor body bias generation circuitry with latch-up prevention
US20080094100A1 (en) * 2006-03-06 2008-04-24 Altera Corporation Adjustable transistor body bias generation circuitry with latch-up prevention
US20080258802A1 (en) * 2006-03-06 2008-10-23 Srinivas Perisetty Adjustable transistor body bias circuitry
US7355437B2 (en) 2006-03-06 2008-04-08 Altera Corporation Latch-up prevention circuitry for integrated circuits with transistor body biasing
US7495471B2 (en) 2006-03-06 2009-02-24 Altera Corporation Adjustable transistor body bias circuitry
US7330049B2 (en) 2006-03-06 2008-02-12 Altera Corporation Adjustable transistor body bias generation circuitry with latch-up prevention
US20070205824A1 (en) * 2006-03-06 2007-09-06 Srinivas Perisetty Adjustable transistor body bias circuitry
US20070205801A1 (en) * 2006-03-06 2007-09-06 Srinivas Perisetty Latch-up prevention circuitry for integrated circuits with transistor body biasing
US7592832B2 (en) 2006-03-06 2009-09-22 Altera Corporation Adjustable transistor body bias circuitry
US20070205802A1 (en) * 2006-03-06 2007-09-06 Srinivas Perisetty Adjustable transistor body bias generation circuitry with latch-up prevention
US20080219079A1 (en) * 2007-03-08 2008-09-11 Samsung Electronics Co., Ltd. Semiconductor memory device and output drive circuit thereof
US7825692B2 (en) * 2007-03-08 2010-11-02 Samsung Electronics Co., Ltd. Semiconductor memory device and output drive circuit thereof
US20090267588A1 (en) * 2008-04-23 2009-10-29 Schmitz Michael J Method and apparatus to dynamically control impedance to maximize power supply
US20090273361A1 (en) * 2008-05-02 2009-11-05 Texas Instruments Incorporated Localized calibration of programmable digital logic cells
US8102187B2 (en) * 2008-05-02 2012-01-24 Texas Instruments Incorporated Localized calibration of programmable digital logic cells
US8823405B1 (en) 2010-09-10 2014-09-02 Xilinx, Inc. Integrated circuit with power gating
US20180254778A1 (en) * 2015-09-25 2018-09-06 Intel Corporation Local cell-level power gating switch
US10659046B2 (en) * 2015-09-25 2020-05-19 Intel Corporation Local cell-level power gating switch
US20170116363A1 (en) * 2015-10-23 2017-04-27 Dspace Digital Signal Processing And Control Engineering Gmbh Method for determining the power consumption of a programmable logic device
US10102325B2 (en) * 2015-10-23 2018-10-16 Dspace Digital Signal Processing And Control Engineering Gmbh Method for determining the power consumption of a programmable logic device

Also Published As

Publication number Publication date
JP2006166458A (en) 2006-06-22
US7986160B2 (en) 2011-07-26
US20060202713A1 (en) 2006-09-14
US20060202714A1 (en) 2006-09-14
EP1670140A3 (en) 2009-03-25
EP1670140A2 (en) 2006-06-14
CN1797951A (en) 2006-07-05
JP2012075168A (en) 2012-04-12

Similar Documents

Publication Publication Date Title
US20060119382A1 (en) Apparatus and methods for adjusting performance characteristics of programmable logic devices
US7348827B2 (en) Apparatus and methods for adjusting performance of programmable logic devices
US7415690B2 (en) Apparatus and methods for multi-gate silicon-on-insulator transistors
US8138786B2 (en) Apparatus and methods for adjusting performance of integrated circuits
US7400167B2 (en) Apparatus and methods for optimizing the performance of programmable logic devices
US7675317B2 (en) Integrated circuits with adjustable body bias and power supply circuitry
US8698516B2 (en) Apparatus for improving performance of field programmable gate arrays and associated methods
US8630113B1 (en) Apparatus for memory with improved performance and associated methods
US8198914B2 (en) Apparatus and methods for adjusting performance of programmable logic devices
US8461869B1 (en) Apparatus for configuring performance of field programmable gate arrays and associated methods
US20090302887A1 (en) Apparatus for power consumption reduction in programmable logic devices and associated methods
US10200037B2 (en) Apparatus and methods for on-die temperature sensing to improve FPGA performance
US10348311B2 (en) Apparatus for improving power consumption of communication circuitry and associated methods

Legal Events

Date Code Title Description
AS Assignment

Owner name: ALTERA CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SHUMARAYEV, SERGEY Y.;PATEL, RAKESH;REEL/FRAME:016067/0118;SIGNING DATES FROM 20041115 TO 20041130

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

AS Assignment

Owner name: INTEL CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ALTERA CORPORATION;REEL/FRAME:060778/0032

Effective date: 20220708

AS Assignment

Owner name: TAHOE RESEARCH, LTD., IRELAND

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTEL CORPORATION;REEL/FRAME:061827/0686

Effective date: 20220718