US20060038766A1 - Driver circuit of display device - Google Patents
Driver circuit of display device Download PDFInfo
- Publication number
- US20060038766A1 US20060038766A1 US11/178,466 US17846605A US2006038766A1 US 20060038766 A1 US20060038766 A1 US 20060038766A1 US 17846605 A US17846605 A US 17846605A US 2006038766 A1 US2006038766 A1 US 2006038766A1
- Authority
- US
- United States
- Prior art keywords
- transistor
- signals
- level
- electric potential
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
Definitions
- the present invention relates to a driver circuit for driving scan lines or signal lines in a display device.
- Plane display devices typified by liquid crystal display devices, feature thinness, light weight, and low power consumption, and accordingly are in use for displays of various types of electric appliances.
- active-matrix liquid crystal display devices with a transistor arranged in each pixel have been increasingly in use for note personal computers and portable information terminal devices.
- p-Si TFTs polysilicon thin film transistors
- This establishment has made it possible to fabricate transistors in a smaller size, which are in use for liquid crystal display devices.
- the pixel part is configured by arranging a transistor at an intersection between each of a plurality of scan lines and its corresponding one of a plurality of signal lines, and the driver circuits respectively drive a group of scan lines and a group of signal lines.
- An electric potential difference between the high-level voltage and the low-level voltage of output signals from a driver circuit is used in order for the output signals from the driver circuit to control the writing of video signals into each pixel. For this reason, from the viewpoint of enabling the writing to be stable, it is desirable that the electric potential difference be as large as possible.
- a larger electric potential difference between the high-level voltage and the low-level voltage means a higher voltage stress being on the transistors. This is likely to reduce reliability in operation of each of the transistors that constitute the driver circuits.
- the larger electric potential difference leads driving the driver circuits at a higher voltage. This brings about a problem of requiring larger power consumption.
- An object of the present invention is to prevent voltage stress on each transistor from increasing, to concurrently make it possible to set larger an electric potential difference between the high-level voltage and the low-level voltage of output signals.
- a driver circuit for a display device is characterized by including shift resistors and buffers.
- Each of the shift resistors shifts the phase of input signals to be inputted thereinto, and outputs the signals with the shifted phase.
- Each of the buffers amplifies the amplitude of the output signals from the shift resistor corresponding to the buffer by use of enable signals, and outputs the signals with the amplified amplitude to a scan line or a signal line.
- the driver circuit is characterized in that an electric potential difference between the high-level voltage and the low-level voltage of the enable signals is used as an electric potential difference with which to drive the scan lines or the signal lines, and in that an electric potential difference between the high-level power supply voltage and the low-level power supply voltage respectively in the shift resistors and the buffers is set smaller than the electric potential difference between the high-level voltage and the low-level voltage of the enable signals.
- an electric potential difference between the high-level power supply voltage and the low-level power supply voltage respectively for the shift resistors and the buffers are set smaller than the electric potential difference between the high-level voltage and the low-level voltage of the enable signals.
- the electric potential difference between the high-level voltage and the low-level voltage is made larger with regard to output signals from each of the buffers, which are amplified by use of the enable signals.
- the shift resistors and the buffers are caused to operate by use of the high-level power supply voltage and the low-level power supply voltage, between which an electric potential difference is small. These help reduce voltage stress on each transistor.
- FIG. 1 shows a circuit diagram of a display device according to an embodiment.
- FIG. 2 shows a circuit diagram of a driver circuit in the display device.
- FIG. 3 shows a circuit diagram of a shift resistor and a buffer in the driver circuit.
- FIG. 4 shows a timing chart of the driver circuit operations.
- FIG. 5 shows diagram of output signals from the shift resistor and output signals from the buffer in an overlapping manner.
- FIG. 6 shows a circuit diagram of a shift resistor and a buffer in a driver circuit as a comparative example.
- FIG. 7 shows a timing chart of the driver circuit as the comparative example.
- FIG. 8 shows a diagram of output signals from the shift resistor and output signals from the buffer in the comparative example in an overlapping manner.
- FIG. 9 shows a circuit diagram of other configurations respectively of the shift resistor and the buffer in the driver circuit.
- a display device As shown in the circuit diagram of FIG. 1 , a display device according to the embodiment includes a pixel part 11 , a scan line driver circuit 21 and a signal line driver circuit 31 on the surface of a transparent glass substrate 10 .
- a configuration of the display device giving an example of active-matrix liquid crystal display devices.
- a plurality of scan lines G 1 , G 2 , . . . , Gn (hereinafter generically termed as “G”) and a plurality of signal lines S 1 , S 2 , . . . , Sm (hereinafter generically termed as “S”) are arranged in a way that the plurality of scan lines and the plurality of signal lines intersect each other.
- a switching element 12 , a pixel electrode 13 , a liquid crystal capacitor 14 and an auxiliary capacitor 15 are arranged at each intersection.
- a polysilicon thin film transistor is used for the switching element 12 .
- the scan line driver circuit 21 includes a vertical shift-resistor 22 and a buffer 23 .
- the vertical shift resistor 22 is formed of a plurality of shift resistors electrically connected to one another longitudinally.
- the buffer is connected to the output stage of the vertical shift resistor 22 .
- the signal line driver circuit 31 includes a horizontal shift resistor 32 , a buffer 33 , a video signal line 34 and a plurality of analog switches 35 .
- the horizontal shift resistor 32 is formed of a plurality of shift resistors electrically connected to one another longitudinally.
- the buffer 33 is connected to the output stage of the horizontal shift resistor 32 .
- the video signal line 34 is one through which video signals are supplied.
- the plurality of analog switches 35 are ones through which the video signal line 34 is connected with each of the signal lines S.
- Both start pulse signals (STP) and clock signals (CK) are inputted into the vertical shift resister 22 and the horizontal shift resistor 33 .
- the start pulse signals to be inputted into the vertical shift resistor 22 are termed as STV
- the start pulse signals to be inputted into the horizontal shift resistor 32 are termed as STH.
- the clock signals to be inputted into the vertical shift resistor 22 are termed as CKV
- the clock signals to be inputted into the horizontal shift resistor 32 are termed as CKH.
- Each of the vertical shift resistor 22 and the horizontal shift resistor 32 shifts the phase of start pulse signals STP to be inputted thereinto, and outputs the signals with the shifted phase.
- the scan line driver circuit 21 outputs vertical scan pulses from each of the shift resistors therein to the respective scan lines G corresponding to the shift resistor while shifting phases of the vertical scan pulses one by one.
- the signal line driver circuit 31 outputs horizontal scan pulses from each of the shift resistors therein to its corresponding one of the analog switches 35 provided to the respective signal lines S while shifting phases of the horizontal scan pulses one by one, thereby turning the analog switches 35 on. Accordingly, the signal line driver circuit 31 causes video signals, which have been supplied to the signal line driver circuit 31 through the video signal line 34 from the outside, to be outputted in each of the signal lines S respectively through the analog switches 35 .
- the width W and the length L of the channel of each of the transistors in the buffers 23 and 24 are made larger than the width and the length of the channel of each of the transistors in the vertical shift resistor 22 and the horizontal shift resistor 32 in order that pulses capable of fully driving the scan lines G and the analog switches 35 may be outputted.
- the driver circuits are respectively configured of only either a set of pMOS transistors or a set of nMOS transistors in order to cut back the manufacturing process and to enable costs to be reduced.
- FIG. 2 shows a circuit diagram of the driver circuit.
- a configuration of the scan line driver circuit 21 is similar to that of the signal line driver circuit 31 . It is a matter of course that any one of the two driver circuits may be configured in a manner as shown in FIG. 2 .
- Each of the driver circuits is configured to include the plurality of shift resistors SR 1 , SR 2 , . . . , SRn (hereinafter genetically termed as SR), a clock line 36 , a plurality of buffers BUF 1 , BUF 2 , . . . , BUFn, and an output line 37 .
- the plurality of shift resistors SR are electrically connected to one another longitudinally.
- the clock line 36 is one through which any two of three clock signals CK 1 , CK 2 and CK 3 with their phases shifted one by one are inputted to each of the shift resistors SR.
- the plurality of buffers are connected respectively to the output stages of the shift resistors SR 1 , SR 2 , . . . , SRn.
- the output line 37 is one through which enable signals OE (output enable) are supplied to each of the buffers BUF.
- the clock signals CK 1 to CK 3 constitutes vertical clock signals CKV in the vertical shift resistor 22 , and constitutes horizontal clock signals CKH in the horizontal shift resistor 32 .
- the shift resistors SR 1 , SR 2 , . . . , and SRn correspond respectively to a first stage, a second stage, . . . , and an nth stage.
- Each of the shift resistors SR includes a first clock terminal 41 and a second clock terminal 42 .
- a first clock signal CK 1 is inputted into the first clock terminal 41
- a second clock signal CK 2 is inputted into the second clock terminal 42
- a second clock signal CK 2 is inputted into the first clock terminal 41
- a third clock signal CK 3 is inputted into the second clock terminal 42 .
- Each of the shift resistors SR shifts the phase of input signals IN to be inputted thereinto in a way that the phase is synchronized to two of the three clock signals, and outputs the signals respectively with the phases thus shifted as output signals OUT.
- Start pulse signals STP are inputted, as the input signals IN, into a shift resistor SR 1 at a first stage.
- Output signals OUT from a shift resistor SR at any stage coming at or after the second stage are inputted into a shift resistor at the ensuing stage.
- Each of the buffers BUF amplifies the amplitude of output signals OUT, and outputs the signals with the amplified amplitude as output signals BOUT.
- the scan line driver circuit 21 outputs output signals BOUT from each of the buffers BUF, as vertical scan pulses, to the scan lines G corresponding to the buffer.
- the signal line driver circuit 31 outputs output signals BOUT from each of the buffers BUF, as horizontal scan pulses, to the control electrode of the analog switch 35 corresponding to the buffer.
- FIG. 3 shows a circuit diagram of the configurations respectively of one of the shift resistors SR and one of the buffers BUF.
- Input signals IN are inputted into the input terminal 43 .
- any two of the three clock signals CK 1 , CK 2 and CK 3 with their phases shifted one by one are inputted to clock terminals.
- a first clock signal CK 1 is inputted into the first clock terminal 41
- a second clock signal CK 2 is inputted into the second clock terminal 42 .
- all of the transistors included in the shift resistors SR and the buffers BUF are pMOS transistors.
- Each of the shift resistors SR is configured to include an output circuit, an input circuit and a reset circuit.
- the output circuit is configured of a first transistor T 1 and a second transistor T 2 .
- the drain and the source of the first transistor T 1 are electrically connected respectively to the first clock terminal 41 and the output terminal 44 .
- the source and the drain of the second transistor T 2 are electrically connected respectively to a power supply electrode 46 and the output terminal 44 .
- a first clock signal CK 1 is inputted into the first clock terminal 41 , and high-level power supply voltage VDD is supplied to the power supply electrode 46 .
- This output circuit outputs the first clock signal CK 1 to the output terminal 44 in a case where the first transistor T 1 is on and the second transistor T 2 is off.
- This output circuit outputs the power supply voltage VDD to the output terminal 44 in a case where the first transistor T 1 is off and the second transistor T 2 is on.
- a conductive path of the first transistor T 1 to the control electrode is denominated by a node n 1
- a conductive path of the second transistor T 2 to the control electrode is denominated by a node n 2 .
- the input circuit is configured of a third transistor T 3 and a fourth transistor T 4 .
- the drain and the gate of the third transistor T 3 are electrically connected to the input terminal 43
- the source of the third transistor T 3 is electrically connected to the control electrode of the first transistor T 1 .
- the source, the drain and the gate of the fourth transistor T 4 are electrically connected respectively to the power supply electrode 46 , the control electrode of the second transistor T 2 and the input terminal 43 .
- the input circuit receives input signals IN through the input terminal 43 .
- the reset circuit is configured of a fifth transistor T 5 and a sixth transistor T 6 .
- the drain and the gate of the fifth transistor T 5 are electrically connected to the second clock terminal 42 , and the source of the fifth transistor T 5 is electrically connected to the control electrode of the second transistor T 2 .
- the drain of the sixth transistor T 6 is electrically connected to the control electrode of the first transistor T 1
- the gate of the sixth transistor T 6 is electrically connected to the drain of the fourth transistor T 4 and the control electrode of the second transistor T 2
- the source of the sixth transistor T 6 is electrically connected to the power supply electrode 46 .
- a second clock signal CK 2 is inputted into the second clock terminal 42 .
- This reset circuit turns on one of the first and the second transistors T 1 and T 2 , and turns off the other of the first and second transistors T 1 and T 2 .
- Each of the buffers BUF includes an inverter, an output circuit, an eleventh transistor T 11 .
- the inverter is configured of a seventh transistor T 7 and an eighth transistor T 8 .
- the output circuit is configured of a ninth transistor T 9 and a tenth transistor T 10 .
- the eleventh transistor T 11 is connected to the middle between the output terminal 44 of the shift resistor corresponding to the buffer and the control electrode of the ninth transistor T 9 .
- the gate and the source of the seventh transistor T 7 are connected respectively to the output terminal 44 of the shift resistor and the power supply electrode 46 to which the power supply voltage VDD is supplied.
- the gate and the drain of the eighth transistor T 8 is connected to a power supply electrode 47 to which low-level power supply voltage VSS 2 is supplied, and the source of the eighth transistor T 8 is connected to the drain of the seventh transistor T 7 .
- the ninth transistor T 9 includes a conductive path between an enable terminal 48 and an out terminal 49 : the enable terminal 48 is one to which enable signals OE are inputted, and the output terminal 49 is one from which amplified signals are outputted.
- the tenth transistor T 10 includes a conductive path between the output terminal 49 and the power supply voltage VDD. More specifically, the drain and the source of the ninth transistor T 9 are connected respectively to the enable terminal 48 and the output terminal 49 , and the gate of the ninth transistor T 9 is connected to the output terminal 44 of the shift resistor corresponding to the buffer through the eleventh transistor T 11 . The gate of this eleventh transistor T 11 is supplied with the low-level power supply voltage VSS 2 .
- the drain and the source of the tenth transistor T 10 are connected respectively to the output terminal 49 and the power supply electrode 46 to which the power supply voltage VDD is supplied, and the gate of the tenth transistor T 10 is connected to a connecting point between the seventh transistor T 7 and the eighth transistor T 8 .
- a conductive path of the tenth transistor T 10 to the control electrode is denominated by a node n 3
- a conductive path of the ninth transistor T 9 to the control electrode is denominated by a node n 4 .
- This driver circuit is characterized in that the electric potential difference between the high-level power supply voltage and the low-level power supply voltage respectively for the shift resistors SR and the buffers BUF are set smaller than the electric potential difference between the high-level voltage and the low-level voltage for enable signals OE.
- the high-level power supply voltage VDD is caused to be maintained at a constant level, and concurrently the low-level power supply voltage VSS 2 used in the shift registers SR and the buffers BUF is caused to have an electric potential higher than the low-level power supply voltage VSS of enable signals OE.
- FIG. 4 is a timing chart showing a mutual relationship among input signals IN into the shift register SRI, clock signals CK 1 to CK 3 , enable signals OE, signals at the nodes n 1 to n 4 , output signals OUT from the shift resistor SR 1 and output signals BOUT from the buffer BUF corresponding to the shift resistor SR 1 .
- the output signals OUT from the shift resistor SR 1 are obtained by shifting the phase of the input signals IN.
- the other shift resistors SR operate according to the timing chart shown in FIG. 4 in common with the shift resistor SR 1 .
- the low-level power supply voltage and the low-level voltage for the various types of signals such as the input signals IN, the clock signals CK 1 to CK 3 are set at VSS 2 , whose potential is higher than that of the low-level voltage VSS for the enable signals OE.
- VSS 2 whose potential is higher than that of the low-level voltage VSS for the enable signals OE.
- the electric potential of the input signals IN changes from the high-level voltage VDD to the low-level voltage VSS 2 , thus turning on the third transistor T 3 and the fourth transistor T 4 .
- the second clock signal CK 2 is at the high-level voltage, and accordingly the fifth transistor T 5 is in an off-state.
- the high-level power supply voltage is supplied to the node n 2 through the fourth transistor T 4 , thus raising the electric potential of the node n 2 to the high level. This turns off the second transistor T 2 and the sixth transistor T 6 .
- the third transistor T 3 is on, and the sixth transistor T 6 is off. Accordingly, the input signals IN at the low-level voltage are supplied to the node n 1 through the third transistor T 3 , thus lowering the electric potential of the node n 1 to VSS 2 . This turns on the first transistor T 1 . As a consequence, the first clock signal CK 1 at the high-level voltage is supplied to the output terminal 44 of the shift resistor through the first transistor T 1 . This maintains the output signals OUT from the shift resistor at the high-level voltage.
- the electric potential of the input signals IN changes from the low-level voltage VSS 2 to the high-level voltage VDD, and concurrently the electric potential of the first clock signal CK 1 is reversed from the high-level voltage VDD to the low-level voltage VSS 2 .
- the rise of the electric potential of the input signals IN to the high level turns off the third transistor T 3 and the sixth transistor T 6 , thus turning the node n 1 to a floating state which does not apply electric voltage to the node n 1 .
- the node n 1 is influenced by the reversal of the electric potential of the first clock signal CK 1 to the low level through the transistor T 1 , thus lowering the electric potential of the node n 1 to a low electric potential (an LL level), which is lower than the low-level voltage VSS 2 .
- the second clock signal CK 2 is at the high-level voltage.
- the fifth transistor T 5 is in an off-state, and the fourth transistor T 4 is also in an off-state.
- the node n 2 is supplied with no voltage, and is in a floating state.
- the parasitic capacity maintains the node n 2 at the high-level voltage.
- the node n 1 is at the LL level while being in the floating state, and the node n 2 is at the high-level voltage VDD while being in the floating state.
- the widths of the channels respectively of the first transistor T 1 and the second transistor T 2 are beforehand set larger than the width of the channels respectively of the other transistors with the aforementioned case taken into consideration, this causes the parasitic capacities of the first transistor and the second transistor to be larger. Accordingly, the nodes n 1 and n 2 can maintain the LL-level electric potential and the high-level potential respectively.
- the electric potential of the first clock signal CK 1 rises to the high-level voltage VDD
- the electric potential of the second clock signal CK 2 decreases to the low-level voltage VSS 2
- the decrease of the electric potential of the second clock signal CK 2 to the low-level voltage turns on the fifth transistor T 5 .
- the fourth transistor T 4 is in an off-state.
- the electric potential of the node n 2 changes to the low-level voltage VSS 2 through the fifth transistor T 5 .
- the second transistor T 2 and the sixth transistor T 6 are turned on. Turning on the sixth transistor T 6 raises the node n 1 to the high-level voltage, and turns off the first transistor T 1 .
- the electric potential of the input signals IN is fixed at the high level.
- the nodes n 1 and n 2 maintain the high-level voltage VDD and the low-level voltage VSS 2 respectively, and the output signals OUT maintain the high-level voltage VDD.
- the width W of the channel of the second transistor T 2 is beforehand set fully larger than the width of the channel of the fifth transistor T 5 , this can reduce influence of the coupling of the gate and the drain of the fifth transistor T 5 , thereby enabling the electric potential of the node n 2 to be maintained at the low level securely.
- the high-level voltage and the low-level voltage of the enable signals OE are respectively VDD and VSS.
- This voltage VSS is a voltage lower than the aforementioned low-level voltage VSS 2 .
- the electric potential of the enable signals OE decreases to the low-level voltage VSS, thus causing the bootstrap to operate. Accordingly, the electric potential of the node N 4 in a floating state decreases to a level which is lower than VSS 2 by a voltage equivalent to (VDD-VSS), thus maintaining the ninth transistor T 9 in an on-state. Thereby, the electric potential of the output signals BOUT decreases to the low-level voltage VSS in conjunction with change in voltage of the enable signals OE.
- the electric potential of the enable signals OE rises to the high-level voltage VDD, thus returning the electric potential of the node n 4 to the normal low-level voltage VSS 2 .
- the ninth transistor T 9 is maintained in an on-state, and the electric potential of the output signals BOUT returns to the high-level voltage in conjunction with change in voltage of the enable signals OE.
- the electric potential of the output signals OUT from the shift resistor rises to the high-level voltage VDD.
- the electric potentials respectively of the nodes n 3 and n 4 are reversed, the electric potential of the node n 3 decreases to the low-level voltage VSS 2 , and the electric potential of the node n 4 rises to the high-level voltage VDD.
- the ninth and the tenth transistors T 9 and T 10 are turned off and on respectively. Accordingly, through the tenth transistor T 10 , the buffer is supplied with the power supply voltage VDD.
- the electric potential of the output signals BOUT is maintained at the high-level voltage, no matter what electric potential the enable signals OE may be at.
- the output signals OUT and the output signals BOUT are shown in an overlapping manner in FIG. 5 .
- the output signals OUT from the shift resistor are signals at a voltage level in a range of VSS 2 to VDD
- the output signals BOUT are signals at a voltage level in a range of VSS to VDD, whose electric potential difference is larger than that between VSS 2 and VDD.
- all the parts of the shift resistors and the parts other than the output circuit in each of the buffers are designed to operate at 18V, and the output circuit of each of the buffers is designed to operate at 22.5V.
- the driver circuits in this display device can write the video signals into the pixels stably, since the buffers BUF can output the output signals BOUT with a larger electric potential difference between the high-level voltage and the low-level voltage.
- the circuits other than the output circuits of the buffers BUF are designed to operate by use of the high-level voltage and the low-level voltage, between which the electric potential difference is smaller. This makes it possible to reduce the voltage stress on each of the transistors, accordingly enabling the driver circuits to operate with higher reliability.
- the driver circuits are caused to operate at a lower voltage, thus enabling the power consumption to be reduced to a lower level.
- FIG. 6 is a circuit diagram showing configurations respectively of a shift resistor and a buffer on the driver circuit as the comparative example.
- the low-level voltage of the various types of signals as well as the low-level power supply voltage in the shift resistors and the buffers in addition to the low-level voltage of the enable signals OE are set at the single VSS.
- the other basic configurations respectively of the shift resistor and the buffer are the same as those of the circuits show in FIG. 3 .
- FIG. 7 is a timing chart showing operations of the driver circuit in the comparative example.
- the driver circuit in the comparative example basically operates as shown by the timing chart of FIG. 4 .
- all of the various types of signals are signals at VDD and VSS, between which the electric potential difference is larger.
- an electric potential difference applied to the output signals BOUT is larger, thus enabling video signals to be written onto each of the pixels stably.
- the insides of a shift resistor and a buffer are supplied with the high-level voltage and the low-level voltage, between which the electric potential difference is larger. This causes the voltage stress on each of the transistors to be higher, thus reducing reliability in operations of the driver circuit.
- the driver circuit is operated at a higher voltage, thus consuming much more electric power.
- the output signals OUT and the output signals BOUT are shown in overlapping manner in FIG. 8 .
- the voltage stress on each of the transistors is lower, thus making higher the reliability in operations of the driver circuit.
- the driving of the driver circuit at the low-level voltage prevents an increase in the power consumption.
- the electric potential difference between the high-level power supply voltage and the low-level power supply voltage in the shift resistors and the buffers is set smaller than the electric potential difference between the high-level voltage and the low-level voltage of enable signals OE, which the buffers use in their respective output circuits.
- the configuration of the shift resistors is not limited to the configuration shown in FIG. 3 . No matter what configuration may be used for the shift resistors, if the configuration enables phases of input signals to be shifted.
- the configuration of the buffers is not limited to the configuration shown in FIG. 3 . No matter what configuration may be used for the buffers, if the configuration makes it possible to amplify amplitudes of output signals OUT from the shift resistors by use of enable signals OE. In this case, the electric potential difference between the high-level power supply voltage and the low-level power supply voltage of the shift resistors and buffers is set smaller than the electric potential difference between the high-level voltage and the low-level voltage in the enable signals OE.
- the output circuits respectively of the buffers are configured to include the ninth transistor T 9 and the tenth transistor T 10 , and that the output circuits are configured to output the output signals BOUT by use of the bootstrap by the ninth transistor T 9 .
- the driver circuit has been described, in which pMOS transistors are used for the shift resistors and the buffers, and which start pulse signals STP with pulses in the downward direction are transmitted.
- the driver circuit is not limited to this.
- the shift resistors and the buffers may be configured of nMOS transistors, in association with which the driver circuits are configured to transmit start pulse signals with pulses in the upward direction. This case can bring about the same effect as the aforementioned case brings about.
Abstract
Description
- This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2004-242535 filed on Aug. 23, 2004; the entire contents of which are incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to a driver circuit for driving scan lines or signal lines in a display device.
- 2. Description of the Related Art
- Plane display devices, typified by liquid crystal display devices, feature thinness, light weight, and low power consumption, and accordingly are in use for displays of various types of electric appliances. Out of the plane display devices, active-matrix liquid crystal display devices with a transistor arranged in each pixel have been increasingly in use for note personal computers and portable information terminal devices. Recently, a technique has been established, which forms polysilicon thin film transistors (p-Si TFTs) with high electron mobility by means of a process to be performed at a temperature relatively lower than that which is applied in order to form amorphous silicon thin film transistors, which have been in use for conventional liquid crystal display devices. This establishment has made it possible to fabricate transistors in a smaller size, which are in use for liquid crystal display devices. This has made it possible to integrally form a pixel part and driver circuits on a transparent glass substrate through a single manufacturing process: the pixel part is configured by arranging a transistor at an intersection between each of a plurality of scan lines and its corresponding one of a plurality of signal lines, and the driver circuits respectively drive a group of scan lines and a group of signal lines.
- In addition, as disclosed in Japanese Patent Laid-open No. 2003-344873, development has been in progress for a bootstrap circuit for the purpose of setting electric potential for output signals from a driver circuit at a sufficient level.
- An electric potential difference between the high-level voltage and the low-level voltage of output signals from a driver circuit is used in order for the output signals from the driver circuit to control the writing of video signals into each pixel. For this reason, from the viewpoint of enabling the writing to be stable, it is desirable that the electric potential difference be as large as possible. However, a larger electric potential difference between the high-level voltage and the low-level voltage means a higher voltage stress being on the transistors. This is likely to reduce reliability in operation of each of the transistors that constitute the driver circuits. Furthermore, the larger electric potential difference leads driving the driver circuits at a higher voltage. This brings about a problem of requiring larger power consumption.
- An object of the present invention is to prevent voltage stress on each transistor from increasing, to concurrently make it possible to set larger an electric potential difference between the high-level voltage and the low-level voltage of output signals.
- A driver circuit for a display device according to the present invention is characterized by including shift resistors and buffers. Each of the shift resistors shifts the phase of input signals to be inputted thereinto, and outputs the signals with the shifted phase. Each of the buffers amplifies the amplitude of the output signals from the shift resistor corresponding to the buffer by use of enable signals, and outputs the signals with the amplified amplitude to a scan line or a signal line. The driver circuit is characterized in that an electric potential difference between the high-level voltage and the low-level voltage of the enable signals is used as an electric potential difference with which to drive the scan lines or the signal lines, and in that an electric potential difference between the high-level power supply voltage and the low-level power supply voltage respectively in the shift resistors and the buffers is set smaller than the electric potential difference between the high-level voltage and the low-level voltage of the enable signals.
- In the present invention, an electric potential difference between the high-level power supply voltage and the low-level power supply voltage respectively for the shift resistors and the buffers are set smaller than the electric potential difference between the high-level voltage and the low-level voltage of the enable signals. Thereby, the electric potential difference between the high-level voltage and the low-level voltage is made larger with regard to output signals from each of the buffers, which are amplified by use of the enable signals. On the other hand, the shift resistors and the buffers are caused to operate by use of the high-level power supply voltage and the low-level power supply voltage, between which an electric potential difference is small. These help reduce voltage stress on each transistor. This makes it possible to set larger an electric potential difference between the high-level voltage and the low-level voltage of output signals from each of the buffers, thus enabling video signals to be written into the pixel corresponding to the buffer stably. Moreover, this makes it possible to reduce voltage stress on each transistor inside the shift resistors and the buffers, thus achieving highly reliable operations. Additionally, this enables the driver circuit to operate at a lower voltage, thus enabling power consumption to be reduced.
-
FIG. 1 shows a circuit diagram of a display device according to an embodiment. -
FIG. 2 shows a circuit diagram of a driver circuit in the display device. -
FIG. 3 shows a circuit diagram of a shift resistor and a buffer in the driver circuit. -
FIG. 4 shows a timing chart of the driver circuit operations. -
FIG. 5 shows diagram of output signals from the shift resistor and output signals from the buffer in an overlapping manner. -
FIG. 6 shows a circuit diagram of a shift resistor and a buffer in a driver circuit as a comparative example. -
FIG. 7 shows a timing chart of the driver circuit as the comparative example. -
FIG. 8 shows a diagram of output signals from the shift resistor and output signals from the buffer in the comparative example in an overlapping manner. -
FIG. 9 shows a circuit diagram of other configurations respectively of the shift resistor and the buffer in the driver circuit. - As shown in the circuit diagram of
FIG. 1 , a display device according to the embodiment includes apixel part 11, a scanline driver circuit 21 and a signalline driver circuit 31 on the surface of atransparent glass substrate 10. In this case, descriptions will be provided for a configuration of the display device, giving an example of active-matrix liquid crystal display devices. - In the
pixel part 11, a plurality of scan lines G1, G2, . . . , Gn (hereinafter generically termed as “G”) and a plurality of signal lines S1, S2, . . . , Sm (hereinafter generically termed as “S”) are arranged in a way that the plurality of scan lines and the plurality of signal lines intersect each other. Aswitching element 12, apixel electrode 13, aliquid crystal capacitor 14 and anauxiliary capacitor 15 are arranged at each intersection. As an example, a polysilicon thin film transistor is used for theswitching element 12. - The scan
line driver circuit 21 includes a vertical shift-resistor 22 and abuffer 23. Thevertical shift resistor 22 is formed of a plurality of shift resistors electrically connected to one another longitudinally. The buffer is connected to the output stage of thevertical shift resistor 22. The signalline driver circuit 31 includes ahorizontal shift resistor 32, abuffer 33, avideo signal line 34 and a plurality ofanalog switches 35. Thehorizontal shift resistor 32 is formed of a plurality of shift resistors electrically connected to one another longitudinally. Thebuffer 33 is connected to the output stage of thehorizontal shift resistor 32. Thevideo signal line 34 is one through which video signals are supplied. The plurality ofanalog switches 35 are ones through which thevideo signal line 34 is connected with each of the signal lines S. - Both start pulse signals (STP) and clock signals (CK) are inputted into the
vertical shift resister 22 and thehorizontal shift resistor 33. In this case, the start pulse signals to be inputted into thevertical shift resistor 22 are termed as STV, and the start pulse signals to be inputted into thehorizontal shift resistor 32 are termed as STH. In addition, the clock signals to be inputted into thevertical shift resistor 22 are termed as CKV, and the clock signals to be inputted into thehorizontal shift resistor 32 are termed as CKH. - Each of the
vertical shift resistor 22 and thehorizontal shift resistor 32 shifts the phase of start pulse signals STP to be inputted thereinto, and outputs the signals with the shifted phase. In this respect, the scanline driver circuit 21 outputs vertical scan pulses from each of the shift resistors therein to the respective scan lines G corresponding to the shift resistor while shifting phases of the vertical scan pulses one by one. The signalline driver circuit 31 outputs horizontal scan pulses from each of the shift resistors therein to its corresponding one of theanalog switches 35 provided to the respective signal lines S while shifting phases of the horizontal scan pulses one by one, thereby turning theanalog switches 35 on. Accordingly, the signalline driver circuit 31 causes video signals, which have been supplied to the signalline driver circuit 31 through thevideo signal line 34 from the outside, to be outputted in each of the signal lines S respectively through the analog switches 35. - The width W and the length L of the channel of each of the transistors in the
buffers 23 and 24 are made larger than the width and the length of the channel of each of the transistors in thevertical shift resistor 22 and thehorizontal shift resistor 32 in order that pulses capable of fully driving the scan lines G and the analog switches 35 may be outputted. In addition, it is desirable that the driver circuits are respectively configured of only either a set of pMOS transistors or a set of nMOS transistors in order to cut back the manufacturing process and to enable costs to be reduced. -
FIG. 2 shows a circuit diagram of the driver circuit. Basically, a configuration of the scanline driver circuit 21 is similar to that of the signalline driver circuit 31. It is a matter of course that any one of the two driver circuits may be configured in a manner as shown inFIG. 2 . Each of the driver circuits is configured to include the plurality of shift resistors SR1, SR2, . . . , SRn (hereinafter genetically termed as SR), aclock line 36, a plurality of buffers BUF1, BUF2, . . . , BUFn, and anoutput line 37. The plurality of shift resistors SR are electrically connected to one another longitudinally. Theclock line 36 is one through which any two of three clock signals CK1, CK2 and CK3 with their phases shifted one by one are inputted to each of the shift resistors SR. The plurality of buffers are connected respectively to the output stages of the shift resistors SR1, SR2, . . . , SRn. Theoutput line 37 is one through which enable signals OE (output enable) are supplied to each of the buffers BUF. The clock signals CK1 to CK3 constitutes vertical clock signals CKV in thevertical shift resistor 22, and constitutes horizontal clock signals CKH in thehorizontal shift resistor 32. - The shift resistors SR1, SR2, . . . , and SRn correspond respectively to a first stage, a second stage, . . . , and an nth stage. Each of the shift resistors SR includes a
first clock terminal 41 and asecond clock terminal 42. In the shift resistor SR1, for example, a first clock signal CK1 is inputted into thefirst clock terminal 41, and a second clock signal CK2 is inputted into thesecond clock terminal 42. In the shift resistor SR2, a second clock signal CK2 is inputted into thefirst clock terminal 41, and a third clock signal CK3 is inputted into thesecond clock terminal 42. - Each of the shift resistors SR shifts the phase of input signals IN to be inputted thereinto in a way that the phase is synchronized to two of the three clock signals, and outputs the signals respectively with the phases thus shifted as output signals OUT. Start pulse signals STP are inputted, as the input signals IN, into a shift resistor SR1 at a first stage. Output signals OUT from a shift resistor SR at any stage coming at or after the second stage are inputted into a shift resistor at the ensuing stage. Each of the buffers BUF amplifies the amplitude of output signals OUT, and outputs the signals with the amplified amplitude as output signals BOUT.
- The scan
line driver circuit 21 outputs output signals BOUT from each of the buffers BUF, as vertical scan pulses, to the scan lines G corresponding to the buffer. The signalline driver circuit 31 outputs output signals BOUT from each of the buffers BUF, as horizontal scan pulses, to the control electrode of theanalog switch 35 corresponding to the buffer. -
FIG. 3 shows a circuit diagram of the configurations respectively of one of the shift resistors SR and one of the buffers BUF. Input signals IN are inputted into theinput terminal 43. In addition, any two of the three clock signals CK1, CK2 and CK3 with their phases shifted one by one are inputted to clock terminals. As an example, it is supposed inFIG. 3 that a first clock signal CK1 is inputted into thefirst clock terminal 41, and that a second clock signal CK2 is inputted into thesecond clock terminal 42. As an example, it is also supposed that all of the transistors included in the shift resistors SR and the buffers BUF are pMOS transistors. - Each of the shift resistors SR is configured to include an output circuit, an input circuit and a reset circuit. The output circuit is configured of a first transistor T1 and a second transistor T2. The drain and the source of the first transistor T1 are electrically connected respectively to the
first clock terminal 41 and theoutput terminal 44. The source and the drain of the second transistor T2 are electrically connected respectively to apower supply electrode 46 and theoutput terminal 44. A first clock signal CK1 is inputted into thefirst clock terminal 41, and high-level power supply voltage VDD is supplied to thepower supply electrode 46. This output circuit outputs the first clock signal CK1 to theoutput terminal 44 in a case where the first transistor T1 is on and the second transistor T2 is off. This output circuit outputs the power supply voltage VDD to theoutput terminal 44 in a case where the first transistor T1 is off and the second transistor T2 is on. Here, a conductive path of the first transistor T1 to the control electrode is denominated by a node n1, and a conductive path of the second transistor T2 to the control electrode is denominated by a node n2. - The input circuit is configured of a third transistor T3 and a fourth transistor T4. The drain and the gate of the third transistor T3 are electrically connected to the
input terminal 43, and the source of the third transistor T3 is electrically connected to the control electrode of the first transistor T1. In addition, the source, the drain and the gate of the fourth transistor T4 are electrically connected respectively to thepower supply electrode 46, the control electrode of the second transistor T2 and theinput terminal 43. The input circuit receives input signals IN through theinput terminal 43. - The reset circuit is configured of a fifth transistor T5 and a sixth transistor T6. The drain and the gate of the fifth transistor T5 are electrically connected to the
second clock terminal 42, and the source of the fifth transistor T5 is electrically connected to the control electrode of the second transistor T2. In addition, the drain of the sixth transistor T6 is electrically connected to the control electrode of the first transistor T1, and the gate of the sixth transistor T6 is electrically connected to the drain of the fourth transistor T4 and the control electrode of the second transistor T2, and the source of the sixth transistor T6 is electrically connected to thepower supply electrode 46. A second clock signal CK2 is inputted into thesecond clock terminal 42. This reset circuit turns on one of the first and the second transistors T1 and T2, and turns off the other of the first and second transistors T1 and T2. - Each of the buffers BUF includes an inverter, an output circuit, an eleventh transistor T11. The inverter is configured of a seventh transistor T7 and an eighth transistor T8. The output circuit is configured of a ninth transistor T9 and a tenth transistor T10. The eleventh transistor T11 is connected to the middle between the
output terminal 44 of the shift resistor corresponding to the buffer and the control electrode of the ninth transistor T9. - More specifically, the gate and the source of the seventh transistor T7 are connected respectively to the
output terminal 44 of the shift resistor and thepower supply electrode 46 to which the power supply voltage VDD is supplied. The gate and the drain of the eighth transistor T8 is connected to apower supply electrode 47 to which low-level power supply voltage VSS2 is supplied, and the source of the eighth transistor T8 is connected to the drain of the seventh transistor T7. - The ninth transistor T9 includes a conductive path between an enable
terminal 48 and an out terminal 49: the enableterminal 48 is one to which enable signals OE are inputted, and theoutput terminal 49 is one from which amplified signals are outputted. The tenth transistor T10 includes a conductive path between theoutput terminal 49 and the power supply voltage VDD. More specifically, the drain and the source of the ninth transistor T9 are connected respectively to the enableterminal 48 and theoutput terminal 49, and the gate of the ninth transistor T9 is connected to theoutput terminal 44 of the shift resistor corresponding to the buffer through the eleventh transistor T11. The gate of this eleventh transistor T11 is supplied with the low-level power supply voltage VSS2. The drain and the source of the tenth transistor T10 are connected respectively to theoutput terminal 49 and thepower supply electrode 46 to which the power supply voltage VDD is supplied, and the gate of the tenth transistor T10 is connected to a connecting point between the seventh transistor T7 and the eighth transistor T8. Here, a conductive path of the tenth transistor T10 to the control electrode is denominated by a node n3, and a conductive path of the ninth transistor T9 to the control electrode is denominated by a node n4. - This driver circuit is characterized in that the electric potential difference between the high-level power supply voltage and the low-level power supply voltage respectively for the shift resistors SR and the buffers BUF are set smaller than the electric potential difference between the high-level voltage and the low-level voltage for enable signals OE.
- More specifically, the high-level power supply voltage VDD is caused to be maintained at a constant level, and concurrently the low-level power supply voltage VSS2 used in the shift registers SR and the buffers BUF is caused to have an electric potential higher than the low-level power supply voltage VSS of enable signals OE. These will be described in detail with reference to
FIGS. 3 and 4 . -
FIG. 4 is a timing chart showing a mutual relationship among input signals IN into the shift register SRI, clock signals CK1 to CK3, enable signals OE, signals at the nodes n1 to n4, output signals OUT from the shift resistor SR1 and output signals BOUT from the buffer BUF corresponding to the shift resistor SR1. The output signals OUT from the shift resistor SR1 are obtained by shifting the phase of the input signals IN. Incidentally, the other shift resistors SR operate according to the timing chart shown inFIG. 4 in common with the shift resistor SR1. - As shown in
FIG. 4 , the low-level power supply voltage and the low-level voltage for the various types of signals such as the input signals IN, the clock signals CK1 to CK3 are set at VSS2, whose potential is higher than that of the low-level voltage VSS for the enable signals OE. This makes smaller an electric potential difference between the high-level voltage and the low-level voltage. As described later, the electric potential difference between the high-level voltage VDD and the low-level voltage VSS2 suffices if the electric potential difference turns on the ninth transistor T9. The electric potential difference does not have to be larger than that. - In a time period between time t1 and time t2, the electric potential of the input signals IN changes from the high-level voltage VDD to the low-level voltage VSS2, thus turning on the third transistor T3 and the fourth transistor T4. The second clock signal CK2 is at the high-level voltage, and accordingly the fifth transistor T5 is in an off-state. The high-level power supply voltage is supplied to the node n2 through the fourth transistor T4, thus raising the electric potential of the node n2 to the high level. This turns off the second transistor T2 and the sixth transistor T6.
- The third transistor T3 is on, and the sixth transistor T6 is off. Accordingly, the input signals IN at the low-level voltage are supplied to the node n1 through the third transistor T3, thus lowering the electric potential of the node n1 to VSS2. This turns on the first transistor T1. As a consequence, the first clock signal CK1 at the high-level voltage is supplied to the
output terminal 44 of the shift resistor through the first transistor T1. This maintains the output signals OUT from the shift resistor at the high-level voltage. - In a time period between time t2 and time t3, the electric potential of the input signals IN changes from the low-level voltage VSS2 to the high-level voltage VDD, and concurrently the electric potential of the first clock signal CK1 is reversed from the high-level voltage VDD to the low-level voltage VSS2. The rise of the electric potential of the input signals IN to the high level turns off the third transistor T3 and the sixth transistor T6, thus turning the node n1 to a floating state which does not apply electric voltage to the node n1. In addition, the node n1 is influenced by the reversal of the electric potential of the first clock signal CK1 to the low level through the transistor T1, thus lowering the electric potential of the node n1 to a low electric potential (an LL level), which is lower than the low-level voltage VSS2.
- This is because the existence of parasitic capacity between the gate and the source of the first transistor T1 or between the gate and the drain of the first transistor T1 changes the electric potential of the
node 1 in conjunction with change in electric potential between the drain and the source of the first transistor T1 in a case where the node n1 is in the floating state. Bootstrap is a term for the phenomenon of fluctuation in electric potential of the node in the floating state under influence of fluctuation in electric potential in a transistor to which the node is connected. In addition, bootstrap node is a term for the node in this case. Here, the decrease of the electric potential of the node n1 to the further lower level turns the first transistor T1 to an on-state securely. This causes theoutput terminal 44 of the shift resistor to be supplied with the first clock signal CK1 at the low-level voltage through the first transistor T1, thus turning the output signals OUT to the low-level voltage VSS2. - Furthermore, the second clock signal CK2 is at the high-level voltage. For this reason, the fifth transistor T5 is in an off-state, and the fourth transistor T4 is also in an off-state. Accordingly, the node n2 is supplied with no voltage, and is in a floating state. As a consequence, the parasitic capacity maintains the node n2 at the high-level voltage. In other words, in this time period, the node n1 is at the LL level while being in the floating state, and the node n2 is at the high-level voltage VDD while being in the floating state.
- If the widths of the channels respectively of the first transistor T1 and the second transistor T2 are beforehand set larger than the width of the channels respectively of the other transistors with the aforementioned case taken into consideration, this causes the parasitic capacities of the first transistor and the second transistor to be larger. Accordingly, the nodes n1 and n2 can maintain the LL-level electric potential and the high-level potential respectively.
- At time t3, the electric potential of the first clock signal CK1 rises to the high-level voltage VDD, the electric potential of the second clock signal CK2 decreases to the low-level voltage VSS2. The decrease of the electric potential of the second clock signal CK2 to the low-level voltage turns on the fifth transistor T5. At this time, the fourth transistor T4 is in an off-state. For this reason, the electric potential of the node n2 changes to the low-level voltage VSS2 through the fifth transistor T5. As a consequence, the second transistor T2 and the sixth transistor T6 are turned on. Turning on the sixth transistor T6 raises the node n1 to the high-level voltage, and turns off the first transistor T1. Turning off the first transistor T1 and turning on the second transistor T2 in this manner causes the
output terminal 44 to be supplied with the high-level power supply voltage VDD through the second transistor T2, thus raising the electric potential of the output signals OUT from the shift transistor to the high level. - After time t3, the electric potential of the input signals IN is fixed at the high level. For this reason, the nodes n1 and n2 maintain the high-level voltage VDD and the low-level voltage VSS2 respectively, and the output signals OUT maintain the high-level voltage VDD. In this respect, if the width W of the channel of the second transistor T2 is beforehand set fully larger than the width of the channel of the fifth transistor T5, this can reduce influence of the coupling of the gate and the drain of the fifth transistor T5, thereby enabling the electric potential of the node n2 to be maintained at the low level securely.
- Next, descriptions will be provided for operations of the buffers BUF. As shown in
FIG. 4 , the high-level voltage and the low-level voltage of the enable signals OE are respectively VDD and VSS. This voltage VSS is a voltage lower than the aforementioned low-level voltage VSS2. - In a time period between time t2 and time ta, when the output signals OUT from the shift resistor at the low-level voltage VSS2 is inputted into the buffer BUF, the electric potential of the node n3 turns to the high-level voltage VDD, since the seventh and the eighth transistors T7 and T8 constitute the inverter circuit. This turns off the tenth transistor T10. Furthermore, the output signals OUT at the low-level voltage, which are supplied from the shift resistor through the eleventh transistor T11, turns the node n4 to the low-level voltage VSS2, thus turning on the ninth transistor T9. The enable signals OE at the high-level voltage are supplied to the
output terminal 49 of the buffer BUF through the ninth transistor T9, accordingly maintaining the output signals BOUT at the high-level voltage VDD. - In a time period between time ta and time tb, the electric potential of the enable signals OE decreases to the low-level voltage VSS, thus causing the bootstrap to operate. Accordingly, the electric potential of the node N4 in a floating state decreases to a level which is lower than VSS2 by a voltage equivalent to (VDD-VSS), thus maintaining the ninth transistor T9 in an on-state. Thereby, the electric potential of the output signals BOUT decreases to the low-level voltage VSS in conjunction with change in voltage of the enable signals OE.
- In a time period between time tb and time t3, the electric potential of the enable signals OE rises to the high-level voltage VDD, thus returning the electric potential of the node n4 to the normal low-level voltage VSS2. Thus, the ninth transistor T9 is maintained in an on-state, and the electric potential of the output signals BOUT returns to the high-level voltage in conjunction with change in voltage of the enable signals OE.
- After time t3, the electric potential of the output signals OUT from the shift resistor rises to the high-level voltage VDD. Thus, the electric potentials respectively of the nodes n3 and n4 are reversed, the electric potential of the node n3 decreases to the low-level voltage VSS2, and the electric potential of the node n4 rises to the high-level voltage VDD. As a consequence, the ninth and the tenth transistors T9 and T10 are turned off and on respectively. Accordingly, through the tenth transistor T10, the buffer is supplied with the power supply voltage VDD. Hence, the electric potential of the output signals BOUT is maintained at the high-level voltage, no matter what electric potential the enable signals OE may be at. For the reference, the output signals OUT and the output signals BOUT are shown in an overlapping manner in
FIG. 5 . - In the case of this driver circuit, as shown in
FIG. 5 , the output signals OUT from the shift resistor are signals at a voltage level in a range of VSS2 to VDD, while the output signals BOUT are signals at a voltage level in a range of VSS to VDD, whose electric potential difference is larger than that between VSS2 and VDD. This causes the buffer circuits to amplify the signals. That is because the electric potential difference between the high-level power supply voltage VDD and the low-level power supply voltage VSS2 for the shift resistors SR and the buffers BUF is set smaller than the electric potential difference between the high-level power supply voltage VDD and the low-level power supply voltage VSS for the enable signals OE. For example, all the parts of the shift resistors and the parts other than the output circuit in each of the buffers are designed to operate at 18V, and the output circuit of each of the buffers is designed to operate at 22.5V. - In other words, the driver circuits in this display device can write the video signals into the pixels stably, since the buffers BUF can output the output signals BOUT with a larger electric potential difference between the high-level voltage and the low-level voltage. As far as the insides respectively of the shift resistors SR and the buffers BUF are concerned, the circuits other than the output circuits of the buffers BUF are designed to operate by use of the high-level voltage and the low-level voltage, between which the electric potential difference is smaller. This makes it possible to reduce the voltage stress on each of the transistors, accordingly enabling the driver circuits to operate with higher reliability. In addition, the driver circuits are caused to operate at a lower voltage, thus enabling the power consumption to be reduced to a lower level.
- Next, descriptions will be provided for a driver circuit as a comparative example.
FIG. 6 is a circuit diagram showing configurations respectively of a shift resistor and a buffer on the driver circuit as the comparative example. In this comparative example, the low-level voltage of the various types of signals as well as the low-level power supply voltage in the shift resistors and the buffers in addition to the low-level voltage of the enable signals OE are set at the single VSS. The other basic configurations respectively of the shift resistor and the buffer are the same as those of the circuits show inFIG. 3 . -
FIG. 7 is a timing chart showing operations of the driver circuit in the comparative example. The driver circuit in the comparative example basically operates as shown by the timing chart ofFIG. 4 . However, all of the various types of signals are signals at VDD and VSS, between which the electric potential difference is larger. For this reason, an electric potential difference applied to the output signals BOUT is larger, thus enabling video signals to be written onto each of the pixels stably. On the other hand, the insides of a shift resistor and a buffer are supplied with the high-level voltage and the low-level voltage, between which the electric potential difference is larger. This causes the voltage stress on each of the transistors to be higher, thus reducing reliability in operations of the driver circuit. In addition, the driver circuit is operated at a higher voltage, thus consuming much more electric power. For the reference, the output signals OUT and the output signals BOUT are shown in overlapping manner inFIG. 8 . - In contrast to this, in the case of the driver circuit according to this embodiment, the voltage stress on each of the transistors is lower, thus making higher the reliability in operations of the driver circuit. In addition, the driving of the driver circuit at the low-level voltage prevents an increase in the power consumption.
- Consequently, according to this embodiment, the electric potential difference between the high-level power supply voltage and the low-level power supply voltage in the shift resistors and the buffers is set smaller than the electric potential difference between the high-level voltage and the low-level voltage of enable signals OE, which the buffers use in their respective output circuits. This makes larger the electric potential difference between the high-level voltage and the low-level voltage of output signals BOUT, which output signals are amplified by use of enable signals OE. Accordingly, video signals can be written into each of the pixels stably. Furthermore, as far as the insides respectively of the shift resistors and the buffers are concerned, all of the circuits, except for the output circuits of the buffers, operate by use of the high-level voltage VDD and the low-level voltage VSS2, between which the electric potential difference is smaller. This makes it possible to reduce the voltage stress on each of the transistors, accordingly enabling the operational reliability to be improved and concurrently power consumption to be reduced.
- The configuration of the shift resistors is not limited to the configuration shown in
FIG. 3 . No matter what configuration may be used for the shift resistors, if the configuration enables phases of input signals to be shifted. - Furthermore, the configuration of the buffers is not limited to the configuration shown in
FIG. 3 . No matter what configuration may be used for the buffers, if the configuration makes it possible to amplify amplitudes of output signals OUT from the shift resistors by use of enable signals OE. In this case, the electric potential difference between the high-level power supply voltage and the low-level power supply voltage of the shift resistors and buffers is set smaller than the electric potential difference between the high-level voltage and the low-level voltage in the enable signals OE. Incidentally, it is desirable that the output circuits respectively of the buffers are configured to include the ninth transistor T9 and the tenth transistor T10, and that the output circuits are configured to output the output signals BOUT by use of the bootstrap by the ninth transistor T9. - Finally, in the case of this embodiment, the driver circuit has been described, in which pMOS transistors are used for the shift resistors and the buffers, and which start pulse signals STP with pulses in the downward direction are transmitted. However, the driver circuit is not limited to this. As shown in
FIG. 9 , for example, the shift resistors and the buffers may be configured of nMOS transistors, in association with which the driver circuits are configured to transmit start pulse signals with pulses in the upward direction. This case can bring about the same effect as the aforementioned case brings about.
Claims (4)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004242535A JP2006058770A (en) | 2004-08-23 | 2004-08-23 | Driving circuit for display apparatus |
JP2004-242535 | 2004-08-23 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20060038766A1 true US20060038766A1 (en) | 2006-02-23 |
US7221197B2 US7221197B2 (en) | 2007-05-22 |
Family
ID=35909161
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/178,466 Active 2025-07-28 US7221197B2 (en) | 2004-08-23 | 2005-07-12 | Driver circuit of display device |
Country Status (4)
Country | Link |
---|---|
US (1) | US7221197B2 (en) |
JP (1) | JP2006058770A (en) |
KR (1) | KR100674543B1 (en) |
TW (1) | TWI278802B (en) |
Cited By (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070086078A1 (en) * | 2005-02-23 | 2007-04-19 | Pixtronix, Incorporated | Circuits for controlling display apparatus |
US20080283175A1 (en) * | 2007-05-18 | 2008-11-20 | Pixtronix, Inc. | Methods for manufacturing fluid-filled mems displays |
US20090195855A1 (en) * | 2006-02-23 | 2009-08-06 | Pixtronix, Inc. | Mechanical light modulators with stressed beams |
US20090244454A1 (en) * | 2008-03-28 | 2009-10-01 | Fujifilm Corporation | Liquid-crystal display device |
US20110122474A1 (en) * | 2005-02-23 | 2011-05-26 | Pixtronix, Inc. | Display apparatus and methods for manufacture thereof |
US20110205259A1 (en) * | 2008-10-28 | 2011-08-25 | Pixtronix, Inc. | System and method for selecting display modes |
US8482496B2 (en) * | 2006-01-06 | 2013-07-09 | Pixtronix, Inc. | Circuits for controlling MEMS display apparatus on a transparent substrate |
US8520285B2 (en) | 2008-08-04 | 2013-08-27 | Pixtronix, Inc. | Methods for manufacturing cold seal fluid-filled display apparatus |
US8519923B2 (en) | 2005-02-23 | 2013-08-27 | Pixtronix, Inc. | Display methods and apparatus |
US8519945B2 (en) | 2006-01-06 | 2013-08-27 | Pixtronix, Inc. | Circuits for controlling display apparatus |
US8599463B2 (en) | 2008-10-27 | 2013-12-03 | Pixtronix, Inc. | MEMS anchors |
US8982015B2 (en) | 2008-04-22 | 2015-03-17 | Sharp Kabushiki Kaisha | Shift register and active matrix device |
US9082353B2 (en) | 2010-01-05 | 2015-07-14 | Pixtronix, Inc. | Circuits for controlling display apparatus |
US9087486B2 (en) | 2005-02-23 | 2015-07-21 | Pixtronix, Inc. | Circuits for controlling display apparatus |
US9135868B2 (en) | 2005-02-23 | 2015-09-15 | Pixtronix, Inc. | Direct-view MEMS display devices and methods for generating images thereon |
US9134552B2 (en) | 2013-03-13 | 2015-09-15 | Pixtronix, Inc. | Display apparatus with narrow gap electrostatic actuators |
US9158106B2 (en) | 2005-02-23 | 2015-10-13 | Pixtronix, Inc. | Display methods and apparatus |
US9229222B2 (en) | 2005-02-23 | 2016-01-05 | Pixtronix, Inc. | Alignment methods in fluid-filled MEMS displays |
US9500853B2 (en) | 2005-02-23 | 2016-11-22 | Snaptrack, Inc. | MEMS-based display apparatus |
US20160351150A1 (en) * | 2014-11-19 | 2016-12-01 | Boe Technology Group Co., Ltd. | Shift register unit, shift register, gate driving circuit and display device |
CN109564745A (en) * | 2016-07-27 | 2019-04-02 | 堺显示器制品株式会社 | Driving circuit and display device |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7443202B2 (en) | 2006-06-02 | 2008-10-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and electronic apparatus having the same |
JP5069950B2 (en) * | 2006-06-02 | 2012-11-07 | 株式会社半導体エネルギー研究所 | Semiconductor device, display device, liquid crystal display device, display module, and electronic apparatus |
JP2008040332A (en) * | 2006-08-09 | 2008-02-21 | Toshiba Matsushita Display Technology Co Ltd | Scanning line driving circuit for display apparatus |
JP4932415B2 (en) | 2006-09-29 | 2012-05-16 | 株式会社半導体エネルギー研究所 | Semiconductor device |
JP2008139520A (en) | 2006-12-01 | 2008-06-19 | Sony Corp | Display device |
JP2008191295A (en) * | 2007-02-02 | 2008-08-21 | Sony Corp | Display device, driving method of display device and electronic equipment |
KR100897171B1 (en) * | 2007-07-27 | 2009-05-14 | 삼성모바일디스플레이주식회사 | Organic Light Emitting Display |
JP2009128524A (en) * | 2007-11-21 | 2009-06-11 | Sony Corp | Drive circuit, display device, and electronic device |
JP2009128523A (en) * | 2007-11-21 | 2009-06-11 | Sony Corp | Drive circuit, display device, and electronic device |
KR100916906B1 (en) * | 2008-04-25 | 2009-09-09 | 삼성모바일디스플레이주식회사 | Buffer and organic light emitting display using the same |
US8169239B2 (en) * | 2009-04-14 | 2012-05-01 | Himax Technologies Limited | Driver circuit of display device |
US8305328B2 (en) * | 2009-07-24 | 2012-11-06 | Himax Technologies Limited | Multimode source driver and display device having the same |
WO2011114569A1 (en) * | 2010-03-15 | 2011-09-22 | シャープ株式会社 | Shift register, scanning signal line drive circuit, and display device |
US8169240B2 (en) * | 2010-03-23 | 2012-05-01 | Himax Technologies Limited | Driver circuit of display device |
US9330782B2 (en) * | 2010-07-13 | 2016-05-03 | Sharp Kabushiki Kaisha | Shift register and display device having the same |
JP5288654B2 (en) * | 2011-11-02 | 2013-09-11 | 株式会社半導体エネルギー研究所 | Semiconductor device, display device, liquid crystal display device, display module, and electronic apparatus |
TWI462475B (en) * | 2011-12-29 | 2014-11-21 | Au Optronics Corp | Bidirectional shift register and driving method thereof |
JP2014085648A (en) * | 2012-10-26 | 2014-05-12 | Japan Display Inc | Display device and drive circuit |
KR102052065B1 (en) * | 2013-08-12 | 2020-01-09 | 삼성디스플레이 주식회사 | Stage circuit and scan driver using the same |
JP2018078573A (en) * | 2017-11-20 | 2018-05-17 | 株式会社半導体エネルギー研究所 | Flip-flop and shift register |
KR20220016350A (en) * | 2020-07-30 | 2022-02-09 | 삼성디스플레이 주식회사 | Scan driver and display device |
JP7087132B2 (en) * | 2021-02-05 | 2022-06-20 | 株式会社半導体エネルギー研究所 | Semiconductor equipment |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5166960A (en) * | 1992-04-20 | 1992-11-24 | Xerox Corporation | Parallel multi-phased a-Si shift register for fast addressing of an a-Si array |
US5206634A (en) * | 1990-10-01 | 1993-04-27 | Sharp Kabushiki Kaisha | Liquid crystal display apparatus |
US5222082A (en) * | 1991-02-28 | 1993-06-22 | Thomson Consumer Electronics, S.A. | Shift register useful as a select line scanner for liquid crystal display |
US5414443A (en) * | 1989-04-04 | 1995-05-09 | Sharp Kabushiki Kaisha | Drive device for driving a matrix-type LCD apparatus |
US20030174106A1 (en) * | 2002-03-14 | 2003-09-18 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting apparatus and method of driving same |
US6928135B2 (en) * | 2001-04-13 | 2005-08-09 | Kabushiki Kaisha Toshiba | Shift register for pulse-cut clock signal |
US7098882B2 (en) * | 2002-11-29 | 2006-08-29 | Toshiba Matsushita Display Technology Co., Ltd. | Bidirectional shift register shifting pulse in both forward and backward directions |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1065516A (en) * | 1996-08-22 | 1998-03-06 | Hitachi Ltd | Driver ic and electronic device using the same |
JPH11242204A (en) * | 1998-02-25 | 1999-09-07 | Sony Corp | Liquid crystal display device and driving circuit therefor |
TW582005B (en) * | 2001-05-29 | 2004-04-01 | Semiconductor Energy Lab | Pulse output circuit, shift register, and display device |
KR100896404B1 (en) * | 2001-12-12 | 2009-05-08 | 엘지디스플레이 주식회사 | Shift register with level shifter |
US7050036B2 (en) * | 2001-12-12 | 2006-05-23 | Lg.Philips Lcd Co., Ltd. | Shift register with a built in level shifter |
JP2003288061A (en) * | 2002-01-22 | 2003-10-10 | Seiko Epson Corp | Method for generating control signal, control-signal generation circuit, data-line driving circuit, element substrate, optoelectronic device, and electronic apparatus |
JP4130332B2 (en) | 2002-05-24 | 2008-08-06 | 東芝松下ディスプレイテクノロジー株式会社 | Flat panel display using bootstrap circuit |
KR100487439B1 (en) * | 2002-12-31 | 2005-05-03 | 엘지.필립스 엘시디 주식회사 | Circuit and method for bi-directional driving plat display device |
KR100917009B1 (en) * | 2003-02-10 | 2009-09-10 | 삼성전자주식회사 | Method for driving transistor and shift register, and shift register for performing the same |
-
2004
- 2004-08-23 JP JP2004242535A patent/JP2006058770A/en active Pending
-
2005
- 2005-07-12 US US11/178,466 patent/US7221197B2/en active Active
- 2005-07-12 TW TW094123635A patent/TWI278802B/en active
- 2005-08-22 KR KR1020050076642A patent/KR100674543B1/en active IP Right Grant
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5414443A (en) * | 1989-04-04 | 1995-05-09 | Sharp Kabushiki Kaisha | Drive device for driving a matrix-type LCD apparatus |
US5206634A (en) * | 1990-10-01 | 1993-04-27 | Sharp Kabushiki Kaisha | Liquid crystal display apparatus |
US5222082A (en) * | 1991-02-28 | 1993-06-22 | Thomson Consumer Electronics, S.A. | Shift register useful as a select line scanner for liquid crystal display |
US5166960A (en) * | 1992-04-20 | 1992-11-24 | Xerox Corporation | Parallel multi-phased a-Si shift register for fast addressing of an a-Si array |
US6928135B2 (en) * | 2001-04-13 | 2005-08-09 | Kabushiki Kaisha Toshiba | Shift register for pulse-cut clock signal |
US20030174106A1 (en) * | 2002-03-14 | 2003-09-18 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting apparatus and method of driving same |
US7098882B2 (en) * | 2002-11-29 | 2006-08-29 | Toshiba Matsushita Display Technology Co., Ltd. | Bidirectional shift register shifting pulse in both forward and backward directions |
Cited By (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9261694B2 (en) | 2005-02-23 | 2016-02-16 | Pixtronix, Inc. | Display apparatus and methods for manufacture thereof |
US9087486B2 (en) | 2005-02-23 | 2015-07-21 | Pixtronix, Inc. | Circuits for controlling display apparatus |
US9135868B2 (en) | 2005-02-23 | 2015-09-15 | Pixtronix, Inc. | Direct-view MEMS display devices and methods for generating images thereon |
US9229222B2 (en) | 2005-02-23 | 2016-01-05 | Pixtronix, Inc. | Alignment methods in fluid-filled MEMS displays |
US20110122474A1 (en) * | 2005-02-23 | 2011-05-26 | Pixtronix, Inc. | Display apparatus and methods for manufacture thereof |
US9500853B2 (en) | 2005-02-23 | 2016-11-22 | Snaptrack, Inc. | MEMS-based display apparatus |
US8310442B2 (en) | 2005-02-23 | 2012-11-13 | Pixtronix, Inc. | Circuits for controlling display apparatus |
US9177523B2 (en) | 2005-02-23 | 2015-11-03 | Pixtronix, Inc. | Circuits for controlling display apparatus |
US9336732B2 (en) | 2005-02-23 | 2016-05-10 | Pixtronix, Inc. | Circuits for controlling display apparatus |
US8519923B2 (en) | 2005-02-23 | 2013-08-27 | Pixtronix, Inc. | Display methods and apparatus |
US9158106B2 (en) | 2005-02-23 | 2015-10-13 | Pixtronix, Inc. | Display methods and apparatus |
US9274333B2 (en) | 2005-02-23 | 2016-03-01 | Pixtronix, Inc. | Alignment methods in fluid-filled MEMS displays |
US20070086078A1 (en) * | 2005-02-23 | 2007-04-19 | Pixtronix, Incorporated | Circuits for controlling display apparatus |
US8482496B2 (en) * | 2006-01-06 | 2013-07-09 | Pixtronix, Inc. | Circuits for controlling MEMS display apparatus on a transparent substrate |
US8519945B2 (en) | 2006-01-06 | 2013-08-27 | Pixtronix, Inc. | Circuits for controlling display apparatus |
US20090195855A1 (en) * | 2006-02-23 | 2009-08-06 | Pixtronix, Inc. | Mechanical light modulators with stressed beams |
US9128277B2 (en) | 2006-02-23 | 2015-09-08 | Pixtronix, Inc. | Mechanical light modulators with stressed beams |
US8526096B2 (en) | 2006-02-23 | 2013-09-03 | Pixtronix, Inc. | Mechanical light modulators with stressed beams |
US20080283175A1 (en) * | 2007-05-18 | 2008-11-20 | Pixtronix, Inc. | Methods for manufacturing fluid-filled mems displays |
US9176318B2 (en) | 2007-05-18 | 2015-11-03 | Pixtronix, Inc. | Methods for manufacturing fluid-filled MEMS displays |
US20090244454A1 (en) * | 2008-03-28 | 2009-10-01 | Fujifilm Corporation | Liquid-crystal display device |
US8982015B2 (en) | 2008-04-22 | 2015-03-17 | Sharp Kabushiki Kaisha | Shift register and active matrix device |
US8520285B2 (en) | 2008-08-04 | 2013-08-27 | Pixtronix, Inc. | Methods for manufacturing cold seal fluid-filled display apparatus |
US8891152B2 (en) | 2008-08-04 | 2014-11-18 | Pixtronix, Inc. | Methods for manufacturing cold seal fluid-filled display apparatus |
US9182587B2 (en) | 2008-10-27 | 2015-11-10 | Pixtronix, Inc. | Manufacturing structure and process for compliant mechanisms |
US9116344B2 (en) | 2008-10-27 | 2015-08-25 | Pixtronix, Inc. | MEMS anchors |
US8599463B2 (en) | 2008-10-27 | 2013-12-03 | Pixtronix, Inc. | MEMS anchors |
US20110205259A1 (en) * | 2008-10-28 | 2011-08-25 | Pixtronix, Inc. | System and method for selecting display modes |
US9082353B2 (en) | 2010-01-05 | 2015-07-14 | Pixtronix, Inc. | Circuits for controlling display apparatus |
US9134552B2 (en) | 2013-03-13 | 2015-09-15 | Pixtronix, Inc. | Display apparatus with narrow gap electrostatic actuators |
US20160351150A1 (en) * | 2014-11-19 | 2016-12-01 | Boe Technology Group Co., Ltd. | Shift register unit, shift register, gate driving circuit and display device |
CN109564745A (en) * | 2016-07-27 | 2019-04-02 | 堺显示器制品株式会社 | Driving circuit and display device |
Also Published As
Publication number | Publication date |
---|---|
KR20060053199A (en) | 2006-05-19 |
TW200615879A (en) | 2006-05-16 |
US7221197B2 (en) | 2007-05-22 |
JP2006058770A (en) | 2006-03-02 |
TWI278802B (en) | 2007-04-11 |
KR100674543B1 (en) | 2007-01-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7221197B2 (en) | Driver circuit of display device | |
US11361728B2 (en) | Gate driving circuit and display apparatus having the same | |
KR100426910B1 (en) | Shift register, driving circuit with the same, electrode substrate and display device | |
US7319452B2 (en) | Shift register and display device having the same | |
US7098882B2 (en) | Bidirectional shift register shifting pulse in both forward and backward directions | |
JP4359038B2 (en) | Shift register with built-in level shifter | |
US9076370B2 (en) | Scanning signal line drive circuit, display device having the same, and drive method for scanning signal line | |
WO2019041853A1 (en) | Shift register unit, driving apparatus, display apparatus, and driving method | |
WO2017045346A1 (en) | Shift register unit and driving method therefor, gate drive apparatus and display apparatus | |
US7986761B2 (en) | Shift register and liquid crystal display device using same | |
US20100245328A1 (en) | Storage capacitor line drive circuit and display device | |
KR101022293B1 (en) | Shift register and display apparatus having the same | |
JP4413795B2 (en) | Shift register and flat display device using the same | |
JP4130332B2 (en) | Flat panel display using bootstrap circuit | |
JP2014085648A (en) | Display device and drive circuit | |
US20050073349A1 (en) | Voltage level transferring circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: TOSHIBA MATSUSHITA DISPLAY TECHNOLOGY CO., LTD., J Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MORITA, TETSUO;REEL/FRAME:016776/0717 Effective date: 20050614 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: JAPAN DISPLAY CENTRAL INC., JAPAN Free format text: CHANGE OF NAME;ASSIGNOR:TOSHIBA MOBILE DISPLAY CO., LTD.;REEL/FRAME:028339/0316 Effective date: 20120330 Owner name: TOSHIBA MOBILE DISPLAY CO., LTD., JAPAN Free format text: CHANGE OF NAME;ASSIGNOR:TOSHIBA MATSUSHITA DISPLAY TECHNOLOGY CO., LTD.;REEL/FRAME:028339/0273 Effective date: 20090525 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |