US20060010410A1 - Genie: a method for classification and graphical display of negative slack timing test failures - Google Patents
Genie: a method for classification and graphical display of negative slack timing test failures Download PDFInfo
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- IBM® is a registered trademark of International Business Machines Corporation, Armonk, N.Y., U.S.A. and other names used herein may be registered trademarks, trademarks or product names of International Business Machines Corporation or other companies.
- This invention relates to circuit design, and particularly a tool for integrated circuit design, one which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer.
- Endpoint Report is a text based file which contains detailed descriptions of timing test failures. Endpoint reports are very lengthy and verbose, requiring users to scroll horizontally and vertically. They do not group related paths nor identify the overlapping segments within them. There is a lot of information in an endpoint report; so much that often there is too much information for an engineer to comprehend.
- Critical Path Chart This is a chart that graphically represents paths using multiple colors and bars of different length representing logic and wire delay.
- the critical path chart cannot find relationships between failing paths.
- the graphical representation can hint at the relationships, but the critical path chart does not definitively describe the commonality between them.
- a tool is needed which can condense many thousands of failing paths into a concise format which identifies repetition/commonality amongst those paths. Such a tool will save design engineers a lot of time in fixing timing problems by providing insight and priorities for fixing negative slack timing test failures.
- Genie is a tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer.
- Genie groups failing paths into Timing Islands.
- a timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub.
- the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.
- FIG. 1 illustrates one example of the application of the preferred embodiment where a timing island is a group of failing timing paths that contain at least one shared segment or hub.
- FIG. 2 illustrates an example of a preferred timing path flowchart for generating a timing island file which represents the islands.
- FIG. 4 illustrated the interrelationship of timing islands showing shared cells.
- a cell is a logic device or element such as a latch, AND gate, SRAM, etc.
- Endpoint Report is a text based file which contains detailed descriptions of timing test failures. Endpoint reports are very lengthy and verbose, requiring users to scroll horizontally and vertically. They do not group related paths nor identify the overlapping segments within them. There is a lot of information in an endpoint report; so much that often there is too much information for an engineer to comprehend.
- Critical Path Chart This is a chart that graphically represents paths using multiple colors and bars of different length representing logic and wire delay.
- the critical path chart cannot find relationships between failing paths.
- the graphical representation can hint at the relationships, but the critical path chart does not definitively describe the commonality between them.
- a tool is needed which can condense many thousands of failing paths into a concise format which identifies repetition/commonality amongst those paths. Such a tool will save design engineers a lot of time in fixing timing problems by providing insight and priorities for fixing negative slack timing test failures.
- Genie is a tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer.
- Genie groups failing paths into Timing Islands.
- a timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub.
- the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.
- Genie As illustrated in FIG. 2 , generates a custom endpoint report: this contains only a subset of information available in traditional endpoint reports.
- the custom report is designed to be interpreted by a computer program, not a human being, and is condensed to keep data processing and storage requirements to a minimum.
- Genie processes the custom endpoint report using an abstraction of a DNA sequence alignment algorithm to group timing paths into timing islands.
- DNA sequence alignment is used to locate regions of similarity between a query sequence (sequence of unknown function and structure) and other known DNA sequences. These regions of similarity help reveal the homology, genealogy, functionality and structure of the query sequence.
- similar methodology may be used to discover independent timing problems in ASIC designs. Timing paths within an ASIC may be represented as sequences of segments (a segment being a pin to pin connection) instead of sequences of amino acids as with DNA. Like the DNA sequences, the ASIC timing path sequences may be aligned with each other to discover homogenous regions (partial path equalities). The partial path equivalences, which are defined as hubs, tend to be the most likely cause of timing problems and are of high interest to the designer.
- Aligning DNA sequences involves comparing the sequences to find a series of characters or patterns that are in the same order in both of the sequences.
- the two sequences can be written on a page in two rows on top of one another.
- the objective will be to find the alignment, where the greatest number of identical characters, are in vertical register. Often this involves inserting gaps and aligning mismatched characters.
- Table 1 shows a small example. TABLE 1 (Human alignment of two sequences which happen to be of unequal length) SEQ1 VESLCY SEQ2 VDSCY VESLCY VDS-CY
- This Dot Matrix algorithm has become a standard tool which can quickly determine whether two sequences may have a possible alignment. This algorithm sets up a comparison matrix to determine the sequence similarities. Using the same small sequences as in Table 1, an example of a Dot Matrix algorithm follows in Table 2: TABLE 2 V E S L C Y V X D S X C X Y X
- each column of the matrix represents a letter of sequence one and each row represents a character of sequence two.
- each position of the matrix is marked with an X if both the letter at the top of the column and the beginning of the row are the same. Everywhere an X shows up there is a similarity between the sequences. It is ideal to find long diagonal strings of Xs (CiRi, Ci+1Ri+1 . . . . Ci+kRi+k where i,k integers >0 and C means column and R means row) as this indicates a possible conserved region (regions of similar function or structure). The longest diagonal in the example is found at C5R4 and continues through C6R5. The completed matrix infers the following alignment illustrated by Table 3. TABLE 3 V_S_CY V_S CY
- Each_(underscored space) in the alignment represents a character which was not aligned and each blank between characters which is not underscored represents a gap. Using short sequences as in the above example it is easy to determine what the alignment should be and where the gaps should go.
- timing paths need share only one segment to be part of the same island and all path sequences must be compared against each other to properly find exclusive timing islands.
- Dot Matrix Algorithm is designed to fully compare two sequences to find all like amino acid subsequences between two DNA sequences or sometimes executed multiple times to compare a query sequence against a large database of sequences.
- the first point, that paths need only share one segment to be members of the same island, may be implemented by modifying the Dot-Matrix algorithm as follows.
- the example based on Table 2 may be used again by replacing the DNA sequences with timing path sequences (since the sequences in Table 2 are composed of unique elements, the same sequences may represent timing paths).
- Examining the Table 2 shows a common segment in the comparison of C1R1. This fits the definition of a timing island, thus the two sequences are part of the same island. In addition this happens to be the best case performance result since only one compare was needed to determine whether the paths had similarity.
- the algorithm may stop here and compare the query sequence to the next sequence in the report. Ending the sequence alignment before a complete comparison is part of the abstraction.
- the worst case performance scenario is two paths that have no commonality. This would cause a full comparison of all segments in each path.
- the second point, that all paths must be compared to all other paths may be interpreted as the following. If there are N failing tests, the unmodified Dot Matrix Algorithm must be run N ⁇ 2 times to ensure the resulting islands are exclusive. As the number of failing paths increases the O(N ⁇ 2) runtime would increase to levels which may drastically affect usability. This situation has been accounted for in the Genie algorithm. In a situation where the first path in the report has a similar segment to all of the other paths, there would only be one island. Ideally in this situation, the program would stop after the first path has been compared to all paths in the report. Run time for this best case situation is in O(N) time.
- FIG. 2 provides a detailed description of the complete Genie timing island generation algorithm.
- the Genie Algorithm finishes by writing out a timing island file (formatted contents of the remaining bins).
- the timing island file will be read by Genie's Graphical User Interface, which displays the timing island information.
- Genie GUI Graphical User Interface
- users are able to see each of the independent timing islands.
- the GUI allows users to probe into each island to see its comprising segments. Islands are sorted by the worst slack within them, which prioritizes each island by the severity of the timing failures. Segments within islands are sorted by the number of paths they are repeated in, identifying the hub at the top of the list and the “leaves” at the bottom.
- Genie allows users to select the color that the island is displayed in, and will draw the hub in a brighter hue than the rest of the segments. This will allow users to visually identify hubs on the layout, and give insight how to fix the timing failure within the hub.
- Genie can color fixed (here, we mean immobile; constrained by the placement) cells blue along paths it displays. The user can enable and disable this feature easily within the Genie program.
- Genie provides a slack analysis tool and a net weight display tool. Users can select one or more cells within ChipBench and Genie will display vectors describing the slack pulling on the cell(s). Color is used to represent the amount of slack—red for negative slack; and yellow, orange, and blue for various amounts of positive slack. Genie looks through timing optimization buffers when computing these slacks, therefore the vectors actually point to the next connecting logic device, not to a timing buffer. Designers can use the slack analysis capability to determine if and how cells might be relocated within a placed design to cure timing failures. Genie's net weight display tool is similar to the slack analysis tool in that it draws vectors representing the net weights pulling on selected cells. This information will provide the designer some background information, perhaps explaining why a cell was placed in a particular location.
- timing optimization buffers are a significant feature of the slack analysis and net weight tools.
- Genie is essentially comparing two VIM states—the VIM after timing optimization but pre-placement, and the placement-optimized VIM—to compute accurate slacks on a placed design. This capability allows designers to directly see how placement has affected their timing. Buffer look-through allows for the observation of the logic connectivity before placement optimization. Observing this pre-placement optimized connectivity allows users to quickly understand the important point connections within the placement-optimized design. For instance the designer should not care where the timing optimization buffers are placed as long as the path meets it's timing requirements.
- the FIG. 3 below shows an example of the same path in two VIM states.
- Genie solves the problem depicted in the above FIG. 3 by tracing through the buffers and displaying a single vector from L 1 to L 2 .
- This vector is the representation of the timing optimized VIM connectivity within the placement optimized VIM.
- the first is “common cell island groups”, in which timing islands sharing one or more common cells will be linked together for display. This function would permit designers to see timing problems stemming from, driving to, or passing through common cells—a type of analysis that does not currently exist.
- “common cell island chains” link together all timing groups that contain a common timing island, thus connecting the islands into chains based on shared cells. Examples of both common cell island groups and common cell island chains are depicted in FIG. 4 .
- “incremental buffer strip and rebuild” is a feature which relates to the Genie slack analysis tool.
- Genie computes slack by looking through the buffers. However, the buffers are still in the placement, which could possibly make the slacks appear to get worse. This new feature will detect a movement, and will strip out and reinsert timing optimization buffers in new locations reflecting the new position of the cell(s).
- Genie will show additional path characteristics.
- Genie will color fixed cells blue; with this new feature, cells which have particular syn_hide keywords and other special attributes will be colored different shades or otherwise displayed differently to the user. This information is already available within ChipBench, but not in this format.
- Genie can be used to parallelize timing optimization. That is, a designer can use Genie to isolate timing islands, and dispatch several machines concurrently to attack each respective island. The designer can then pull all of the parallel fixes back together in one final processing pass on a single machine to discover any remaining problems or conflicts.
- the capabilities of the present invention can be implemented in software, firmware, hardware or some combination thereof and used to provide a service for use in chip design.
- one or more aspects of the present invention can be included in an tool of manufacture (e.g., one or more computer program products) having, for instance, computer usable media.
- the media has embodied therein, for instance, computer readable program code means for providing and facilitating the capabilities of the present invention.
- the article of manufacture can be included as a part of a computer system or sold separately.
- At least one program storage device readable by a machine, tangibly embodying at least one program of instructions executable by the machine to perform the capabilities of the present invention can be provided.
Abstract
Description
- This application is a continuation in part of U.S. Ser. No. 10/890,463, filed Jul. 12, 2004, and entitled “Method, System and Storage Medium for Determining Circuit Placement” by James Curtin et al., and contains subject matter which is related to the subject matter of the following co-pending applications, each of which is assigned to the same assignee as this application, International Business Machines Corporation of Armonk, N.Y. Each of the below listed applications is hereby incorporated herein by reference in its entirety:
- USSN (POU920050006US1) filed concurrently herewith and entitled “A method for netlist path characteristics extraction”
- USSN (POU920050004US1) filed concurrently herewith and entitled “Negative Slack Recoverability Factor—A net weight to enhance timing closure behavior”
- IBM® is a registered trademark of International Business Machines Corporation, Armonk, N.Y., U.S.A. and other names used herein may be registered trademarks, trademarks or product names of International Business Machines Corporation or other companies.
- 1. Field of the Invention
- This invention relates to circuit design, and particularly a tool for integrated circuit design, one which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer.
- 2. Description of Background
- When performing timing analysis of paths within chips there often are many hundreds or thousands of paths which fail to meet timing requirements. Many of those failing paths can be related in that a few common segments within them are causing timing failures, and all the rest of the connections within the paths are very close to or meet timing. Unfortunately, a tool does not exist which can find the commonality in failing paths.
- Commonly, these paths are reported to users in the form of an Endpoint Report. The Endpoint report is a text based file which contains detailed descriptions of timing test failures. Endpoint reports are very lengthy and verbose, requiring users to scroll horizontally and vertically. They do not group related paths nor identify the overlapping segments within them. There is a lot of information in an endpoint report; so much that often there is too much information for an engineer to comprehend.
- One known solution to the problem of having too much information can be found in the Critical Path Chart. This is a chart that graphically represents paths using multiple colors and bars of different length representing logic and wire delay. However, the critical path chart cannot find relationships between failing paths. The graphical representation can hint at the relationships, but the critical path chart does not definitively describe the commonality between them.
- A tool is needed which can condense many thousands of failing paths into a concise format which identifies repetition/commonality amongst those paths. Such a tool will save design engineers a lot of time in fixing timing problems by providing insight and priorities for fixing negative slack timing test failures.
- The shortcomings of the prior art are overcome and additional advantages are provided through the provision of the tool we call Genie which is a tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.
- Previously, using only endpoint reports or the critical path chart, users would not be able to easily identify the hub, and would spend days and weeks manually investigating individual paths. Users would often cull only the worst 500 or so failing paths and ignore the rest (perhaps thousands) because there was too much information to handle.
- Our system during setup allows the user to maker a choice between late mode and early mode for the Endpoint report and the tests they would like to run.
- System and computer program products corresponding to the above-summarized methods are also described and claimed herein.
- Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.
- The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
-
FIG. 1 illustrates one example of the application of the preferred embodiment where a timing island is a group of failing timing paths that contain at least one shared segment or hub. -
FIG. 2 illustrates an example of a preferred timing path flowchart for generating a timing island file which represents the islands. -
FIG. 3 illustrates a timing optimized VIM (VIM=VLSI Integrated Model) and a placement optimized VIM. -
FIG. 4 illustrated the interrelationship of timing islands showing shared cells. A cell is a logic device or element such as a latch, AND gate, SRAM, etc. - The detailed description explains the preferred embodiments of the invention, together with advantages and features, by way of example with reference to the drawings.
- When performing late mode timing analysis of paths within chips, those paths which cannot meet timing are labeled as having a negative slack—their signals propagate too slowly causing data to arrive late. Often there are many hundreds or thousands of paths which fail to meet timing requirements. Many of those failing paths can be related in that a few common segments within them are causing timing failures, and all of the rest of the connections within the paths are very close to or meet timing. Unfortunately, a tool does not exist which can find the commonality in failing paths.
- Commonly, these paths are reported to users in the form of an Endpoint Report. The Endpoint report is a text based file which contains detailed descriptions of timing test failures. Endpoint reports are very lengthy and verbose, requiring users to scroll horizontally and vertically. They do not group related paths nor identify the overlapping segments within them. There is a lot of information in an endpoint report; so much that often there is too much information for an engineer to comprehend.
- One known solution to the problem of having too much information can be found in the Critical Path Chart. This is a chart that graphically represents paths using multiple colors and bars of different length representing logic and wire delay. However, the critical path chart cannot find relationships between failing paths. The graphical representation can hint at the relationships, but the critical path chart does not definitively describe the commonality between them.
- A tool is needed which can condense many thousands of failing paths into a concise format which identifies repetition/commonality amongst those paths. Such a tool will save design engineers a lot of time in fixing timing problems by providing insight and priorities for fixing negative slack timing test failures.
- Genie is a tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.
- Previously, using only endpoint reports or the critical path chart, users would not be able to easily identify the hub, and would spend days and weeks manually investigating individual paths. Users would often cull only the worst 500 or so failing paths and ignore the rest (perhaps thousands) because there was too much information to handle.
- A significant portion of Genie has already been implemented as software that extends, and is being incorporated into, IBM EDA's ChipBench suite, a preferred chip design tool, using Chipbench: version 10.1 maint 66. First, Genie, as illustrated in
FIG. 2 , generates a custom endpoint report: this contains only a subset of information available in traditional endpoint reports. The custom report is designed to be interpreted by a computer program, not a human being, and is condensed to keep data processing and storage requirements to a minimum. - Genie processes the custom endpoint report using an abstraction of a DNA sequence alignment algorithm to group timing paths into timing islands. Typically, DNA sequence alignment is used to locate regions of similarity between a query sequence (sequence of unknown function and structure) and other known DNA sequences. These regions of similarity help reveal the homology, genealogy, functionality and structure of the query sequence. Likewise, similar methodology may be used to discover independent timing problems in ASIC designs. Timing paths within an ASIC may be represented as sequences of segments (a segment being a pin to pin connection) instead of sequences of amino acids as with DNA. Like the DNA sequences, the ASIC timing path sequences may be aligned with each other to discover homogenous regions (partial path equalities). The partial path equivalences, which are defined as hubs, tend to be the most likely cause of timing problems and are of high interest to the designer.
- Aligning DNA sequences involves comparing the sequences to find a series of characters or patterns that are in the same order in both of the sequences. The two sequences can be written on a page in two rows on top of one another. The objective will be to find the alignment, where the greatest number of identical characters, are in vertical register. Often this involves inserting gaps and aligning mismatched characters. Table 1 shows a small example.
TABLE 1 (Human alignment of two sequences which happen to be of unequal length) SEQ1 VESLCY SEQ2 VDSCY VESLCY VDS-CY - As seen in Table 1 the two sequences are of unequal length and required the insertion of a gap and left one pair of characters (amino acids E and D) mismatched. This example is representative of a simple DNA sequence alignment.
-
- However, DNA sequences are lengthy and human alignment can be error prone and very time consuming. This created a need to develop alignment algorithms that would reduce time and error. Most alignment algorithms use various forms of matrices. The first algorithm to use the matrix approach was the Dot Matrix algorithm described by Gibbs and McIntyre (1970) which is incorporated herein and is found as Gibbs & McIntyre, 1970
- Gibbs, A. J. & McIntyre, G. A. (1970).
- The Diagram Method for Comparing Sequences. Its Use with Amino Acid and Nucleotide Sequences.
- Eur. J. Biochem. 16, 1-11.
- However, DNA sequences are lengthy and human alignment can be error prone and very time consuming. This created a need to develop alignment algorithms that would reduce time and error. Most alignment algorithms use various forms of matrices. The first algorithm to use the matrix approach was the Dot Matrix algorithm described by Gibbs and McIntyre (1970) which is incorporated herein and is found as Gibbs & McIntyre, 1970
- This Dot Matrix algorithm has become a standard tool which can quickly determine whether two sequences may have a possible alignment. This algorithm sets up a comparison matrix to determine the sequence similarities. Using the same small sequences as in Table 1, an example of a Dot Matrix algorithm follows in Table 2:
TABLE 2 V E S L C Y V X D S X C X Y X - In accordance with the preferred process, first a matrix is set up where each column of the matrix represents a letter of sequence one and each row represents a character of sequence two. Once the matrix is set up, each position of the matrix is marked with an X if both the letter at the top of the column and the beginning of the row are the same. Everywhere an X shows up there is a similarity between the sequences. It is ideal to find long diagonal strings of Xs (CiRi, Ci+1Ri+1 . . . . Ci+kRi+k where i,k integers >0 and C means column and R means row) as this indicates a possible conserved region (regions of similar function or structure). The longest diagonal in the example is found at C5R4 and continues through C6R5. The completed matrix infers the following alignment illustrated by Table 3.
TABLE 3 V_S_CY V_S CY - Each_(underscored space) in the alignment represents a character which was not aligned and each blank between characters which is not underscored represents a gap. Using short sequences as in the above example it is easy to determine what the alignment should be and where the gaps should go.
- The problem with this algorithm is the possibility of character repetition in DNA sequences. Just as an example what if the two sequences were VVVVVV and VVVVV. Applying the dot matrix algorithm would cause every location in the matrix to be marked with an X. This is both a downfall and advantage of the Dot Matrix algorithm. Interpreting the resulting matrix may make for a difficult alignment but at the same time, may indicate regions of special interest in the DNA sequence. In order to alleviate the alignment problems due to amino acid repetition the Dot Matrix algorithm evolved into an algorithm which used a unary scoring matrix. Instead of Xs each match was marked with a 1 and gap penalties were also issued. Yet, unlike a DNA sequence, ASIC timing paths are built of unique segments, where each segment is found only once in the design. Therefore, repetition and substitution are not issues with timing path alignment and an abstraction of the basic Dot Matrix method will be sufficient to perform timing island discovery.
- The abstraction on the Dot Matrix algorithm and the concept of timing islands are what make the Genie algorithm unique. In order to properly explain the abstraction, the problem will be restated.
- Genie must process a custom report of failing timing paths into a group of timing islands, where a timing island is a group of failing timing paths that contain at least one shared segment (see
FIG. 1 ). So, the preferred embodiment employs key points for the Genie implementation, these are: timing paths need share only one segment to be part of the same island and all path sequences must be compared against each other to properly find exclusive timing islands. These are key differences to the Dot Matrix algorithm. The Dot Matrix Algorithm is designed to fully compare two sequences to find all like amino acid subsequences between two DNA sequences or sometimes executed multiple times to compare a query sequence against a large database of sequences. - The first point, that paths need only share one segment to be members of the same island, may be implemented by modifying the Dot-Matrix algorithm as follows. The example based on Table 2 may be used again by replacing the DNA sequences with timing path sequences (since the sequences in Table 2 are composed of unique elements, the same sequences may represent timing paths). Examining the Table 2 shows a common segment in the comparison of C1R1. This fits the definition of a timing island, thus the two sequences are part of the same island. In addition this happens to be the best case performance result since only one compare was needed to determine whether the paths had similarity. The algorithm may stop here and compare the query sequence to the next sequence in the report. Ending the sequence alignment before a complete comparison is part of the abstraction. The worst case performance scenario is two paths that have no commonality. This would cause a full comparison of all segments in each path.
- The second point, that all paths must be compared to all other paths may be interpreted as the following. If there are N failing tests, the unmodified Dot Matrix Algorithm must be run Nˆ2 times to ensure the resulting islands are exclusive. As the number of failing paths increases the O(Nˆ2) runtime would increase to levels which may drastically affect usability. This situation has been accounted for in the Genie algorithm. In a situation where the first path in the report has a similar segment to all of the other paths, there would only be one island. Ideally in this situation, the program would stop after the first path has been compared to all paths in the report. Run time for this best case situation is in O(N) time.
- In the situation where all paths are exclusive the algorithm would have to compare all paths against each other giving the worst case runtime O(Nˆ2). This is also reduced in the Genie algorithm by instantiating the use of temporary bins to hold intermediate results. These intermediate results are used to gradually define the islands. Placing the intermediate results into bins allows the worst case runtime to be reduced from O(Nˆ2) (all paths are exclusive) to O((Nˆ2+N)/2) and the best case time remains O(N). In effect, the temporary bins help eliminate redundant segment compares and still allows for exclusivity amongst timing islands.
FIG. 2 provides a detailed description of the complete Genie timing island generation algorithm. - The Genie Algorithm finishes by writing out a timing island file (formatted contents of the remaining bins). The timing island file will be read by Genie's Graphical User Interface, which displays the timing island information. From the Genie GUI, users are able to see each of the independent timing islands. The GUI allows users to probe into each island to see its comprising segments. Islands are sorted by the worst slack within them, which prioritizes each island by the severity of the timing failures. Segments within islands are sorted by the number of paths they are repeated in, identifying the hub at the top of the list and the “leaves” at the bottom.
- Users can select timing islands or segments, or any combination of the two, and display them superimposed upon a placed design layout. Genie allows users to select the color that the island is displayed in, and will draw the hub in a brighter hue than the rest of the segments. This will allow users to visually identify hubs on the layout, and give insight how to fix the timing failure within the hub.
- Genie can color fixed (here, we mean immobile; constrained by the placement) cells blue along paths it displays. The user can enable and disable this feature easily within the Genie program.
- In addition to timing island analysis, Genie provides a slack analysis tool and a net weight display tool. Users can select one or more cells within ChipBench and Genie will display vectors describing the slack pulling on the cell(s). Color is used to represent the amount of slack—red for negative slack; and yellow, orange, and blue for various amounts of positive slack. Genie looks through timing optimization buffers when computing these slacks, therefore the vectors actually point to the next connecting logic device, not to a timing buffer. Designers can use the slack analysis capability to determine if and how cells might be relocated within a placed design to cure timing failures. Genie's net weight display tool is similar to the slack analysis tool in that it draws vectors representing the net weights pulling on selected cells. This information will provide the designer some background information, perhaps explaining why a cell was placed in a particular location.
- Looking through timing optimization buffers is a significant feature of the slack analysis and net weight tools. By looking through timing optimization buffers, Genie is essentially comparing two VIM states—the VIM after timing optimization but pre-placement, and the placement-optimized VIM—to compute accurate slacks on a placed design. This capability allows designers to directly see how placement has affected their timing. Buffer look-through allows for the observation of the logic connectivity before placement optimization. Observing this pre-placement optimized connectivity allows users to quickly understand the important point connections within the placement-optimized design. For instance the designer should not care where the timing optimization buffers are placed as long as the path meets it's timing requirements. The
FIG. 3 below shows an example of the same path in two VIM states. - Genie solves the problem depicted in the above
FIG. 3 by tracing through the buffers and displaying a single vector from L1 to L2. This vector is the representation of the timing optimized VIM connectivity within the placement optimized VIM. - Whereas all of the above features currently exist in Genie, there are several other features which are included in our preferred embodiment. The first is “common cell island groups”, in which timing islands sharing one or more common cells will be linked together for display. This function would permit designers to see timing problems stemming from, driving to, or passing through common cells—a type of analysis that does not currently exist. Also, “common cell island chains” link together all timing groups that contain a common timing island, thus connecting the islands into chains based on shared cells. Examples of both common cell island groups and common cell island chains are depicted in
FIG. 4 . - Next, “incremental buffer strip and rebuild” is a feature which relates to the Genie slack analysis tool. When users move cells, Genie computes slack by looking through the buffers. However, the buffers are still in the placement, which could possibly make the slacks appear to get worse. This new feature will detect a movement, and will strip out and reinsert timing optimization buffers in new locations reflecting the new position of the cell(s). Lastly, Genie will show additional path characteristics. Currently, Genie will color fixed cells blue; with this new feature, cells which have particular syn_hide keywords and other special attributes will be colored different shades or otherwise displayed differently to the user. This information is already available within ChipBench, but not in this format.
- Applications in the synthesis process flow also exist for Genie. For instance, designers can use the grouping capabilities to discover dependencies between cells of logic. Finally, Genie can be used to parallelize timing optimization. That is, a designer can use Genie to isolate timing islands, and dispatch several machines concurrently to attack each respective island. The designer can then pull all of the parallel fixes back together in one final processing pass on a single machine to discover any remaining problems or conflicts.
- The capabilities of the present invention can be implemented in software, firmware, hardware or some combination thereof and used to provide a service for use in chip design.
- As one example, one or more aspects of the present invention can be included in an tool of manufacture (e.g., one or more computer program products) having, for instance, computer usable media. The media has embodied therein, for instance, computer readable program code means for providing and facilitating the capabilities of the present invention. The article of manufacture can be included as a part of a computer system or sold separately.
- Additionally, at least one program storage device readable by a machine, tangibly embodying at least one program of instructions executable by the machine to perform the capabilities of the present invention can be provided.
- The flow diagrams depicted herein are just examples. There may be many variations to these diagrams or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order, or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention.
- While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.
Claims (20)
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US11/180,740 US7376924B2 (en) | 2004-07-12 | 2005-07-13 | Methods for placement which maintain optimized behavior, while improving wireability potential |
US11/934,995 US7823108B2 (en) | 2004-07-12 | 2007-11-05 | Chip having timing analysis of paths performed within the chip during the design process |
US12/047,382 US7921398B2 (en) | 2004-07-12 | 2008-03-13 | System and medium for placement which maintain optimized timing behavior, while improving wireability potential |
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US10/890,463 US7120888B2 (en) | 2004-07-12 | 2004-07-12 | Method, system and storage medium for determining circuit placement |
US11/129,784 US7356793B2 (en) | 2004-07-12 | 2005-05-16 | Genie: a method for classification and graphical display of negative slack timing test failures |
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US10/890,463 Continuation-In-Part US7120888B2 (en) | 2004-07-12 | 2004-07-12 | Method, system and storage medium for determining circuit placement |
US11/129,786 Continuation-In-Part US7290233B2 (en) | 2004-07-12 | 2005-05-16 | Method for netlist path characteristics extraction |
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US11/129,785 Continuation-In-Part US7305644B2 (en) | 2004-07-12 | 2005-05-16 | Negative slack recoverability factor—a net weight to enhance timing closure behavior |
US11/934,995 Continuation US7823108B2 (en) | 2004-07-12 | 2007-11-05 | Chip having timing analysis of paths performed within the chip during the design process |
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US20100064264A1 (en) * | 2008-09-10 | 2010-03-11 | International Business Machines Corporation | Method to graphically identify registers with unbalanced slack as part of placement driven synthesis optimization |
CN102156771A (en) * | 2011-01-20 | 2011-08-17 | 北京中星微电子有限公司 | Method and device for generating data path according to bit value |
US8082535B1 (en) * | 2009-02-03 | 2011-12-20 | Xilinx, Inc. | Method and apparatus for testing programmable integrated circuits |
US20160188774A1 (en) * | 2009-01-30 | 2016-06-30 | Synopsys, Inc. | Circuit Design and Optimization |
US9405871B1 (en) * | 2014-12-05 | 2016-08-02 | Xilinx, Inc. | Determination of path delays in circuit designs |
CN108280191A (en) * | 2018-01-25 | 2018-07-13 | 北京工商大学 | The comparison visual analysis method and system of more areas MRL standards |
US10846453B1 (en) * | 2018-09-20 | 2020-11-24 | Synopsys, Inc. | Generating interrelated path groups by using machine learning |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7356793B2 (en) * | 2004-07-12 | 2008-04-08 | International Business Machines Corporation | Genie: a method for classification and graphical display of negative slack timing test failures |
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US9996656B2 (en) | 2016-06-27 | 2018-06-12 | International Business Machines Corporation | Detecting dispensable inverter chains in a circuit design |
Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5220512A (en) * | 1990-04-19 | 1993-06-15 | Lsi Logic Corporation | System for simultaneous, interactive presentation of electronic circuit diagrams and simulation data |
US5587919A (en) * | 1994-04-22 | 1996-12-24 | Lucent Technologies, Inc. | Apparatus and method for logic optimization by redundancy addition and removal |
US5636372A (en) * | 1994-09-30 | 1997-06-03 | International Business Machines Corporation | Network timing analysis method which eliminates timing variations between signals traversing a common circuit path |
US5790435A (en) * | 1991-11-12 | 1998-08-04 | Chronology Corporation | Automated development of timing diagrams for electrical circuits |
US6209123B1 (en) * | 1996-11-01 | 2001-03-27 | Motorola, Inc. | Methods of placing transistors in a circuit layout and semiconductor device with automatically placed transistors |
US20020013933A1 (en) * | 2000-05-26 | 2002-01-31 | Nec Corporation | Graphic data conversion method and its apparatus |
US6470482B1 (en) * | 1990-04-06 | 2002-10-22 | Lsi Logic Corporation | Method and system for creating, deriving and validating structural description of electronic system from higher level, behavior-oriented description, including interactive schematic design and simulation |
US6643683B1 (en) * | 2000-05-08 | 2003-11-04 | International Business Machines Corporation | Interactive client-server environment for performing collaborative timing analysis of circuit designs |
US20030229865A1 (en) * | 2002-06-11 | 2003-12-11 | Sergei Bakarian | Method for eliminating false failures saved by redundant paths during circuit area analysis on an integrated circuit layout |
US20040153988A1 (en) * | 2000-10-03 | 2004-08-05 | Fujitsu Limited | Placement/net wiring processing system |
US20040205681A1 (en) * | 2003-01-16 | 2004-10-14 | Yasuyuki Nozuyama | Calculation system of fault coverage and calculation method of the same |
US20050066297A1 (en) * | 2003-09-18 | 2005-03-24 | Kerim Kalafala | System and method for correlated process pessimism removal for static timing analysis |
US20050262463A1 (en) * | 2001-02-12 | 2005-11-24 | Cohn John M | Wiring optimizations for power |
US20060259885A1 (en) * | 2004-08-09 | 2006-11-16 | Mortensen Michael P | System and method for analyzing a circuit |
Family Cites Families (39)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5095454A (en) * | 1989-05-25 | 1992-03-10 | Gateway Design Automation Corporation | Method and apparatus for verifying timing during simulation of digital circuits |
US5218551A (en) | 1990-04-30 | 1993-06-08 | International Business Machines Corporation | Timing driven placement |
US5237514A (en) | 1990-12-21 | 1993-08-17 | International Business Machines Corporation | Minimizing path delay in a machine by compensation of timing through selective placement and partitioning |
EP0643855A1 (en) | 1992-06-04 | 1995-03-22 | Xilinx, Inc. | Timing driven method for laying out a user's circuit onto a programmable integrated circuit device |
JP2601168B2 (en) | 1993-03-30 | 1997-04-16 | 日本電気株式会社 | Method of retiming and redesigning sequential circuit |
JP2601177B2 (en) | 1993-06-08 | 1997-04-16 | 日本電気株式会社 | Method for determining optimal clock period in synchronous logic circuit |
US5608645A (en) | 1994-03-17 | 1997-03-04 | Vlsi Technology, Inc. | Method of finding a critical path in a circuit by considering the clock skew |
US5719783A (en) * | 1996-02-07 | 1998-02-17 | Unisys Corporation | Method and apparatus for performing timing analysis on a circuit design |
CN1127147C (en) | 1997-07-03 | 2003-11-05 | 松下电器产业株式会社 | Synthesis method for functional block model with stream line circuit and streamline circuit apparatus |
US6086631A (en) | 1998-04-08 | 2000-07-11 | Xilinx, Inc. | Post-placement residual overlap removal method for core-based PLD programming process |
US6099583A (en) | 1998-04-08 | 2000-08-08 | Xilinx, Inc. | Core-based placement and annealing methods for programmable logic devices |
JP4693197B2 (en) * | 1998-04-23 | 2011-06-01 | 株式会社東芝 | Semiconductor memory device |
US6915249B1 (en) * | 1998-05-14 | 2005-07-05 | Fujitsu Limited | Noise checking method and apparatus |
US6397170B1 (en) | 1998-08-18 | 2002-05-28 | International Business Machines Corporation | Simulation based power optimization |
US6233724B1 (en) | 1998-10-30 | 2001-05-15 | Micron Technology, Inc. | Circuit synthesis time budgeting based upon wireload information |
US6601226B1 (en) | 2000-03-14 | 2003-07-29 | Synopsys, Inc. | Tightloop method of timing driven placement |
US7139992B2 (en) * | 2000-12-01 | 2006-11-21 | Sun Microsystems, Inc. | Short path search using tiles and piecewise linear cost propagation |
JP4218924B2 (en) | 2001-02-15 | 2009-02-04 | 株式会社日立製作所 | Semiconductor integrated circuit design system |
JP2002245110A (en) | 2001-02-19 | 2002-08-30 | Matsushita Electric Ind Co Ltd | Method for allocating clock timing |
US6598209B1 (en) | 2001-02-28 | 2003-07-22 | Sequence Design, Inc. | RTL power analysis using gate-level cell power models |
JP2002366605A (en) * | 2001-06-11 | 2002-12-20 | Hitachi Ltd | Delay time display method |
US6836753B1 (en) | 2001-06-13 | 2004-12-28 | Cadence Design Systems, Inc. | Cone slack allocator for computing time budgets |
US6507937B1 (en) | 2001-06-19 | 2003-01-14 | Lsi Logic Corporation | Method of global placement of control cells and hardmac pins in a datapath macro for an integrated circuit design |
US6754763B2 (en) * | 2001-07-30 | 2004-06-22 | Axis Systems, Inc. | Multi-board connection system for use in electronic design automation |
US20030145294A1 (en) * | 2002-01-25 | 2003-07-31 | Ward Julie Ann | Verifying interconnect fabric designs |
US6698005B2 (en) | 2002-02-19 | 2004-02-24 | Telefonaktiebolaget L M Ericsson (Publ) | Min-time / race margins in digital circuits |
US6952816B2 (en) | 2002-10-07 | 2005-10-04 | Hewlett-Packard Development Company, L.P. | Methods and apparatus for digital circuit design generation |
US7096438B2 (en) | 2002-10-07 | 2006-08-22 | Hewlett-Packard Development Company, L.P. | Method of using clock cycle-time in determining loop schedules during circuit design |
US7000210B2 (en) | 2002-11-05 | 2006-02-14 | Lattice Semiconductor Corporation | Adaptive adjustment of constraints during PLD placement processing |
US7013445B1 (en) | 2002-12-31 | 2006-03-14 | Cadence Design Systems, Inc. | Post processor for optimizing manhattan integrated circuits placements into non manhattan placements |
WO2004109706A2 (en) * | 2003-06-02 | 2004-12-16 | California Institute Of Technology | Nanoscale wire-based sublithographic programmable logic arrays |
US7137093B2 (en) | 2003-08-08 | 2006-11-14 | Cadence Design Systems, Inc. | Post-placement timing optimization of IC layout |
US6930934B2 (en) * | 2003-10-28 | 2005-08-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | High efficiency redundancy architecture in SRAM compiler |
US7494146B2 (en) * | 2007-03-30 | 2009-02-24 | Merida Industry Co., Ltd. | Bicycle frame |
US7376924B2 (en) | 2004-07-12 | 2008-05-20 | International Business Machines Corporation | Methods for placement which maintain optimized behavior, while improving wireability potential |
US7356793B2 (en) * | 2004-07-12 | 2008-04-08 | International Business Machines Corporation | Genie: a method for classification and graphical display of negative slack timing test failures |
JP4082616B2 (en) * | 2005-01-17 | 2008-04-30 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Signal propagation path drawing apparatus, drawing method and program thereof |
US7490305B2 (en) * | 2006-07-17 | 2009-02-10 | International Business Machines Corporation | Method for driving values to DC adjusted/untimed nets to identify timing problems |
US7853912B2 (en) * | 2007-11-05 | 2010-12-14 | International Business Machines Corporation | Arrangements for developing integrated circuit designs |
-
2005
- 2005-05-16 US US11/129,784 patent/US7356793B2/en not_active Expired - Fee Related
-
2007
- 2007-11-05 US US11/934,995 patent/US7823108B2/en not_active Expired - Fee Related
Patent Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6470482B1 (en) * | 1990-04-06 | 2002-10-22 | Lsi Logic Corporation | Method and system for creating, deriving and validating structural description of electronic system from higher level, behavior-oriented description, including interactive schematic design and simulation |
US5220512A (en) * | 1990-04-19 | 1993-06-15 | Lsi Logic Corporation | System for simultaneous, interactive presentation of electronic circuit diagrams and simulation data |
US5790435A (en) * | 1991-11-12 | 1998-08-04 | Chronology Corporation | Automated development of timing diagrams for electrical circuits |
US5587919A (en) * | 1994-04-22 | 1996-12-24 | Lucent Technologies, Inc. | Apparatus and method for logic optimization by redundancy addition and removal |
US5636372A (en) * | 1994-09-30 | 1997-06-03 | International Business Machines Corporation | Network timing analysis method which eliminates timing variations between signals traversing a common circuit path |
US6209123B1 (en) * | 1996-11-01 | 2001-03-27 | Motorola, Inc. | Methods of placing transistors in a circuit layout and semiconductor device with automatically placed transistors |
US6643683B1 (en) * | 2000-05-08 | 2003-11-04 | International Business Machines Corporation | Interactive client-server environment for performing collaborative timing analysis of circuit designs |
US20020013933A1 (en) * | 2000-05-26 | 2002-01-31 | Nec Corporation | Graphic data conversion method and its apparatus |
US20040153988A1 (en) * | 2000-10-03 | 2004-08-05 | Fujitsu Limited | Placement/net wiring processing system |
US20050262463A1 (en) * | 2001-02-12 | 2005-11-24 | Cohn John M | Wiring optimizations for power |
US20030229865A1 (en) * | 2002-06-11 | 2003-12-11 | Sergei Bakarian | Method for eliminating false failures saved by redundant paths during circuit area analysis on an integrated circuit layout |
US20040205681A1 (en) * | 2003-01-16 | 2004-10-14 | Yasuyuki Nozuyama | Calculation system of fault coverage and calculation method of the same |
US20050066297A1 (en) * | 2003-09-18 | 2005-03-24 | Kerim Kalafala | System and method for correlated process pessimism removal for static timing analysis |
US7117466B2 (en) * | 2003-09-18 | 2006-10-03 | International Business Machines Corporation | System and method for correlated process pessimism removal for static timing analysis |
US20060259885A1 (en) * | 2004-08-09 | 2006-11-16 | Mortensen Michael P | System and method for analyzing a circuit |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060090147A1 (en) * | 2004-10-19 | 2006-04-27 | Sharp Kabushiki Kaisha | Inspection method and inspection apparatus for semiconductor integrated circuit |
US7404158B2 (en) * | 2004-10-19 | 2008-07-22 | Sharp Kabushiki Kaisha | Inspection method and inspection apparatus for semiconductor integrated circuit |
US20100064264A1 (en) * | 2008-09-10 | 2010-03-11 | International Business Machines Corporation | Method to graphically identify registers with unbalanced slack as part of placement driven synthesis optimization |
US7895544B2 (en) * | 2008-09-10 | 2011-02-22 | International Business Machines Corporation | Method to graphically identify registers with unbalanced slack as part of placement driven synthesis optimization |
US20160188774A1 (en) * | 2009-01-30 | 2016-06-30 | Synopsys, Inc. | Circuit Design and Optimization |
US8082535B1 (en) * | 2009-02-03 | 2011-12-20 | Xilinx, Inc. | Method and apparatus for testing programmable integrated circuits |
CN102156771A (en) * | 2011-01-20 | 2011-08-17 | 北京中星微电子有限公司 | Method and device for generating data path according to bit value |
US9405871B1 (en) * | 2014-12-05 | 2016-08-02 | Xilinx, Inc. | Determination of path delays in circuit designs |
CN108280191A (en) * | 2018-01-25 | 2018-07-13 | 北京工商大学 | The comparison visual analysis method and system of more areas MRL standards |
US10846453B1 (en) * | 2018-09-20 | 2020-11-24 | Synopsys, Inc. | Generating interrelated path groups by using machine learning |
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US7356793B2 (en) | 2008-04-08 |
US20080066036A1 (en) | 2008-03-13 |
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