US20050264320A1 - Logic circuits having linear and cellular gate transistors - Google Patents
Logic circuits having linear and cellular gate transistors Download PDFInfo
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- US20050264320A1 US20050264320A1 US10/709,784 US70978404A US2005264320A1 US 20050264320 A1 US20050264320 A1 US 20050264320A1 US 70978404 A US70978404 A US 70978404A US 2005264320 A1 US2005264320 A1 US 2005264320A1
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- inverter
- logic circuit
- capacitive load
- gate transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
- H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
Definitions
- the present invention relates to logic circuits. More particularly, the present invention relates to logic circuits having linear and cellular gate transistors.
- MOS complementary metal oxide silicone
- Such logic circuits commonly require two or more inverters connected in series.
- buffer circuits, oscillator circuits, digital circuits, memory circuits, and other logic circuits require two or more serial inverters.
- More complex logic circuits also use two or more inverters connected in series, but further expand the circuit to combine inverters in a partially series, partially parallel structure.
- Inverters typically include a P-channel type MOS transistor (PMOS) and an N-channel type MOS transistor (NMOS).
- PMOS P-channel type MOS transistor
- NMOS N-channel type MOS transistor
- the design of the transistor can have an effect of the time delay of the logic circuit, the area or size of the circuit, and the current drive required by the circuit.
- the commercial success of many electronic consumer devices having such logic circuits can be dependent on, among other factors, the size, speed, and battery usage rate of the device.
- a logic circuit having two or more inverters in series with one another, where one of the inverters drives a smaller load than the other inverter.
- the inverter driving the smaller load has a plurality of linear gate transistors, while the inverter driving the larger load has a plurality of cellular gate transistors.
- a logic circuit is provided with a first inverter having a plurality of linear gate transistors driving a first capacitive load and a second inverter having a plurality of cellular gate transistors driving a second capacitive load.
- the first inverter is serially connected to the second inverter.
- the second capacitive load is larger than the first capacitive load.
- a logic circuit is also provided with a first inverter having a plurality of linear gate transistors with a first input capacitance and a second inverter having a plurality of cellular gate transistors with a second input capacitance.
- the first inverter is connected in series to the second inverter.
- the second input capacitance is at least about one and one-half times larger than the first input capacitance.
- a logic circuit is provided with a first inverter having a plurality of linear gate transistors with a first drain capacitance and a second inverter having a plurality of cellular gate transistors with a second drain capacitance.
- the first inverter is connected in series to the second inverter.
- the second drain capacitance is at least about one and one-half times larger than the first drain capacitance.
- FIG. 1 is a schematic view of a first prior art inverter having linear gate transistors
- FIGS. 2 and 3 are schematic views of a second prior art inverter having cellular gate transistors
- FIG. 4 is a graph according to the present invention illustrating the time delay per threshold voltage of the transistors of FIGS. 1, 2 , and 3 ;
- FIG. 5 is a graph according to the present invention illustrating the time delay per current of the transistors of FIGS. 1, 2 , and 3 ;
- FIG. 6 is an exemplary embodiment of a logic circuit according to the present invention having linear and cellular gate transistors.
- First inverter 10 has a PMOS transistor 12 and an NMOS transistor 14 .
- Transistors 12 , 14 have a plurality of source regions 16 , a plurality of drain regions 18 , and one or more linearly disposed gate structures 20 .
- Source and drain regions 16 , 18 are formed in alternating rows.
- first inverter 10 is illustrated having two source regions 16 and one center drain region 18 .
- First inverter 10 includes only one metal source interconnect (not shown) to properly bias source regions 16 and only one metal drain interconnect (not shown) to properly bias drain regions 18 .
- Linear gate transistors 12 , 14 having linearly disposed gates structures 20 are referred to herein as “linear gate transistors”. In linear gate transistors 12 , 14 , carriers flow from each source region 16 to one drain region 18 under gate structures 20 .
- Second inverter 22 has a PMOS transistor 24 and an NMOS transistor 26 .
- Transistors 24 , 26 have a plurality of source regions 28 , a plurality of drain regions 30 , and one or more intersecting gate structures 32 .
- Source and drain regions 28 , 30 are formed in a checker board pattern, of alternating columns and rows.
- Second inverter 22 includes only one metal source interconnect 34 to properly bias source regions 28 and one metal drain interconnect 36 to properly bias drain regions 30 .
- Transistors 24 , 26 having intersecting gates structures 32 are referred to herein as “cellular gate transistors”.
- intersecting gate structures 32 define a plurality of cell-shaped areas about each source and drain region 28 , 30 .
- intersecting gate structures 32 are a plurality of intersecting horizontal and vertical conductors, which together define a plurality of square-shaped cells defined around source and drain regions 28 , 30 .
- intersecting gate structures 32 it is contemplated by the present invention for intersecting gate structures 32 to define other non-square shapes, such as, but not limited to, a diamond shape, a rectangular shape, a triangular shape, an octagonal shape, and other polygonal shapes.
- the cellular gate transistors 24 , 26 of FIG. 2 include three columns of source and drain regions 28 , 30 , while the cellular gate transistors of FIG. 3 include four columns of source and drain regions.
- carriers flow from source regions 28 to drain regions 30 under gates 32 .
- each source region 28 is in electrical communication with two or more drain regions 30 due to the checker pattern of the source and drain regions and the intersecting gates 32 .
- the time delay of the first inverter 10 of FIG. 1 was compared to that of second inverters 22 of FIGS. 2 and 3 , where the inverters all had similar layout areas.
- the ring delay in picoseconds per stage at different threshold voltages is shown in FIG. 4 .
- the ring delay in picoseconds per stage at different currents is shown in FIG. 5 .
- second inverters 22 have a longer delay (i.e., slower) as compared to first inverter 10 .
- second inverters 22 provide higher total drive current as compared to first inverter 10 .
- cellular gate transistors 24 , 26 provide between about 20% to about 80% higher drive current, more particularly about 55% higher drive current than linear gate transistors 12 , 14 . It can also be seen from FIG. 4 that cellular gate transistors 24 , 26 have a delay that is about 15% slower than linear gate transistors 12 , 14 . Since the delay is equal to the capacitance times the voltage divided by the current, it was found that second inverters 22 have about 1.5 to about 3 times higher load capacitance than similar sized first inverter 10 .
- logic circuit 40 taking advantage of the above data is illustrated in FIG. 6 .
- logic circuit 40 is illustrated as a buffer circuit.
- logic circuit 40 combines one or more first inverters 10 having linear gate transistors 12 , 14 with one or more second inverters 22 having cellular gate transistors 24 , 26 .
- logic circuit 40 is configured so that the delay time is minimized.
- C load is the load capacitance of the circuit
- Cg is the input capacitance
- Cd is the drain capacitance
- N the number of inverter stages
- T total is the total delay time
- T 0 is the initial time delay
- T total ( N + 1 ) ⁇ T o ⁇ ( Cd + kCg ) ( Cd + Cg ) ( Equation ⁇ ⁇ 2 )
- T total ln ⁇ ( Cl / Cg ) ( ln ⁇ ⁇ k ) ⁇ T o ⁇ ⁇ ( Cd + kCg ) ( Cd + Cg ) ( Equation ⁇ ⁇ 3 )
- Cd is about 1.5 to about 2 times higher than for the linear gate transistors as estimated based on the layout area of the logic circuit
- Cg is about 1.5 to about 3 times higher than the linear gate transistors as estimated based on the layout area of the logic circuit.
- C load remains 50 pF.
- the number of inverter stages i.e., N
- the constant scale factor i.e., k
- logic circuit 40 takes unique advantage of the benefits of cellular and liner gate transistors to improve the function of the logic circuit.
- logic circuit 40 has two or more inverters in series with one another, where one of the inverters drives a smaller load than the other inverter.
- the inverter driving the smaller load has linear gate transistors, while the inverter driving the larger load has cellular gate transistors.
Abstract
Description
- The present invention relates to logic circuits. More particularly, the present invention relates to logic circuits having linear and cellular gate transistors.
- The use of complementary metal oxide silicone (MOS) transistors to perform logic functions in digital systems is common. Such logic circuits commonly require two or more inverters connected in series. For example, buffer circuits, oscillator circuits, digital circuits, memory circuits, and other logic circuits require two or more serial inverters. More complex logic circuits also use two or more inverters connected in series, but further expand the circuit to combine inverters in a partially series, partially parallel structure.
- Inverters typically include a P-channel type MOS transistor (PMOS) and an N-channel type MOS transistor (NMOS). The design of the transistor can have an effect of the time delay of the logic circuit, the area or size of the circuit, and the current drive required by the circuit. The commercial success of many electronic consumer devices having such logic circuits can be dependent on, among other factors, the size, speed, and battery usage rate of the device.
- Accordingly, there is a continuing need for logic circuits that are useful to reduce the size of the circuit, reduce the current drive required by the circuit, and/or increase the speed of the circuit as compared to the prior art logic circuits.
- A logic circuit is provided having two or more inverters in series with one another, where one of the inverters drives a smaller load than the other inverter. The inverter driving the smaller load has a plurality of linear gate transistors, while the inverter driving the larger load has a plurality of cellular gate transistors.
- In one embodiment of the present invention, a logic circuit is provided with a first inverter having a plurality of linear gate transistors driving a first capacitive load and a second inverter having a plurality of cellular gate transistors driving a second capacitive load. The first inverter is serially connected to the second inverter. The second capacitive load is larger than the first capacitive load.
- A logic circuit is also provided with a first inverter having a plurality of linear gate transistors with a first input capacitance and a second inverter having a plurality of cellular gate transistors with a second input capacitance. The first inverter is connected in series to the second inverter. The second input capacitance is at least about one and one-half times larger than the first input capacitance.
- In a further embodiment, a logic circuit is provided with a first inverter having a plurality of linear gate transistors with a first drain capacitance and a second inverter having a plurality of cellular gate transistors with a second drain capacitance. The first inverter is connected in series to the second inverter. The second drain capacitance is at least about one and one-half times larger than the first drain capacitance.
- The above-described and other features and advantages of the present invention will be appreciated and understood by those skilled in the art from the following detailed description, drawings, and appended claims.
-
FIG. 1 is a schematic view of a first prior art inverter having linear gate transistors; -
FIGS. 2 and 3 are schematic views of a second prior art inverter having cellular gate transistors; -
FIG. 4 is a graph according to the present invention illustrating the time delay per threshold voltage of the transistors ofFIGS. 1, 2 , and 3; -
FIG. 5 is a graph according to the present invention illustrating the time delay per current of the transistors ofFIGS. 1, 2 , and 3; and -
FIG. 6 is an exemplary embodiment of a logic circuit according to the present invention having linear and cellular gate transistors. - Referring now to the drawings, and in particular to
FIG. 1 a first type of prior art inverter is illustrated by way ofreference numeral 10.First inverter 10 has aPMOS transistor 12 and anNMOS transistor 14.Transistors source regions 16, a plurality ofdrain regions 18, and one or more linearly disposedgate structures 20. Source anddrain regions first inverter 10 is illustrated having twosource regions 16 and onecenter drain region 18.First inverter 10 includes only one metal source interconnect (not shown) to properly biassource regions 16 and only one metal drain interconnect (not shown) to properly biasdrain regions 18. -
Transistors gates structures 20 are referred to herein as “linear gate transistors”. Inlinear gate transistors source region 16 to onedrain region 18 undergate structures 20. - In
FIGS. 2 and 3 , a second type of prior art inverter is illustrated by way ofreference numeral 22.Second inverter 22 has aPMOS transistor 24 and anNMOS transistor 26.Transistors source regions 28, a plurality ofdrain regions 30, and one or more intersectinggate structures 32. Source anddrain regions Second inverter 22 includes only one metal source interconnect 34 to properly biassource regions 28 and one metal drain interconnect 36 to properly biasdrain regions 30. -
Transistors gates structures 32 are referred to herein as “cellular gate transistors”. Specifically, intersectinggate structures 32 define a plurality of cell-shaped areas about each source anddrain region gate structures 32 are a plurality of intersecting horizontal and vertical conductors, which together define a plurality of square-shaped cells defined around source anddrain regions gate structures 32 to define other non-square shapes, such as, but not limited to, a diamond shape, a rectangular shape, a triangular shape, an octagonal shape, and other polygonal shapes. - The
cellular gate transistors FIG. 2 include three columns of source anddrain regions FIG. 3 include four columns of source and drain regions. In each embodiment, carriers flow fromsource regions 28 to drainregions 30 undergates 32. However, eachsource region 28 is in electrical communication with two or moredrain regions 30 due to the checker pattern of the source and drain regions and the intersectinggates 32. - The time delay of the
first inverter 10 ofFIG. 1 was compared to that ofsecond inverters 22 ofFIGS. 2 and 3 , where the inverters all had similar layout areas. The ring delay in picoseconds per stage at different threshold voltages is shown inFIG. 4 . Further, the ring delay in picoseconds per stage at different currents is shown inFIG. 5 . - From the data of
FIG. 4 , it was determined thatsecond inverters 22 have a longer delay (i.e., slower) as compared tofirst inverter 10. However, it was determined from the data ofFIG. 5 thatsecond inverters 22 provide higher total drive current as compared tofirst inverter 10. - Importantly, it was determined that the speed decrease and the high current in
second inverters 22 are due to the extra capacitance available from thecellular gate transistors cellular gate transistors linear gate transistors FIG. 4 thatcellular gate transistors linear gate transistors second inverters 22 have about 1.5 to about 3 times higher load capacitance than similar sizedfirst inverter 10. - An exemplary embodiment of a
logic circuit 40 taking advantage of the above data is illustrated inFIG. 6 . In this embodiment,logic circuit 40 is illustrated as a buffer circuit. Advantageously,logic circuit 40 combines one or morefirst inverters 10 havinglinear gate transistors second inverters 22 havingcellular gate transistors logic circuit 40 is configured so that the delay time is minimized. - By way of example, the steps for configuring
logic circuit 40 to minimize the delay time is illustrated below in comparison to conventional (e.g., having only first inverter 10). During design of conventional buffer circuits, Cload is the load capacitance of the circuit, Cg is the input capacitance, Cd is the drain capacitance, N the number of inverter stages, Ttotal is the total delay time, T0 is the initial time delay, and k is the constant scale factor for the inverters in the chain. It can be assumed that the load capacitance of the circuit is as follows:
C load =k N+1 Cg (Equation 1) - Where the total delay time from the input terminal to the load capacitance node is defined by:
- By combining Equations 1 and 2, it can be seen that:
- To minimize the delay, the total delay divided by the scale factor can be set to zero such that:
Delta(T total)/Delta(k)=0 (Equation 4) - By combining Equations 3 and 4, it can be seen that:
- The solution to Equation 5 results in:
k(ln k−1)=Cd/Cg (Equation 6) - Assuming for the conventional buffer circuit that Cd=5 fF (femto Farads), Cg=10 fF (femto Farads), and Cload=50 pF (pico Farads), k=3.18 and N=6.36. Since N is the number of inverters, this value is rounded up to the largest whole number, namely 7.
- In contrast, for
logic circuit 40 having first andsecond inverters logic circuit 40 having first andsecond inverters - Accordingly,
logic circuit 40 takes unique advantage of the benefits of cellular and liner gate transistors to improve the function of the logic circuit. Here,logic circuit 40 has two or more inverters in series with one another, where one of the inverters drives a smaller load than the other inverter. The inverter driving the smaller load has linear gate transistors, while the inverter driving the larger load has cellular gate transistors. - In addition, it should be noted that the terms “first”, “second”, “third”, “upper”, “lower”, and the like may be used herein to modify various elements. These modifiers do not imply a spatial, sequential, or hierarchical order to the modified elements unless specifically stated.
- While the present invention has been described with reference to one or more exemplary embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the scope thereof. Therefore, it is intended that the present invention not be limited to the particular embodiment(s) disclosed as the best mode contemplated, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (19)
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