US20050161757A1 - Wafer level hermetic sealing method - Google Patents

Wafer level hermetic sealing method Download PDF

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Publication number
US20050161757A1
US20050161757A1 US11/087,552 US8755205A US2005161757A1 US 20050161757 A1 US20050161757 A1 US 20050161757A1 US 8755205 A US8755205 A US 8755205A US 2005161757 A1 US2005161757 A1 US 2005161757A1
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Prior art keywords
wafer
hermetic seal
adhesives
wafer level
level hermetic
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US11/087,552
Inventor
Chang-Ho Cho
Hyung-jae Shin
Woon-bae Kim
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority to US11/087,552 priority Critical patent/US20050161757A1/en
Publication of US20050161757A1 publication Critical patent/US20050161757A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/0077—Other packages not provided for in groups B81B7/0035 - B81B7/0074
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00269—Bonding of solid lids or wafers to the substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00349—Creating layers of material on a substrate
    • B81C1/00357—Creating layers of material on a substrate involving bonding one or several substrates on a non-temporary support, e.g. another substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
    • B81C2201/019—Bonding or gluing multiple substrate layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip

Definitions

  • the present invention relates to a semiconductor device with a wafer level hermetic seal and a method of hermetically sealing a device at the wafer level. More particularly, the present invention relates to a method of hermetically sealing a semiconductor device which is at a wafer level where the device sensitive to high temperatures or affected by a heat cycle can be thermally sealed at a low temperature and is not affected by moisture or particles.
  • the surfaces of a conventional semiconductor devices are first micro-machined in order to hermetically seal the devices.
  • the surface micro-machining is a method by which a sacrificial layer is formed, a structure is formed thereon, and then the sacrificial layer is removed, thereby forming a moving structure.
  • structures or semiconductor devices are formed on a wafer (not shown) in a state in which the sacrificial layer (also not shown) is not removed (S 201 ).
  • a first anti-stiction film is coated on the wafer (S 207 ) to prevent dust or particles from attaching to the moving structures. This coating also protects the moving structures during the physical moving, handling and testing of the devices.
  • the anti-stiction film is a film that prevents dust or particles from being attached to a surface by lowering the surface energy of the surface.
  • each individual device is tested according to a first test (S 210 ). Since the unit cost of a packaging process is high, this first test is necessarily performed to seek high quality devices. The atmosphere where the first test is carried out must be adjusted so that there is almost no moisture therein. By adjusting the atmosphere, high quality devices can be prevented from being transformed into low quality ones during the testing process. The wafer is sawed into individual chips after the testing is completed (S 213 ). Here, a high percentage of the chips become defective due to the particles generated during the sawing process. The equipment used in a general semiconductor process cannot be used during the sawing process, while additional equipment for fabricating devices such as MEMS is required. This results in an increase in the production cost.
  • Each individual chip 105 is attached to a package 100 by a die adhesive 103 (S 215 ) and electrically connected to the package 100 by a wire-bonding process 118 (S 217 ).
  • the chip is exposed to the outside environment, and moisture or particles can attach to the chip if the anti-stiction film becomes contaminated. Therefore, a cleaning process is performed to remove such particles (S 220 ).
  • a second anti-stiction film coating is necessarily required because the first anti-stiction film may also be removed during the cleaning process (S 223 ). Even if the first anti-stiction film is not removed during the cleaning process, surfaces of the chip with prolonged exposure to air will absorb the moisture, making the second anti-stiction film coating necessary.
  • the package containing the chip is now also coated with the second anti-stiction film.
  • the lid 115 is aligned with the package 100 , which is coated with the second anti-stiction film, and hermetically sealed with a seal ring 110 (S 225 ).
  • reference numeral 113 represents a lid frame.
  • performing the hermetic sealing process in a chip state is costly as well as labor and time intensive.
  • An increase in cost is attributable to additional equipment needed to carefully handle the MEMS devices or chips having moving structures.
  • maintaining a multiple work environment such as two anti-stiction coating lines and two testing lines is also costly, and labor and time intensive.
  • the second anti-stiction film is coated on every package before sealing. This process is slow because the area of the package to be coated is large, thereby requiring a large amount of time to coat the anti-stiction film.
  • the method of hermetically sealing the package 100 and the lid 115 includes welding and glass high temperature splicing.
  • the lid frame 113 is attached to the lid 115 while the seal ring 110 is placed in-between the package 100 and the lid 115 .
  • the lid 115 along with the seal ring 110 is attached to the package 100 by welding.
  • a high-priced ceramic or metal is used to ensure the hermetic state.
  • a wafer level bonding method includes silicon-silicon fusion bonding, silicon-glass anodic bonding, eutectic bonding using a medium such as Au, and bonding using a glass frit. In these methods, the cleanness of a surface to be sealed is very important and high temperature or pressure is required.
  • a wafer level hermetic sealing method In the method, semiconductor devices are formed on a wafer. A lid wafer is formed. Adhesives are formed in a predetermined position over the wafer and/or the lid wafer. The wafer and the lid wafer are sealed together by the adhesives. The sealed wafer-level devices are diced into an individual wafer level chip.
  • the adhesives are formed of one of In, Sn, Ag, Pb, Zn, Au, Bi, Sb, Cd, Ga and Cu, or an alloy of two or more of these metals.
  • the adhesives are formed of a material having a fusion point of 100 ⁇ 300° C.
  • the adhesives are formed by deposition or sputtering.
  • adhesive promoters are formed over the wafer and/or the lid wafer to promote adhesion of the adhesives.
  • the adhesives and the adhesive promoters are disposed to align the wafer with the lid wafer.
  • the adhesive promoters are formed of metal or polymer.
  • Electrical connectors may be formed on the wafer to transceive an electrical signal.
  • a hole may be formed in a predetermined position so that the electrical connectors are electrically connected to the outside via an interconnection line passing through the hole.
  • FIG. 1 is a cross-sectional view of semiconductor chip packaged according to a conventional sealing method
  • FIG. 2 is a flowchart showing the conventional sealing method
  • FIGS. 3A through 3E are drawings describing semiconductor device(s) with a wafer level hermetic seal and/or method of hermetically sealing device(s) at a wafer level according to the present invention.
  • FIG. 4 is a flowchart showing the method of hermetically sealing device(s) at a wafer level according to the present invention.
  • semiconductor devices are formed at a wafer level, additional lids are also formed at a wafer level, and the semiconductor devices and the lids are sealed at a low temperature using an adhesive.
  • semiconductor devices 12 are formed on a wafer 10 .
  • Electrical connectors 15 for electrical connection with the outside may be formed.
  • a lid wafer 30 for transceiving an optical signal is prepared apart from the wafer 10 .
  • Adhesives 35 are formed to bond the wafer 10 and the lid wafer 30 together.
  • the lid wafer 30 may be formed of transparent materials such as glass in order to exchange an optical signal with the outside.
  • the adhesives 35 are formed on the lid wafer 30 but may be formed on the wafer 10 .
  • the adhesives 35 may use solder, metal, or organic sealant, may have a preformed shape, and may be deposited by deposition or sputtering.
  • adhesive promoters 20 and 33 may be further formed over the wafer 10 and/or the lid wafer 30 to promote adhesion of the adhesives 35 before the adhesives 35 are formed.
  • the adhesive promoters 20 and 33 may be formed of metal or polymer.
  • the adhesives 35 and the adhesive promoters 20 and 33 are formed so as to align the wafer 10 with the lid wafer 30 , thereby easily and accurately sealing semiconductor devices at a wafer level.
  • an electrically connective hole 37 may be formed through the lid wafer 30 in order to ensure space necessary for the electrical connection to the electrical connectors 15 .
  • the electrically connective hole 37 is used as a space for an interconnection line when portions of the electrical connectors 15 exposed outside are electrically connected to the outside via an interconnection line.
  • the wafer 10 aligns with the lid wafer 30 on the basis of the adhesives 35 and the adhesive promoters 20 and 33 after the wafer 10 and the lid wafer 30 are formed, and the wafer 10 and the lid wafer 30 are sealed under a suitable atmosphere.
  • the wafer 10 and the lid wafer 30 are sealed, cavities 40 are formed therebetween.
  • a low temperature sealing process is possible if a solder is used as an adhesive in the sealing process.
  • the solder is preferably formed of one of In, Sn, Ag, Pb, Zn, Au, Bi, Sb, Cd, Ga and Cu, or an alloy of two or more of these metals.
  • the solder is formed of a material having a fusion point of 100 ⁇ 300° C., more preferably, 100 ⁇ 200° C.
  • the material includes BiSnPb, BiPbSn, BiSnCd, Biln, BiPbSnCd, BiSnPbCdCu, InCd, BiPb, InSn, InSnPbCd, BiPb, PbBiSn, BiSnInPb, InSnPb, BiPbSnAg, InAg, BiCd, InGa, PbBi, SnAg, InPb, SnZn, SnPbBi, SnPbSb, AuSn, and SnCu and the like.
  • devices sealed at a wafer level are sawed into individual chips 45 .
  • dust, particles, or moisture may not stick to the semiconductor device 12 sealed within the individual chip 45 during the sawing process.
  • FIG. 4 shows a flowchart of the wafer level sealing process as described above.
  • Individual semiconductor devices 12 are formed on the wafer 10 (S 1 ).
  • a lid wafer 30 is formed apart from the wafer 10 and adhesives 35 are formed in a predetermined position to bond the wafer 10 and the lid wafer 30 (S 2 ).
  • the wafer 10 and the lid wafer 30 are sealed together using the adhesives 35 (S 4 ).
  • the devices formed at a wafer level are diced into individual chips (S 5 ).
  • an operation S 3 of forming an electrically connective hole 37 may be further included when the lid wafer 30 is formed in order to ensure a space necessary for an electrical connection.
  • the wafer level hermetic sealing method according to the present invention can be applied to MEMS devices or chips whose lives are shortened by a stiction phenomenon due to moisture or particles, charged coupled devices (CCD) and sensors requiring the minimization of high temperature, moisture, gas by-products, or particles. Also, the wafer level hermetic sealing method can be applied to general semiconductor devices and hybrid chips for optical communication.
  • CCD charged coupled devices
  • sealing is performed at a wafer level and thus the overall required processing time is reduced. It is easier to handle MEMS devices or chips having the moving structures and production cost is reduced due to the use of existing dicing processes. Also, in the present invention, sealing is performed right after the moving structures are formed. Testing the device and attaching the device to a package are performed in a sealed state. Therefore, detrimental effects due to dust, particles or moisture generated during the testing process can be excluded.
  • the hermetic sealing process can be performed at a low temperature using a solder and thus it can be applied to semiconductor devices sensitive to heat.

Abstract

A device that is hermetically sealed at a wafer level or a method of hermetically sealing a device, which is sensitive to high temperatures or affected by heating cycles. Semiconductor devices are formed on a wafer. A lid wafer is formed. Adhesives are formed in a predetermined position over the wafer and/or the lid wafer. The wafer and the lid wafer are sealed by the adhesives at the wafer level. The sealing may be performed at a low temperature using a solder to protect the devices sensitive to heat. The sealed devices are diced into individual chips. In the wafer level hermetic sealing method, a sawing operation is performed after the devices are sealed. Therefore, the overall processing time is reduced, devices are protected from the effects of moisture or particles, and devices having a moving structure, such as MEMS devices, are more easily handled.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application is a divisional of application Ser. No. 09/984,734 filed on Oct. 31, 2001, now pending, the content of which is incorporated by reference herein.
  • This application claims the benefit of Korean Application No. 2001-5256, filed Feb. 3, 2001, in the Korean Industrial Property Office, the disclosure of which is incorporated by reference herein.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a semiconductor device with a wafer level hermetic seal and a method of hermetically sealing a device at the wafer level. More particularly, the present invention relates to a method of hermetically sealing a semiconductor device which is at a wafer level where the device sensitive to high temperatures or affected by a heat cycle can be thermally sealed at a low temperature and is not affected by moisture or particles.
  • 2. Description of the Related Art
  • Referring to FIGS. 1 and 2, the surfaces of a conventional semiconductor devices, such as MicroElectroMechanical Systems (MEMS), are first micro-machined in order to hermetically seal the devices. The surface micro-machining is a method by which a sacrificial layer is formed, a structure is formed thereon, and then the sacrificial layer is removed, thereby forming a moving structure. In the case where the surface micro-machining is used, structures or semiconductor devices are formed on a wafer (not shown) in a state in which the sacrificial layer (also not shown) is not removed (S201). Then the wafer is sawed in half (S203) and the sacrificial layer is etched to form moving structures (S205). The resulting moving structures must be carefully handled because these structures can be damaged or rendered completely inoperative by a single microscopic particle. Thus, a first anti-stiction film is coated on the wafer (S207) to prevent dust or particles from attaching to the moving structures. This coating also protects the moving structures during the physical moving, handling and testing of the devices. The anti-stiction film is a film that prevents dust or particles from being attached to a surface by lowering the surface energy of the surface.
  • After the first anti-stiction film coating, each individual device is tested according to a first test (S210). Since the unit cost of a packaging process is high, this first test is necessarily performed to seek high quality devices. The atmosphere where the first test is carried out must be adjusted so that there is almost no moisture therein. By adjusting the atmosphere, high quality devices can be prevented from being transformed into low quality ones during the testing process. The wafer is sawed into individual chips after the testing is completed (S213). Here, a high percentage of the chips become defective due to the particles generated during the sawing process. The equipment used in a general semiconductor process cannot be used during the sawing process, while additional equipment for fabricating devices such as MEMS is required. This results in an increase in the production cost.
  • Each individual chip 105 is attached to a package 100 by a die adhesive 103 (S215) and electrically connected to the package 100 by a wire-bonding process 118 (S217). Here, the chip is exposed to the outside environment, and moisture or particles can attach to the chip if the anti-stiction film becomes contaminated. Therefore, a cleaning process is performed to remove such particles (S220). However, a second anti-stiction film coating is necessarily required because the first anti-stiction film may also be removed during the cleaning process (S223). Even if the first anti-stiction film is not removed during the cleaning process, surfaces of the chip with prolonged exposure to air will absorb the moisture, making the second anti-stiction film coating necessary. The package containing the chip is now also coated with the second anti-stiction film.
  • The lid 115 is aligned with the package 100, which is coated with the second anti-stiction film, and hermetically sealed with a seal ring 110 (S225). Here, reference numeral 113 represents a lid frame. By-products, moisture, and particles are generated when the chip 105 is first tested in an unsealed state and then attached to the package 100. These factors can damage the device or make the device completely inoperable. Therefore, a second test is performed after the seal (S227).
  • As described above, performing the hermetic sealing process in a chip state is costly as well as labor and time intensive. An increase in cost is attributable to additional equipment needed to carefully handle the MEMS devices or chips having moving structures. In addition, maintaining a multiple work environment such as two anti-stiction coating lines and two testing lines is also costly, and labor and time intensive. In particular, the second anti-stiction film is coated on every package before sealing. This process is slow because the area of the package to be coated is large, thereby requiring a large amount of time to coat the anti-stiction film.
  • The method of hermetically sealing the package 100 and the lid 115 includes welding and glass high temperature splicing. In a typical welding process, the lid frame 113 is attached to the lid 115 while the seal ring 110 is placed in-between the package 100 and the lid 115. Then the lid 115 along with the seal ring 110 is attached to the package 100 by welding. Here, a high-priced ceramic or metal is used to ensure the hermetic state.
  • A wafer level bonding method includes silicon-silicon fusion bonding, silicon-glass anodic bonding, eutectic bonding using a medium such as Au, and bonding using a glass frit. In these methods, the cleanness of a surface to be sealed is very important and high temperature or pressure is required.
  • Accordingly, these methods are not appropriate for devices such as MEMS, which use aluminum actuators having a relatively low fusion temperature. In the case of a silicon-glass anodic bonding method, bonding is performed at a relatively low temperature of about 450□C. However, even a temperature of about 450□C. is too high for aluminum actuators and high pressure, which may negatively affect the device, is required.
    • SUMMARY OF THE INVENTION
  • To solve the above mentioned problems, it is an object of the present invention to provide a semiconductor device or chip with a wafer level hermetic seal and/or a wafer level hermetic sealing method by which semiconductor device(s) can be sealed at a wafer level so as not to be affected by moisture or particles, and at a low temperature so as to be appropriate for devices such as MEMS structures, which are sensitive to high temperature.
  • Additional objects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
  • Accordingly, to achieve the above and other objects, there is provided a wafer level hermetic sealing method. In the method, semiconductor devices are formed on a wafer. A lid wafer is formed. Adhesives are formed in a predetermined position over the wafer and/or the lid wafer. The wafer and the lid wafer are sealed together by the adhesives. The sealed wafer-level devices are diced into an individual wafer level chip.
  • The adhesives are formed of one of In, Sn, Ag, Pb, Zn, Au, Bi, Sb, Cd, Ga and Cu, or an alloy of two or more of these metals. The adhesives are formed of a material having a fusion point of 100˜300° C. The adhesives are formed by deposition or sputtering. In the operation of forming the adhesives, adhesive promoters are formed over the wafer and/or the lid wafer to promote adhesion of the adhesives. In the operation of forming the adhesive promoters, the adhesives and the adhesive promoters are disposed to align the wafer with the lid wafer. The adhesive promoters are formed of metal or polymer. Electrical connectors may be formed on the wafer to transceive an electrical signal. In the operation of forming the lid wafer, a hole may be formed in a predetermined position so that the electrical connectors are electrically connected to the outside via an interconnection line passing through the hole.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above object and advantages of the present invention will become more apparent by describing in detail a preferred embodiment thereof with reference to the attached drawings in which:
  • FIG. 1 is a cross-sectional view of semiconductor chip packaged according to a conventional sealing method;
  • FIG. 2 is a flowchart showing the conventional sealing method;
  • FIGS. 3A through 3E are drawings describing semiconductor device(s) with a wafer level hermetic seal and/or method of hermetically sealing device(s) at a wafer level according to the present invention; and
  • FIG. 4 is a flowchart showing the method of hermetically sealing device(s) at a wafer level according to the present invention.
    • DESCRIPTION OF THE PREFERRED EMBODIMENT
  • Reference will now be made in detail to the present preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below in order to explain the present invention by referring to the figures.
  • Referring to FIGS. 3A through 3E, in the wafer level sealing method of the present invention, semiconductor devices are formed at a wafer level, additional lids are also formed at a wafer level, and the semiconductor devices and the lids are sealed at a low temperature using an adhesive.
  • As shown in FIG. 3A, semiconductor devices 12 are formed on a wafer 10. Electrical connectors 15 for electrical connection with the outside may be formed.
  • As shown in FIG. 3B, a lid wafer 30 for transceiving an optical signal is prepared apart from the wafer 10. Adhesives 35 are formed to bond the wafer 10 and the lid wafer 30 together. The lid wafer 30 may be formed of transparent materials such as glass in order to exchange an optical signal with the outside. Here, the adhesives 35 are formed on the lid wafer 30 but may be formed on the wafer 10. The adhesives 35 may use solder, metal, or organic sealant, may have a preformed shape, and may be deposited by deposition or sputtering.
  • Also, adhesive promoters 20 and 33 may be further formed over the wafer 10 and/or the lid wafer 30 to promote adhesion of the adhesives 35 before the adhesives 35 are formed. Here, the adhesive promoters 20 and 33 may be formed of metal or polymer. Particularly, the adhesives 35 and the adhesive promoters 20 and 33 are formed so as to align the wafer 10 with the lid wafer 30, thereby easily and accurately sealing semiconductor devices at a wafer level.
  • Meanwhile, as shown in FIGS. 3C through 3D, an electrically connective hole 37 may be formed through the lid wafer 30 in order to ensure space necessary for the electrical connection to the electrical connectors 15. In other words, the electrically connective hole 37 is used as a space for an interconnection line when portions of the electrical connectors 15 exposed outside are electrically connected to the outside via an interconnection line.
  • As described above, the wafer 10 aligns with the lid wafer 30 on the basis of the adhesives 35 and the adhesive promoters 20 and 33 after the wafer 10 and the lid wafer 30 are formed, and the wafer 10 and the lid wafer 30 are sealed under a suitable atmosphere. Here, when the wafer 10 and the lid wafer 30 are sealed, cavities 40 are formed therebetween. A low temperature sealing process is possible if a solder is used as an adhesive in the sealing process. Here, the solder is preferably formed of one of In, Sn, Ag, Pb, Zn, Au, Bi, Sb, Cd, Ga and Cu, or an alloy of two or more of these metals. Particularly, the solder is formed of a material having a fusion point of 100˜300° C., more preferably, 100˜200° C. For example, the material includes BiSnPb, BiPbSn, BiSnCd, Biln, BiPbSnCd, BiSnPbCdCu, InCd, BiPb, InSn, InSnPbCd, BiPb, PbBiSn, BiSnInPb, InSnPb, BiPbSnAg, InAg, BiCd, InGa, PbBi, SnAg, InPb, SnZn, SnPbBi, SnPbSb, AuSn, and SnCu and the like.
  • After the sealing process is completed, as shown in FIG. 3E, devices sealed at a wafer level are sawed into individual chips 45. Here, dust, particles, or moisture may not stick to the semiconductor device 12 sealed within the individual chip 45 during the sawing process.
  • FIG. 4 shows a flowchart of the wafer level sealing process as described above. Individual semiconductor devices 12 are formed on the wafer 10 (S1). A lid wafer 30 is formed apart from the wafer 10 and adhesives 35 are formed in a predetermined position to bond the wafer 10 and the lid wafer 30 (S2). The wafer 10 and the lid wafer 30 are sealed together using the adhesives 35 (S4). The devices formed at a wafer level are diced into individual chips (S5). Here, an operation S3 of forming an electrically connective hole 37 may be further included when the lid wafer 30 is formed in order to ensure a space necessary for an electrical connection.
  • The wafer level hermetic sealing method according to the present invention can be applied to MEMS devices or chips whose lives are shortened by a stiction phenomenon due to moisture or particles, charged coupled devices (CCD) and sensors requiring the minimization of high temperature, moisture, gas by-products, or particles. Also, the wafer level hermetic sealing method can be applied to general semiconductor devices and hybrid chips for optical communication.
  • As described above, in the wafer level hermetic sealing method according to the present invention, sealing is performed at a wafer level and thus the overall required processing time is reduced. It is easier to handle MEMS devices or chips having the moving structures and production cost is reduced due to the use of existing dicing processes. Also, in the present invention, sealing is performed right after the moving structures are formed. Testing the device and attaching the device to a package are performed in a sealed state. Therefore, detrimental effects due to dust, particles or moisture generated during the testing process can be excluded.
  • Also, the hermetic sealing process can be performed at a low temperature using a solder and thus it can be applied to semiconductor devices sensitive to heat.
  • Although a few preferred embodiments of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes may be made in this embodiment without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.

Claims (20)

1. An apparatus with a wafer level hermetic seal comprising:
a wafer;
a semiconductor device formed on a device side of the wafer;
a lid wafer with a front side facing the device side of the wafer; and
adhesives which adhere the device side of the wafer and the front side of the lid wafer in a predetermined position, wherein the adhesives seal the device in between the device side of the wafer and the front side of the lid wafer.
2. The apparatus with the wafer level hermetic seal of claim 1, wherein the adhesives are formed of one selected from the group consisting of In, Sn, Ag, Pb, Zn, Au, Bi, Sb, Cd, Ga and Cu, or an alloy of two or more of these metals.
3. The apparatus with the wafer level hermetic seal of claim 2, wherein the adhesives are formed of a material having a fusion point of 100˜300° C.
4. The apparatus with the wafer level hermetic seal of claim 2, wherein the adhesives are formed by deposition or sputtering.
5. The apparatus with the wafer level hermetic seal of claim 2, further comprising adhesive promoters formed over the device side of the wafer and/or the front side of the lid wafer to promote adhesion of the adhesives.
6. The apparatus with the wafer level hermetic seal of claim 5, wherein the adhesives and the adhesive promoters are disposed to align the wafer with the lid wafer.
7. The apparatus with the wafer level hermetic seal of claim 5, wherein the adhesive promoters are formed of metal or polymer.
8. The apparatus with the wafer level hermetic seal of claim 2, wherein electrical connectors are formed on the wafer to transceive an electrical signal.
9. The apparatus with the wafer level hermetic seal of claim 8, wherein the lid wafer comprises a through hole so that the electrical connectors are electrically connected to the outside via an interconnection line passing through the hole.
10. The apparatus with the wafer level hermetic seal of claim 2, wherein the adhesives have a preformed shape.
11. The apparatus with the wafer level hermetic seal of claim 2, wherein the lid wafer formed is a transparent material to exchange an optical signal.
12. The apparatus with the wafer level hermetic seal of claim 1, wherein the adhesives are formed of a material having a fusion point of 100˜300° C.
13. The apparatus with the wafer level hermetic seal of claim 1, further comprising adhesive promoters formed over the device side of the wafer and/or the front side of the lid wafer to promote adhesion of the adhesives.
14. The apparatus with the wafer level hermetic seal of claim 13, wherein the adhesives and the adhesive promoters are disposed to align the wafer with the lid wafer.
15. The apparatus with the wafer level hermetic seal of claim 13, wherein the adhesive promoters are formed of metal or polymer.
16. The apparatus with the wafer level hermetic seal of claim 1, wherein electrical connectors are formed on the wafer to transceive an electrical signal.
17. The apparatus with the wafer level hermetic seal of claim 16, wherein the lid wafer comprises a through hole so that the electrical connectors are electrically connected to the outside via an interconnection line passing through the hole.
18. The apparatus with the wafer level hermetic seal of claim 1, wherein the adhesives have a performed shape.
19. The apparatus with the wafer level hermetic seal of claim 1, wherein the lid wafer formed is a transparent material to exchange an optical signal.
20. The apparatus with the wafer level hermetic seal of claim 1, wherein the adhesives are formed of an organic sealant.
US11/087,552 2001-02-03 2005-03-24 Wafer level hermetic sealing method Abandoned US20050161757A1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8395837B2 (en) * 2003-11-13 2013-03-12 Texas Instruments Incorporated Releasing and post-releasing processes in fabrications for micromirror array devices
CN104979299A (en) * 2015-06-08 2015-10-14 南通富士通微电子股份有限公司 Device packaging structure of micro electro mechanical system and packaging method of device packaging structure
CN109292726A (en) * 2018-08-17 2019-02-01 北方电子研究院安徽有限公司 A kind of total silicon is environmentally isolated MEMS device

Families Citing this family (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100400218B1 (en) * 2000-08-18 2003-10-30 삼성전자주식회사 micro-actuator and manufacturing method therof
US7127362B2 (en) * 2000-08-22 2006-10-24 Mundt Randall S Process tolerant methods and apparatus for obtaining data
US7345316B2 (en) * 2000-10-25 2008-03-18 Shipley Company, L.L.C. Wafer level packaging for optoelectronic devices
US6932519B2 (en) 2000-11-16 2005-08-23 Shipley Company, L.L.C. Optical device package
US6827503B2 (en) * 2000-12-01 2004-12-07 Shipley Company, L.L.C. Optical device package having a configured frame
US6883977B2 (en) * 2000-12-14 2005-04-26 Shipley Company, L.L.C. Optical device package for flip-chip mounting
US6844236B2 (en) * 2001-07-23 2005-01-18 Agere Systems Inc. Method and structure for DC and RF shielding of integrated circuits
US7832177B2 (en) 2002-03-22 2010-11-16 Electronics Packaging Solutions, Inc. Insulated glazing units
US20060191215A1 (en) * 2002-03-22 2006-08-31 Stark David H Insulated glazing units and methods
US6962834B2 (en) * 2002-03-22 2005-11-08 Stark David H Wafer-level hermetic micro-device packages
JP2004296453A (en) * 2003-02-06 2004-10-21 Sharp Corp Solid-state imaging device, semiconductor wafer, optical device module, method of manufacturing the solid-state imaging device, and method of manufacturing the optical device module
DE10308860B4 (en) * 2003-02-27 2007-09-06 X-Fab Semiconductor Foundries Ag Method for separating semiconductor wafers with exposed micromechanical structures into chips
US6888233B2 (en) * 2003-03-10 2005-05-03 Honeywell International Inc. Systems for buried electrical feedthroughs in a glass-silicon MEMS process
US6987304B2 (en) * 2003-05-07 2006-01-17 Honeywell International Inc. Methods and apparatus for particle reduction in MEMS devices
TWI275168B (en) * 2003-06-06 2007-03-01 Sanyo Electric Co Semiconductor device and method for making the same
JP2005056998A (en) * 2003-08-01 2005-03-03 Fuji Photo Film Co Ltd Solid-state image pickup device and its manufacturing method
JP4551638B2 (en) * 2003-08-01 2010-09-29 富士フイルム株式会社 Method for manufacturing solid-state imaging device
EP1515364B1 (en) * 2003-09-15 2016-04-13 Nuvotronics, LLC Device package and methods for the fabrication and testing thereof
US6934065B2 (en) * 2003-09-18 2005-08-23 Micron Technology, Inc. Microelectronic devices and methods for packaging microelectronic devices
US6774327B1 (en) * 2003-09-24 2004-08-10 Agilent Technologies, Inc. Hermetic seals for electronic components
JP4259979B2 (en) 2003-10-22 2009-04-30 新光電気工業株式会社 Light transmissive cover, device provided with the same, and manufacturing method thereof
US7583862B2 (en) * 2003-11-26 2009-09-01 Aptina Imaging Corporation Packaged microelectronic imagers and methods of packaging microelectronic imagers
US7692292B2 (en) * 2003-12-05 2010-04-06 Panasonic Corporation Packaged electronic element and method of producing electronic element package
US7291513B2 (en) * 2003-12-15 2007-11-06 Dalsa Semiconductor Inc. Hermetic wafer-level packaging for MEMS devices with low-temperature metallurgy
US6946728B2 (en) * 2004-02-19 2005-09-20 Hewlett-Packard Development Company, L.P. System and methods for hermetic sealing of post media-filled MEMS package
US7253397B2 (en) * 2004-02-23 2007-08-07 Micron Technology, Inc. Packaged microelectronic imagers and methods of packaging microelectronic imagers
DE102004013816A1 (en) * 2004-03-20 2005-10-06 Robert Bosch Gmbh Method for producing a sensor module and sensor module
TWI284398B (en) * 2004-03-26 2007-07-21 Xintec Inc Chip package structure and its wafer level package method
KR100575363B1 (en) * 2004-04-13 2006-05-03 재단법인서울대학교산학협력재단 Method of packaging of mems device at the vacuum state and vacuum packaged mems device using the same
US7253957B2 (en) * 2004-05-13 2007-08-07 Micron Technology, Inc. Integrated optics units and methods of manufacturing integrated optics units for use with microelectronic imagers
US20050253283A1 (en) * 2004-05-13 2005-11-17 Dcamp Jon B Getter deposition for vacuum packaging
US8092734B2 (en) * 2004-05-13 2012-01-10 Aptina Imaging Corporation Covers for microelectronic imagers and methods for wafer-level packaging of microelectronics imagers
US20050275750A1 (en) * 2004-06-09 2005-12-15 Salman Akram Wafer-level packaged microelectronic imagers and processes for wafer-level packaging
US7498647B2 (en) * 2004-06-10 2009-03-03 Micron Technology, Inc. Packaged microelectronic imagers and methods of packaging microelectronic imagers
US7262405B2 (en) * 2004-06-14 2007-08-28 Micron Technology, Inc. Prefabricated housings for microelectronic imagers
US7199439B2 (en) * 2004-06-14 2007-04-03 Micron Technology, Inc. Microelectronic imagers and methods of packaging microelectronic imagers
US7294897B2 (en) * 2004-06-29 2007-11-13 Micron Technology, Inc. Packaged microelectronic imagers and methods of packaging microelectronic imagers
US7232754B2 (en) 2004-06-29 2007-06-19 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
US7416913B2 (en) * 2004-07-16 2008-08-26 Micron Technology, Inc. Methods of manufacturing microelectronic imaging units with discrete standoffs
US7189954B2 (en) * 2004-07-19 2007-03-13 Micron Technology, Inc. Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers
US7402453B2 (en) * 2004-07-28 2008-07-22 Micron Technology, Inc. Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US20060023107A1 (en) * 2004-08-02 2006-02-02 Bolken Todd O Microelectronic imagers with optics supports having threadless interfaces and methods for manufacturing such microelectronic imagers
US7364934B2 (en) * 2004-08-10 2008-04-29 Micron Technology, Inc. Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US7397066B2 (en) * 2004-08-19 2008-07-08 Micron Technology, Inc. Microelectronic imagers with curved image sensors and methods for manufacturing microelectronic imagers
US7223626B2 (en) * 2004-08-19 2007-05-29 Micron Technology, Inc. Spacers for packaged microelectronic imagers and methods of making and using spacers for wafer-level packaging of imagers
US7115961B2 (en) * 2004-08-24 2006-10-03 Micron Technology, Inc. Packaged microelectronic imaging devices and methods of packaging microelectronic imaging devices
US7429494B2 (en) 2004-08-24 2008-09-30 Micron Technology, Inc. Microelectronic imagers with optical devices having integral reference features and methods for manufacturing such microelectronic imagers
US7276393B2 (en) * 2004-08-26 2007-10-02 Micron Technology, Inc. Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US7511262B2 (en) * 2004-08-30 2009-03-31 Micron Technology, Inc. Optical device and assembly for use with imaging dies, and wafer-label imager assembly
US20070148807A1 (en) * 2005-08-22 2007-06-28 Salman Akram Microelectronic imagers with integrated optical devices and methods for manufacturing such microelectronic imagers
US7646075B2 (en) * 2004-08-31 2010-01-12 Micron Technology, Inc. Microelectronic imagers having front side contacts
US7300857B2 (en) * 2004-09-02 2007-11-27 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
JP2006173557A (en) * 2004-11-22 2006-06-29 Toshiba Corp Hollow type semiconductor apparatus and its manufacture
US7271482B2 (en) * 2004-12-30 2007-09-18 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US7214919B2 (en) * 2005-02-08 2007-05-08 Micron Technology, Inc. Microelectronic imaging units and methods of manufacturing microelectronic imaging units
FR2881847A1 (en) * 2005-02-10 2006-08-11 St Microelectronics Sa Optical device for e.g. mobile telephone, has auto focus camera module with optical chip having microprocessor to process, based on image signals from image sensor, control signal applied to focussing units to ensure auto focus of objective
US7303931B2 (en) * 2005-02-10 2007-12-04 Micron Technology, Inc. Microfeature workpieces having microlenses and methods of forming microlenses on microfeature workpieces
US20060177999A1 (en) * 2005-02-10 2006-08-10 Micron Technology, Inc. Microelectronic workpieces and methods for forming interconnects in microelectronic workpieces
US7190039B2 (en) * 2005-02-18 2007-03-13 Micron Technology, Inc. Microelectronic imagers with shaped image sensors and methods for manufacturing microelectronic imagers
DE102005016751B3 (en) * 2005-04-11 2006-12-14 Schott Ag Method for producing packaged electronic components
US7228177B2 (en) * 2005-04-26 2007-06-05 Medtronic, Inc. Chip level biostable interconnect for implantable medical devices
WO2006124597A2 (en) * 2005-05-12 2006-11-23 Foster Ron B Infinitely stackable interconnect device and method
US7795134B2 (en) * 2005-06-28 2010-09-14 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US20060290001A1 (en) * 2005-06-28 2006-12-28 Micron Technology, Inc. Interconnect vias and associated methods of formation
JP2007027279A (en) 2005-07-13 2007-02-01 Shinko Electric Ind Co Ltd Semiconductor device and manufacturing method thereof
US7417307B2 (en) * 2005-07-29 2008-08-26 Hewlett-Packard Development Company, L.P. System and method for direct-bonding of substrates
US7262134B2 (en) 2005-09-01 2007-08-28 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7288757B2 (en) * 2005-09-01 2007-10-30 Micron Technology, Inc. Microelectronic imaging devices and associated methods for attaching transmissive elements
US20070114643A1 (en) * 2005-11-22 2007-05-24 Honeywell International Inc. Mems flip-chip packaging
US7491567B2 (en) * 2005-11-22 2009-02-17 Honeywell International Inc. MEMS device packaging methods
DE102006019080B3 (en) * 2006-04-25 2007-08-30 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Housing manufacturing method for e.g. infrared sensor, involves enclosing electrical circuit along metal frame, where circuit is isolated along isolating contour that does not cut surface of substrate
JP5026038B2 (en) * 2006-09-22 2012-09-12 新光電気工業株式会社 Electronic component equipment
US7528420B2 (en) * 2007-05-23 2009-05-05 Visera Technologies Company Limited Image sensing devices and methods for fabricating the same
US7563646B2 (en) * 2007-05-31 2009-07-21 Stratedge Corporation Molded ceramic surface mount package
WO2009036359A1 (en) * 2007-09-14 2009-03-19 Electronics Packaging Solutions, Inc. Insulating glass unit having multi-height internal standoffs and visible decoration
US7605466B2 (en) * 2007-10-15 2009-10-20 General Electric Company Sealed wafer packaging of microelectromechanical systems
KR100908648B1 (en) * 2007-10-19 2009-07-21 (주)에스엠엘전자 Bump structure with multiple layers and method of manufacture
KR100848364B1 (en) * 2007-12-24 2008-07-25 코아셈(주) Package for device and packaging method thereof
US8283023B2 (en) 2008-08-09 2012-10-09 Eversealed Windows, Inc. Asymmetrical flexible edge seal for vacuum insulating glass
WO2010083476A2 (en) 2009-01-15 2010-07-22 Eversealed Windows, Inc Flexible edge seal for vacuum insulating glazing unit
WO2010083475A2 (en) 2009-01-15 2010-07-22 Eversealed Windows, Inc. Filament-strung stand-off elements for maintaining pane separation in vacuum insulating glazing units
US20100194465A1 (en) * 2009-02-02 2010-08-05 Ali Salih Temperature compensated current source and method therefor
KR100941446B1 (en) * 2009-03-03 2010-02-11 주식회사 바른전자 Bump structure with multiple layers and method of manufacture
DE102009042479A1 (en) * 2009-09-24 2011-03-31 Msg Lithoglas Ag Method for producing an arrangement having a component on a carrier substrate and arrangement, and method for producing a semifinished product and semifinished product
EP2576950A4 (en) 2010-06-02 2017-07-05 Eversealed Windows, Inc. Multi-pane glass unit having seal with adhesive and hermetic coating layer
US8674495B2 (en) * 2010-10-08 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having a eutectic bonding material and manufacturing methods thereof
EP2455332B1 (en) * 2010-11-19 2014-02-12 Imec Method for producing temporary cap on a MEMS device
US8486758B2 (en) 2010-12-20 2013-07-16 Tessera, Inc. Simultaneous wafer bonding and interconnect joining
US9328512B2 (en) 2011-05-05 2016-05-03 Eversealed Windows, Inc. Method and apparatus for an insulating glazing unit and compliant seal for an insulating glazing unit
US20120288996A1 (en) * 2011-05-12 2012-11-15 Too Seah S Methods and apparatus for applying an adhesive to a circuit board
US20130341747A1 (en) * 2012-06-20 2013-12-26 Xintec Inc. Chip package and method for forming the same
US9162878B2 (en) * 2012-08-30 2015-10-20 Innovative Micro Technology Wafer level hermetic bond using metal alloy with raised feature and wetting layer
KR101581542B1 (en) * 2014-04-24 2015-12-30 주식회사 스탠딩에그 Cap substrate, structure, and method of manufacturing the same
US10541152B2 (en) 2014-07-31 2020-01-21 Skyworks Solutions, Inc. Transient liquid phase material bonding and sealing structures and methods of forming same
TWI661494B (en) 2014-07-31 2019-06-01 美商西凱渥資訊處理科技公司 Multilayered transient liquid phase bonding
US10965269B2 (en) 2016-12-02 2021-03-30 Skyworks Solutions, Inc. Electronic devices formed in a cavity between substrates and including a via
US10319654B1 (en) 2017-12-01 2019-06-11 Cubic Corporation Integrated chip scale packages
US10607857B2 (en) 2017-12-06 2020-03-31 Indium Corporation Semiconductor device assembly including a thermal interface bond between a semiconductor die and a passive heat exchanger
CN111943129B (en) * 2019-05-16 2024-01-30 芯恩（青岛）集成电路有限公司 MEMS wafer cutting alignment method and MEMS wafer

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4824511A (en) * 1987-10-19 1989-04-25 E. I. Du Pont De Nemours And Company Multilayer circuit board with fluoropolymer interlayers
US5534725A (en) * 1992-06-16 1996-07-09 Goldstar Electron Co., Ltd. Resin molded charge coupled device package and method for preparation thereof
US6255741B1 (en) * 1998-03-17 2001-07-03 Denso Corporation Semiconductor device with a protective sheet to affix a semiconductor chip
US6265246B1 (en) * 1999-07-23 2001-07-24 Agilent Technologies, Inc. Microcap wafer-level package
US6297072B1 (en) * 1998-04-17 2001-10-02 Interuniversitair Micro-Elktronica Centrum (Imec Vzw) Method of fabrication of a microstructure having an internal cavity
US6303986B1 (en) * 1998-07-29 2001-10-16 Silicon Light Machines Method of and apparatus for sealing an hermetic lid to a semiconductor die
US6441481B1 (en) * 2000-04-10 2002-08-27 Analog Devices, Inc. Hermetically sealed microstructure package
US20020171131A1 (en) * 1999-10-26 2002-11-21 Heidi L. Denton Component and method for manufacture

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5917270A (en) * 1982-07-21 1984-01-28 Hitachi Ltd Semiconductor device
US5448014A (en) * 1993-01-27 1995-09-05 Trw Inc. Mass simultaneous sealing and electrical connection of electronic devices
JP3507251B2 (en) * 1995-09-01 2004-03-15 キヤノン株式会社 Optical sensor IC package and method of assembling the same
US5945735A (en) * 1997-01-31 1999-08-31 International Business Machines Corporation Hermetic sealing of a substrate of high thermal conductivity using an interposer of low thermal conductivity
JP2976917B2 (en) * 1997-03-31 1999-11-10 日本電気株式会社 Semiconductor device
US5881945A (en) * 1997-04-30 1999-03-16 International Business Machines Corporation Multi-layer solder seal band for semiconductor substrates and process
EP1041628A3 (en) 1999-03-29 2008-05-28 Interuniversitair Microelektronica Centrum Vzw An image sensor ball grid array package and the fabrication thereof
JP3408987B2 (en) * 1999-03-30 2003-05-19 三菱電機株式会社 Semiconductor device manufacturing method and semiconductor device
JP3567793B2 (en) 1999-04-27 2004-09-22 オムロン株式会社 Method for manufacturing semiconductor device
US6452238B1 (en) * 1999-10-04 2002-09-17 Texas Instruments Incorporated MEMS wafer level package
US6602740B1 (en) * 1999-11-24 2003-08-05 Tessera, Inc. Encapsulation of microelectronic assemblies
WO2002074686A2 (en) * 2000-12-05 2002-09-26 Analog Devices, Inc. A method and device for protecting micro electromechanical systems structures during dicing of a wafer

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4824511A (en) * 1987-10-19 1989-04-25 E. I. Du Pont De Nemours And Company Multilayer circuit board with fluoropolymer interlayers
US5534725A (en) * 1992-06-16 1996-07-09 Goldstar Electron Co., Ltd. Resin molded charge coupled device package and method for preparation thereof
US6255741B1 (en) * 1998-03-17 2001-07-03 Denso Corporation Semiconductor device with a protective sheet to affix a semiconductor chip
US6297072B1 (en) * 1998-04-17 2001-10-02 Interuniversitair Micro-Elktronica Centrum (Imec Vzw) Method of fabrication of a microstructure having an internal cavity
US6303986B1 (en) * 1998-07-29 2001-10-16 Silicon Light Machines Method of and apparatus for sealing an hermetic lid to a semiconductor die
US6265246B1 (en) * 1999-07-23 2001-07-24 Agilent Technologies, Inc. Microcap wafer-level package
US20020171131A1 (en) * 1999-10-26 2002-11-21 Heidi L. Denton Component and method for manufacture
US6441481B1 (en) * 2000-04-10 2002-08-27 Analog Devices, Inc. Hermetically sealed microstructure package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8395837B2 (en) * 2003-11-13 2013-03-12 Texas Instruments Incorporated Releasing and post-releasing processes in fabrications for micromirror array devices
CN104979299A (en) * 2015-06-08 2015-10-14 南通富士通微电子股份有限公司 Device packaging structure of micro electro mechanical system and packaging method of device packaging structure
CN109292726A (en) * 2018-08-17 2019-02-01 北方电子研究院安徽有限公司 A kind of total silicon is environmentally isolated MEMS device

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KR100396551B1 (en) 2003-09-03

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