US20050135134A1 - Ternary content addressable memory (tcam) cells with small footprint size and efficient layout aspect ratio - Google Patents
Ternary content addressable memory (tcam) cells with small footprint size and efficient layout aspect ratio Download PDFInfo
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- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
- G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
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- the present invention relates to integrated circuit memory devices and, more particularly, to content addressable memory (CAM) devices.
- CAM content addressable memory
- RAM random access memory
- data is typically accessed by supplying an address to an array of memory cells and then reading data from the memory cells that reside at the supplied address.
- data e.g., search words
- data within a CAM array is not accessed by initially supplying an address, but rather by initially applying data (e.g., search words) to the array and then performing a search operation to identify one or more entries within the CAM array that contain data equivalent to the applied data and thereby represent a “match” condition. In this manner, data is accessed according to its content rather than its address.
- the identified location(s) containing the equivalent data is typically encoded to provide an address (e.g., block address+row address within a block) at which the matching entry is located.
- an address e.g., block address+row address within a block
- local priority encoding operations may be performed to identify a location of a best or highest priority matching entry. Such priority encoding operations frequently utilize the relative physical locations of multiple matching entries within the CAM array to identify a highest priority matching entry.
- the cells within a CAM array are frequently configured as binary CAM cells that store only data bits (as “1” or “0” logic values) or as ternary (or quaternary) CAM cells that store data bits and mask bits.
- binary CAM cells that store only data bits (as “1” or “0” logic values)
- ternary (or quaternary) CAM cells that store data bits and mask bits.
- the ternary CAM cell may operate as a conventional binary CAM cell storing an “unmasked” data bit.
- the ternary CAM cell When the mask bit is active (e.g., set to a logic 0 value), the ternary CAM cell is treated as storing a “don't care” (X) value, which means that all compare operations performed on the actively masked ternary CAM cell will result in a cell match condition.
- X don't care
- a compare operation will yield one or more match conditions whenever all the unmasked data bits of an entry in the ternary CAM array are identical to the corresponding data bits of the applied search word.
- the applied search word equals ⁇ 1011 ⁇
- the following entries will result in a match condition in a CAM comprising ternary CAM cells: ⁇ 1011 ⁇ , ⁇ X011 ⁇ , ⁇ 1X11 ⁇ , ⁇ 10X1 ⁇ , ⁇ 101X ⁇ , ⁇ XX11 ⁇ , ⁇ 1XX1 ⁇ , . . .
- CAM cells may use a variety of different memory cell technologies, including volatile SRAM and DRAM technologies and nonvolatile memory technologies. CAM cells based on these technologies are disclosed in U.S. Pat. Nos. 6,101,116, 6,128,207, 6,256,216, 6,266,263, 6,373,739 and 6,496,399, assigned to the present assignee, the disclosures of which are hereby incorporated herein by reference. In addition, U.S. Pat. No. 6,522,562 to Foss, entitled “Content Addressable Memory Cell Having Improved Layout,” discloses a CAM cell that uses p-channel transistors as SRAM access transistors.
- FIG. 4 of the '562 patent illustrates a CAM half-cell that includes a 6T SRAM cell defined by two PMOS access transistors P 3 and P 4 , two PMOS pull-up transistors P 1 and P 2 and two NMOS pull-down transistors N 1 and N 2 .
- One half of a 4T compare circuit is also illustrated as including two NMOS transistors N 3 and N 4 .
- PMOS transistors typically have lower mobility relative to equivalently-sized NMOS transistors
- using PMOS transistors as access transistors within an SRAM cell may require relatively large PMOS transistors that increase overall unit cell size.
- FIG. 5 of U.S. Pat. No. 6,188,594 to Ong entitled “Reduced-Pitch 6-Transistor NMOS Content-Addressable-Memory Cell,” discloses a 6T CAM cell having a non-unity layout aspect ratio.
- Embodiments of the present invention include ternary CAM cells having extremely small layout footprint size and efficient layout aspect ratios that enhance scalability and uniformity of wiring pitch.
- the ternary CAM cells also have high degrees of symmetry that facilitate extensive sharing of vias between transistor-equivalent half-cells. These shared vias provide electrical interconnects between terminals of the CAM cell transistors and bit, data and match lines. Accordingly, when the CAM half-cells are joined together on all four sides to form a large CAM array, a low per cell via count can be achieved.
- First embodiments of the present invention include a 16T SRAM-based ternary CAM cell that extends in a semiconductor substrate and has a substantially square layout aspect ratio.
- the CAM cell includes first and second pairs of access transistors that extend adjacent a first side of the ternary CAM cell, and first and second pairs of cross-coupled inverters that extend adjacent a second side of the ternary CAM cell.
- First and second halves of a 4T compare circuit are also provided. The first half of the 4T compare circuit is positioned so that is extends between the first pair of access transistors and the first pair of cross-coupled inverters. Similarly, the second half of the 4T compare circuit is positioned so that it extends between the second pair of access transistors and the second pair of cross-coupled inverters.
- the first pair of cross-coupled inverters include a first inverter having a first PMOS pull-up transistor and a first NMOS pull-down transistor therein, and a second inverter having a second PMOS pull-up transistor and a second NMOS pull-down transistor therein.
- the first and second NMOS pull-down transistors are positioned so that they extend between the first and second PMOS pull-up transistors (on one side) and the first half of the 4T compare circuit (on an opposite side).
- the second pair of cross-coupled inverters include a second pair of PMOS pull-up transistors and a second pair of NMOS pull-down transistors, which extend between the second pair of PMOS pull-up transistors and the second half of the 4T compare circuit.
- the first and second pairs of access transistors are equivalently-sized NMOS transistors having a first width/length (W/L) ratio and the 4T compare circuit comprises four equivalently-sized NMOS transistors having a second width/length ratio that is greater than the first width/length ratio.
- the first width/length ratio is less than about 1.15 and the second width/length ratio is greater than about 1.15. More preferably, the first width/length ratio is about 1.04 and the second width/length ratio is about 1.25.
- the first pair of cross-coupled inverters comprises two equivalently-sized NMOS pull-down transistors having a third width/length ratio and two equivalently-sized PMOS pull-up transistors having a fourth width/length ratio that is less than the third width/length ratio.
- the third width/length ratio is greater than about 1.5 and the fourth width/length ratio is less than about 1.25. More preferably, the third width/length ratio is about 1.8 and the fourth width/length ratio is about 1.0.
- a width/height aspect ratio of the ternary CAM cell is approximately square.
- the width/height aspect ratio may be in a range from between about 1.08 and about 1.20.
- High density layouts can also be achieved by placing and orienting the MOS transistors of a CAM cell in orthogonal x and y directions that achieve a high packing density.
- a ternary CAM cell can be achieved having a footprint in a range from between about 3.0 ⁇ m 2 and about 3.6 ⁇ m 2 .
- Ternary CAM cells include a first pair of NMOS access transistors having source and drain regions that are arranged in a y-direction in a first quadrant of the ternary CAM cell.
- a second pair of NMOS access transistors are also provided in a second quadrant of the ternary CAM cell and their source and drain regions are also arranged in the y-direction.
- the ternary CAM cell also includes first and second pairs of cross-coupled inverters that are positioned in fourth and third quadrants, respectively.
- the first pair of cross-coupled inverters comprises two PMOS pull-up transistors and two NMOS pull-down transistors that are arranged in an x-direction, which is orthogonal to the y-direction.
- the second pair of cross-coupled inverters comprises two PMOS pull-up transistors and two NMOS pull-down transistors that are arranged in the x-direction.
- the ternary CAM cell also includes a 4T compare circuit that is divided into two halves. A first half of the 4T compare circuit is positioned between the first pair of access transistors and the first pair of cross-coupled inverters, and comprises two NMOS transistors that are arranged in the x-direction. Similarly, the second half of the 4T compare circuit is positioned between the second pair of access transistors and the second pair of cross-coupled inverters, and comprises two NMOS transistors arranged in the x-direction.
- FIG. 1A is an electrical schematic of a ternary CAM cell according to an embodiment of the present invention.
- FIG. 1B is a layout schematic of the ternary CAM cell of FIG. 1A .
- the left-to-right and top-to-bottom orientation of the MOS transistors in the layout schematic match the orientation of the MOS transistors in the electrical schematic of FIG. 1A .
- FIG. 1C is an electrical schematic of a ternary CAM cell that is similar to the embodiment of FIG. 1A , however, a pseudo-ground (PGND) connection is provided.
- PGND pseudo-ground
- FIG. 1D is a layout schematic of the ternary CAM cell of FIG. 1B , with layout aspect ratio and transistor size information provided.
- FIG. 1E is a layout schematic of the ternary CAM cells of FIGS. 1B and 1D , with dotted lines that show the positions of various transistors within four quadrants of a substantially square CAM cell.
- FIG. 1F is a separated layout view of four half-cells with half-via and quarter-via patterns illustrated.
- the ternary CAM cell 10 A represents a sixteen transistor (16T) ternary CAM cell having two SRAM cells and a four transistor (4T) compare circuit therein.
- Each SRAM cell includes two access transistors and one pair of cross-coupled inverters that operate as a storage element.
- a left half of the ternary CAM cell 10 A is illustrated. This left half includes an X-SRAM storage element that generates an X output, which is provided to a left half of the 4T compare circuit.
- the X-SRAM storage element is defined by a first inverter, which consists of PMOS pull-up transistor P 1 and NMOS pull-down transistor N 1 , and a second inverter, which consists of PMOS pull-up transistor P 2 and NMOS pull-down transistor N 2 .
- the input of the first inverter is designated by the label X and the input of the second inverter is designated by the complementary label XB.
- the input X of the first inverter is electrically connected to a first current carrying terminal of an NMOS access transistor N 10 .
- This first current carrying terminal of the NMOS access transistor N 10 is illustrated as a drain terminal.
- the NMOS access transistor N 10 has a gate terminal that is responsive to a word line signal WL and a second current carrying terminal that is responsive to a true bit line signal (shown as BX).
- the input XB of the second inverter is electrically connected to a first current carrying terminal of an NMOS access transistor N 9 .
- the NMOS access transistor N 9 has a gate terminal that is responsive to the word line signal WL and a second current carrying terminal that is responsive to a complementary bit line signal (shown as BXB).
- NMOS transistors N 5 and N 6 are connected in series (i.e., source-to-drain) between a match line (ML) and a ground reference line (Vss).
- NMOS transistor N 5 is configured to receive the signal X, which is the output of the second inverter defined by PMOS pull-up transistor P 2 and NMOS pull-down transistor N 2 .
- NMOS transistor N 6 is configured to receive a true data signal (shown as D), which represents the true bit of a comparand that is applied to the ternary CAM cell 10 A during a search operation.
- the right half of the ternary CAM cell 10 A includes a Y-SRAM storage element that generates an output to a right half of the 4T compare circuit.
- the Y-SRAM storage element is defined by a third inverter, which consists of PMOS pull-up transistor P 3 and NMOS pull-down transistor N 3 , and a fourth inverter, which consists of PMOS pull-up transistor P 4 and NMOS pull-down transistor N 4 .
- the input of the fourth inverter is designated by the label Y and the input of the third inverter is designated by the label YB.
- the input Y of the fourth inverter is electrically connected to a first current carrying terminal of NMOS access transistor N 12 .
- the NMOS access transistor N 12 has a gate terminal that is responsive to the word line signal WL and a second current carrying terminal that is responsive to a true bit line signal (shown as BY).
- the input YB of the third inverter is electrically connected to a first current carrying terminal of NMOS access transistor N 11 .
- the NMOS access transistor N 11 has a gate terminal that is responsive to the word line signal WL and a second current carrying terminal that is responsive to a complementary bit line signal (shown as BYB).
- BYB complementary bit line signal
- the right half of the 4T compare circuit is defined by NMOS transistors N 7 and N 8 , which are connected in series (i.e., source-to-drain) between a match line (ML) and a ground reference line (Vss).
- NMOS transistor N 8 is configured to receive the signal Y, which is the output of the third inverter defined by PMOS pull-up transistor P 3 and NMOS pull-down transistor N 3 .
- NMOS transistor N 7 is configured to receive a complementary data signal (shown as DB), which represents the complementary bit of the aforementioned comparand.
- the ternary CAM cell 10 A is configured to support three valid states in accordance with TABLE 1: TABLE 1 X Y STATE 0 0 MASK 0 1 0 1 0 1 1 1 INVALID
- the CAM cell 10 A will support the three valid states illustrated by TABLE 2: TABLE 2 X Y STATE 0 0 MASK 0 1 1 1 0 0 1 1 INVALID
- the electrical schematic of the ternary CAM cell 10 A illustrated by FIG. 1A corresponds to the layout schematic of the ternary CAM cell 10 B illustrated by FIG. 1B .
- the lateral (left-to-right) orientation of PMOS pull-up transistors P 1 -P 4 and NMOS transistors N 1 -N 8 represents the lateral x-direction orientation of the PMOS pull-up transistors P 1 -P 4 and the NMOS transistors N 1 -B 8 illustrated by FIG. 1B .
- the vertical (top-to-bottom) orientation of NMOS access transistors N 9 -N 12 represents the vertical y-direction orientation of the NMOS access transistors N 9 -N 12 illustrated by FIG. 1B .
- the open (i.e., unshaded) polygons in the layout of FIG. 1B represent source/drain diffusion patterns and the shaded polygons represent gate “poly” patterns (i.e., polysilicon patterns).
- the source-to-drain direction (i.e., channel length direction) of the PMOS pull-up transistors P 1 -P 4 and the NMOS transistors N 1 -N 8 corresponds to the x-direction
- the source-to-drain direction of the NMOS access transistors N 9 -N 12 corresponds to the y-direction.
- the gate poly patterns associated with PMOS pull-up transistor P 1 , NMOS pull-down transistor N 1 and NMOS transistor N 5 are joined into one contiguous pattern, to represent a portion of the signal line X in FIG. 1A .
- the contiguous gate poly pattern associated with PMOS pull-up transistor P 2 and NMOS pull-down transistor N 2 represents a portion of the signal line XB in FIG. 1A .
- the contiguous gate poly pattern associated with PMOS pull-up transistor P 3 and NMOS pull-down transistor N 3 represents a portion of the signal line YB in FIG. 1A .
- the contiguous gate poly pattern associated with PMOS pull-up transistor P 4 and NMOS pull-down transistor N 4 represents a portion of the signal line Y in FIG. 1A .
- the gate poly patterns associated with NMOS transistor N 6 and NMOS transistor N 7 represent portions of the true and complementary connections to the true data line D and the complementary data line DB, respectively.
- the single gate poly pattern that extends laterally across the top side of the ternary CAM cell 10 B represents a word line (WL).
- the reference labels BXB, BX, BYB and BY which run along the top side of the ternary CAM cell 10 B, represent the source regions of access transistors that are electrically connected (by vias) to two pairs of differential bit lines.
- the reference labels ML represents the drain regions of two NMOS transistors N 5 and N 8 that are electrically connected (by vias) to a match line (not shown), which is typically formed at a higher level of metallization.
- the reference labels Vss represent the source regions of NMOS transistors N 1 -N 4 and N 6 -N 7 , which are electrically connected (by vias) to a ground reference line.
- FIG. 1C a 16T ternary CAM cell 10 C according to another embodiment of the present invention is illustrated.
- This CAM cell 10 C is essentially identical to the ternary CAM cell 10 A of FIG. 1A , however, the source terminals of NMOS transistors N 6 and N 7 within the 4T compare circuit are connected to a switchable pseudo-ground line (PGND), instead of a fixed ground reference line (Vss).
- PGND switchable pseudo-ground line
- Vss fixed ground reference line
- the layout of the CAM cell of FIGS. 1A-1B includes two half-cells, left and right. These two half-cells have equivalent transistor count and the source/drain diffusion regions of these half-cells are mirror images of each other. As illustrated more fully by FIG. 1F , these half-cells may be replicated side-by-side in an alternating left/right half-cell sequence to form a row of CAM cells (e.g., a ⁇ 80 row). Moreover, the CAM cell 10 D of FIG.
- FIG. 1D also illustrates how the layout of the ternary CAM cells 10 A- 10 D results in a width-to-height layout aspect ratio that is substantially square.
- the width/height aspect ratio be in a range from between about 1.08 and about 1.20 and, more preferably, about 1.14.
- Factors which influence the aspect ratio include the placement, size and orientation of the sixteen transistors within a cell. As described more fully hereinbelow, the placement and orientation is chosen so that the resulting CAM cell has essentially identical left and right half-cells.
- These half-cells may share all ML, Vss and Vdd vias with adjacent half-cells in a same row of a CAM array, and also share all bit line and data line vias (e.g., BXB, BX, BYB, BY, D and DB) with adjoining cells in a same column of the CAM array.
- bit line and data line vias e.g., BXB, BX, BYB, BY, D and DB
- CMOS processes including the NexsysTM 90-nanometer process technology developed by Taiwan Semiconductor Manufacturing Company, Ltd.
- This 90-nanometer process technology supports a core supply voltage (Vdd) ranging from 1.0 Volts to 1.2 Volts with an I/O and analog block supply voltage ranging from 1.8 Volts to 3.3 Volts.
- the sixteen transistors within the ternary CAM cell 10 D are also sized to achieve preferred operating characteristics including high soft-error immunity characteristics.
- a proper balance is also struck between the contribution of each cell to the bit line, data line and match line capacitance and cell speed.
- One significant design consideration is the speed/power tradeoff between the match line pull-down strength of each cell and its contribution to match line capacitance, which is a significant consumer of match line power during search operations.
- the first and second pairs of access transistors are equivalently-sized NMOS transistors and the NMOS transistors within the 4T compare circuit are also equivalently-sized.
- the first and second pairs of access transistors N 9 -N 10 and N 11 -N 12 are equivalently-sized NMOS transistors having a first width/length (W/L) ratio.
- the 4T compare circuit comprises four equivalently-sized NMOS transistors N 5 -N 8 having a second width/length ratio that is greater than the first width/length ratio. It is preferable that the first width/length ratio be less than about 1.15 and the second width/length ratio be greater than about 1.15. More preferably, the first width/length ratio is about 1.04 and the second width/length ratio is about 1.25, as illustrated by FIG. 1D .
- the first and second pairs of cross-coupled inverters are also configured to have equivalently-sized NMOS pull-down transistors N 1 -N 2 and N 3 -N 4 having a third width/length ratio, and equivalently-sized PMOS pull-up transistors P 1 -P 2 and P 3 -P 4 having a fourth width/length ratio.
- the third width/length ratio is greater than the fourth width/length ratio. It is preferable that the third width/length ratio is greater than about 1.5 and the fourth width/length ratio is less than about 1.25. More preferably, the third width/length ratio is about 1.8 and the fourth width/length ratio is about 1.0, as illustrated by FIG. 1D .
- FIG. 1E the layout patterns of the CAM cells 10 B and 10 D illustrated by FIGS. 1B and 1D are shown as being divided into four quadrants, I-IV, which occupy a layout footprint of 3.3 ⁇ m 2 .
- Quadrant I is illustrated as including the right pair of access transistors and the right half of the 4T compare circuit.
- Quadrant II is illustrated as including the left pair of access transistors and the left half of the 4T compare circuit.
- Quadrant IV is illustrated as including two cross-coupled inverters, which define a storage element within an SRAM cell.
- each quadrant of the CAM cell 10 B, 10 D illustrated by FIG. 1E contains an equivalent number of transistors.
- FIG. 1F two pairs of CAM half-cells that are arranged within a row of a CAM array are identified by the reference numeral 10 F. These half-cells are similar to those illustrated by FIG. 1D , however, numerous via connection patterns have been added to highlight the extensive via sharing between adjacent half-cells in both the x and y directions, when the half-cells are joined together to define a two-dimensional array of CAM cells.
- These via connections may illustrate: CO contact holes from first level metallization (M 1 ) to the poly gate patterns or source/drain diffusion patterns, VIA 1 holes connecting the first level metallization to second level metallization (M 2 ) (not shown) or VIA 2 holes connection the second level metallization to third level metallization (not shown).
- NMOS transistors N 6 and N 7 which are illustrated by the reference labels D and DB in FIG. 1B , are illustrated as being connected through CO contact holes to respective first level metallization patterns that have been added to FIG. 1F .
- These first level metallization patterns are shaded in the reverse direction relative to the poly gate patterns.
- the via connections to power supply lines (Vdd), ground reference lines (Vss), match lines (ML), and bit and data lines are positioned along the outer periphery of each half-cell in order to achieve high degrees of via sharing (1 ⁇ 2Via or 1 ⁇ 4Via) between adjacent half-cells in both the x and y directions.
- This high degree of via sharing contributes to a smaller layout footprint having a substantially square aspect ratio.
Abstract
Description
- The present invention relates to integrated circuit memory devices and, more particularly, to content addressable memory (CAM) devices.
- In many memory devices, including random access memory (RAM) devices, data is typically accessed by supplying an address to an array of memory cells and then reading data from the memory cells that reside at the supplied address. However, in content addressable memory (CAM) devices, data within a CAM array is not accessed by initially supplying an address, but rather by initially applying data (e.g., search words) to the array and then performing a search operation to identify one or more entries within the CAM array that contain data equivalent to the applied data and thereby represent a “match” condition. In this manner, data is accessed according to its content rather than its address. Upon completion of the search operation, the identified location(s) containing the equivalent data is typically encoded to provide an address (e.g., block address+row address within a block) at which the matching entry is located. If multiple matching entries are identified in response to the search operation, then local priority encoding operations may be performed to identify a location of a best or highest priority matching entry. Such priority encoding operations frequently utilize the relative physical locations of multiple matching entries within the CAM array to identify a highest priority matching entry.
- The cells within a CAM array are frequently configured as binary CAM cells that store only data bits (as “1” or “0” logic values) or as ternary (or quaternary) CAM cells that store data bits and mask bits. As will be understood by those skilled in the art, when a mask bit within a ternary CAM cell is inactive (e.g., set to a
logic 1 value), the ternary CAM cell may operate as a conventional binary CAM cell storing an “unmasked” data bit. When the mask bit is active (e.g., set to a logic 0 value), the ternary CAM cell is treated as storing a “don't care” (X) value, which means that all compare operations performed on the actively masked ternary CAM cell will result in a cell match condition. Thus, if a logic 0 data bit is applied to a ternary CAM cell storing an active mask bit and alogic 1 data bit, the compare operation will indicate a cell match condition. A cell match condition will also be indicated if alogic 1 data bit is applied to a ternary CAM cell storing an active mask bit and a logic 0 data bit. Accordingly, if a data word of length N, where N is an integer, is applied to a ternary CAM array having a plurality of entries therein of logical width N, then a compare operation will yield one or more match conditions whenever all the unmasked data bits of an entry in the ternary CAM array are identical to the corresponding data bits of the applied search word. This means that if the applied search word equals {1011}, the following entries will result in a match condition in a CAM comprising ternary CAM cells: {1011}, {X011}, {1X11}, {10X1}, {101X}, {XX11}, {1XX1}, . . . , {1XXX}, {XXXX}. A quaternary CAM cell is different from a ternary CAM cell because it has four valid combinations of states: ((data=0, mask=active), (data=1, mask=active), (data=0, mask=inactive), (data=1, mask=inactive)). Quaternary CAM cells are frequently treated as “ternary” CAM cells because two of the four states represent equivalent active mask conditions when search operations are performed. However, ternary CAM (TCAM) cells and quaternary CAM (QCAM) cells will be treated herein as separate categories of CAM cells. - CAM cells may use a variety of different memory cell technologies, including volatile SRAM and DRAM technologies and nonvolatile memory technologies. CAM cells based on these technologies are disclosed in U.S. Pat. Nos. 6,101,116, 6,128,207, 6,256,216, 6,266,263, 6,373,739 and 6,496,399, assigned to the present assignee, the disclosures of which are hereby incorporated herein by reference. In addition, U.S. Pat. No. 6,522,562 to Foss, entitled “Content Addressable Memory Cell Having Improved Layout,” discloses a CAM cell that uses p-channel transistors as SRAM access transistors. These p-channel transistors purportedly improve layout efficiency by providing a balanced number of p-channel and N-channel transistors within each CAM cell. In particular,
FIG. 4 of the '562 patent illustrates a CAM half-cell that includes a 6T SRAM cell defined by two PMOS access transistors P3 and P4, two PMOS pull-up transistors P1 and P2 and two NMOS pull-down transistors N1 and N2. One half of a 4T compare circuit is also illustrated as including two NMOS transistors N3 and N4. Unfortunately, because PMOS transistors typically have lower mobility relative to equivalently-sized NMOS transistors, using PMOS transistors as access transistors within an SRAM cell may require relatively large PMOS transistors that increase overall unit cell size. - CAM cells having small unit cell size can also be achieved using lower transistor count dynamic CAM cells. For example,
FIG. 5 of U.S. Pat. No. 6,188,594 to Ong, entitled “Reduced-Pitch 6-Transistor NMOS Content-Addressable-Memory Cell,” discloses a 6T CAM cell having a non-unity layout aspect ratio. - Embodiments of the present invention include ternary CAM cells having extremely small layout footprint size and efficient layout aspect ratios that enhance scalability and uniformity of wiring pitch. The ternary CAM cells also have high degrees of symmetry that facilitate extensive sharing of vias between transistor-equivalent half-cells. These shared vias provide electrical interconnects between terminals of the CAM cell transistors and bit, data and match lines. Accordingly, when the CAM half-cells are joined together on all four sides to form a large CAM array, a low per cell via count can be achieved.
- First embodiments of the present invention include a 16T SRAM-based ternary CAM cell that extends in a semiconductor substrate and has a substantially square layout aspect ratio. In particular, the CAM cell includes first and second pairs of access transistors that extend adjacent a first side of the ternary CAM cell, and first and second pairs of cross-coupled inverters that extend adjacent a second side of the ternary CAM cell. First and second halves of a 4T compare circuit are also provided. The first half of the 4T compare circuit is positioned so that is extends between the first pair of access transistors and the first pair of cross-coupled inverters. Similarly, the second half of the 4T compare circuit is positioned so that it extends between the second pair of access transistors and the second pair of cross-coupled inverters.
- The first pair of cross-coupled inverters include a first inverter having a first PMOS pull-up transistor and a first NMOS pull-down transistor therein, and a second inverter having a second PMOS pull-up transistor and a second NMOS pull-down transistor therein. To facilitate high cell density, the first and second NMOS pull-down transistors are positioned so that they extend between the first and second PMOS pull-up transistors (on one side) and the first half of the 4T compare circuit (on an opposite side). The second pair of cross-coupled inverters include a second pair of PMOS pull-up transistors and a second pair of NMOS pull-down transistors, which extend between the second pair of PMOS pull-up transistors and the second half of the 4T compare circuit.
- According to preferred aspects of these embodiments, the first and second pairs of access transistors are equivalently-sized NMOS transistors having a first width/length (W/L) ratio and the 4T compare circuit comprises four equivalently-sized NMOS transistors having a second width/length ratio that is greater than the first width/length ratio. In some embodiments, the first width/length ratio is less than about 1.15 and the second width/length ratio is greater than about 1.15. More preferably, the first width/length ratio is about 1.04 and the second width/length ratio is about 1.25. The first pair of cross-coupled inverters comprises two equivalently-sized NMOS pull-down transistors having a third width/length ratio and two equivalently-sized PMOS pull-up transistors having a fourth width/length ratio that is less than the third width/length ratio. In some embodiments, the third width/length ratio is greater than about 1.5 and the fourth width/length ratio is less than about 1.25. More preferably, the third width/length ratio is about 1.8 and the fourth width/length ratio is about 1.0.
- To achieve high degrees of scalability and support relatively uniform horizontal and vertical wiring pitches, a width/height aspect ratio of the ternary CAM cell is approximately square. In some embodiments, the width/height aspect ratio may be in a range from between about 1.08 and about 1.20. High density layouts can also be achieved by placing and orienting the MOS transistors of a CAM cell in orthogonal x and y directions that achieve a high packing density. In particular, a ternary CAM cell can be achieved having a footprint in a range from between about 3.0 μm2 and about 3.6 μm2.
- Ternary CAM cells according to additional embodiments of the present invention include a first pair of NMOS access transistors having source and drain regions that are arranged in a y-direction in a first quadrant of the ternary CAM cell. A second pair of NMOS access transistors are also provided in a second quadrant of the ternary CAM cell and their source and drain regions are also arranged in the y-direction. The ternary CAM cell also includes first and second pairs of cross-coupled inverters that are positioned in fourth and third quadrants, respectively. The first pair of cross-coupled inverters comprises two PMOS pull-up transistors and two NMOS pull-down transistors that are arranged in an x-direction, which is orthogonal to the y-direction. Similarly, the second pair of cross-coupled inverters comprises two PMOS pull-up transistors and two NMOS pull-down transistors that are arranged in the x-direction. The ternary CAM cell also includes a 4T compare circuit that is divided into two halves. A first half of the 4T compare circuit is positioned between the first pair of access transistors and the first pair of cross-coupled inverters, and comprises two NMOS transistors that are arranged in the x-direction. Similarly, the second half of the 4T compare circuit is positioned between the second pair of access transistors and the second pair of cross-coupled inverters, and comprises two NMOS transistors arranged in the x-direction.
- Many additional embodiments of the present invention are also provided, as described further herein.
-
FIG. 1A is an electrical schematic of a ternary CAM cell according to an embodiment of the present invention. -
FIG. 1B is a layout schematic of the ternary CAM cell ofFIG. 1A . The left-to-right and top-to-bottom orientation of the MOS transistors in the layout schematic match the orientation of the MOS transistors in the electrical schematic ofFIG. 1A . -
FIG. 1C is an electrical schematic of a ternary CAM cell that is similar to the embodiment ofFIG. 1A , however, a pseudo-ground (PGND) connection is provided. -
FIG. 1D is a layout schematic of the ternary CAM cell ofFIG. 1B , with layout aspect ratio and transistor size information provided. -
FIG. 1E is a layout schematic of the ternary CAM cells ofFIGS. 1B and 1D , with dotted lines that show the positions of various transistors within four quadrants of a substantially square CAM cell. -
FIG. 1F is a separated layout view of four half-cells with half-via and quarter-via patterns illustrated. - The present invention now will be described more fully herein with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout and signal lines and signals thereon may be referred to by the same reference characters. Signals may also be synchronized and/or undergo minor boolean operations (e.g., inversion) without being considered different signals. The suffix B (or prefix symbol “/”) to a signal name may also denote a complementary data or information signal or an active low control signal, for example.
- Referring now to
FIG. 1A , an electrical schematic of aternary CAM cell 10A according to an embodiment of the present invention will be described. Theternary CAM cell 10A represents a sixteen transistor (16T) ternary CAM cell having two SRAM cells and a four transistor (4T) compare circuit therein. Each SRAM cell includes two access transistors and one pair of cross-coupled inverters that operate as a storage element. On the left side ofFIG. 1A , a left half of theternary CAM cell 10A is illustrated. This left half includes an X-SRAM storage element that generates an X output, which is provided to a left half of the 4T compare circuit. The X-SRAM storage element is defined by a first inverter, which consists of PMOS pull-up transistor P1 and NMOS pull-down transistor N1, and a second inverter, which consists of PMOS pull-up transistor P2 and NMOS pull-down transistor N2. The input of the first inverter is designated by the label X and the input of the second inverter is designated by the complementary label XB. - The input X of the first inverter is electrically connected to a first current carrying terminal of an NMOS access transistor N10. This first current carrying terminal of the NMOS access transistor N10 is illustrated as a drain terminal. The NMOS access transistor N10 has a gate terminal that is responsive to a word line signal WL and a second current carrying terminal that is responsive to a true bit line signal (shown as BX). The input XB of the second inverter is electrically connected to a first current carrying terminal of an NMOS access transistor N9. The NMOS access transistor N9 has a gate terminal that is responsive to the word line signal WL and a second current carrying terminal that is responsive to a complementary bit line signal (shown as BXB). The left half of the 4T compare circuit is defined by NMOS transistors N5 and N6, which are connected in series (i.e., source-to-drain) between a match line (ML) and a ground reference line (Vss). NMOS transistor N5 is configured to receive the signal X, which is the output of the second inverter defined by PMOS pull-up transistor P2 and NMOS pull-down transistor N2. NMOS transistor N6 is configured to receive a true data signal (shown as D), which represents the true bit of a comparand that is applied to the
ternary CAM cell 10A during a search operation. - The right half of the
ternary CAM cell 10A includes a Y-SRAM storage element that generates an output to a right half of the 4T compare circuit. The Y-SRAM storage element is defined by a third inverter, which consists of PMOS pull-up transistor P3 and NMOS pull-down transistor N3, and a fourth inverter, which consists of PMOS pull-up transistor P4 and NMOS pull-down transistor N4. The input of the fourth inverter is designated by the label Y and the input of the third inverter is designated by the label YB. The input Y of the fourth inverter is electrically connected to a first current carrying terminal of NMOS access transistor N12. The NMOS access transistor N12 has a gate terminal that is responsive to the word line signal WL and a second current carrying terminal that is responsive to a true bit line signal (shown as BY). - The input YB of the third inverter is electrically connected to a first current carrying terminal of NMOS access transistor N11. The NMOS access transistor N11 has a gate terminal that is responsive to the word line signal WL and a second current carrying terminal that is responsive to a complementary bit line signal (shown as BYB). The right half of the 4T compare circuit is defined by NMOS transistors N7 and N8, which are connected in series (i.e., source-to-drain) between a match line (ML) and a ground reference line (Vss). NMOS transistor N8 is configured to receive the signal Y, which is the output of the third inverter defined by PMOS pull-up transistor P3 and NMOS pull-down transistor N3. NMOS transistor N7 is configured to receive a complementary data signal (shown as DB), which represents the complementary bit of the aforementioned comparand.
- Based on the illustrated configuration of the transistors and interconnections within the cell embodiment of
FIG. 1A , theternary CAM cell 10A is configured to support three valid states in accordance with TABLE 1:TABLE 1 X Y STATE 0 0 MASK 0 1 0 1 0 1 1 1 INVALID - Similarly, by reversing the positions of the differential data lines (D and DB) within the CAM array, the
CAM cell 10A will support the three valid states illustrated by TABLE 2:TABLE 2 X Y STATE 0 0 MASK 0 1 1 1 0 0 1 1 INVALID - The electrical schematic of the
ternary CAM cell 10A illustrated byFIG. 1A corresponds to the layout schematic of theternary CAM cell 10B illustrated byFIG. 1B . Thus, inFIG. 1A , the lateral (left-to-right) orientation of PMOS pull-up transistors P1-P4 and NMOS transistors N1-N8 represents the lateral x-direction orientation of the PMOS pull-up transistors P1-P4 and the NMOS transistors N1-B8 illustrated byFIG. 1B . Likewise, the vertical (top-to-bottom) orientation of NMOS access transistors N9-N12 represents the vertical y-direction orientation of the NMOS access transistors N9-N12 illustrated byFIG. 1B . As will be understood by those skilled in the art, the open (i.e., unshaded) polygons in the layout ofFIG. 1B represent source/drain diffusion patterns and the shaded polygons represent gate “poly” patterns (i.e., polysilicon patterns). Thus, inFIG. 1B , the source-to-drain direction (i.e., channel length direction) of the PMOS pull-up transistors P1-P4 and the NMOS transistors N1-N8 corresponds to the x-direction and the source-to-drain direction of the NMOS access transistors N9-N12 corresponds to the y-direction. - In the
ternary CAM cell 10B, the gate poly patterns associated with PMOS pull-up transistor P1, NMOS pull-down transistor N1 and NMOS transistor N5 are joined into one contiguous pattern, to represent a portion of the signal line X inFIG. 1A . Similarly, the contiguous gate poly pattern associated with PMOS pull-up transistor P2 and NMOS pull-down transistor N2 represents a portion of the signal line XB inFIG. 1A . The contiguous gate poly pattern associated with PMOS pull-up transistor P3 and NMOS pull-down transistor N3 represents a portion of the signal line YB inFIG. 1A . The contiguous gate poly pattern associated with PMOS pull-up transistor P4 and NMOS pull-down transistor N4 represents a portion of the signal line Y inFIG. 1A . The gate poly patterns associated with NMOS transistor N6 and NMOS transistor N7 represent portions of the true and complementary connections to the true data line D and the complementary data line DB, respectively. The single gate poly pattern that extends laterally across the top side of theternary CAM cell 10B represents a word line (WL). - The reference labels BXB, BX, BYB and BY, which run along the top side of the
ternary CAM cell 10B, represent the source regions of access transistors that are electrically connected (by vias) to two pairs of differential bit lines. The reference labels ML represents the drain regions of two NMOS transistors N5 and N8 that are electrically connected (by vias) to a match line (not shown), which is typically formed at a higher level of metallization. The reference labels Vss represent the source regions of NMOS transistors N1-N4 and N6-N7, which are electrically connected (by vias) to a ground reference line. Finally, the reference labels Vdd represent the drain regions of PMOS pull-up transistors P1-P4, which are electrically connected (by vias) to a power supply line (e.g., Vdd=1 Volt). - Referring now to
FIG. 1C , a 16Tternary CAM cell 10C according to another embodiment of the present invention is illustrated. ThisCAM cell 10C is essentially identical to theternary CAM cell 10A ofFIG. 1A , however, the source terminals of NMOS transistors N6 and N7 within the 4T compare circuit are connected to a switchable pseudo-ground line (PGND), instead of a fixed ground reference line (Vss). The use of switchable pseudo-ground lines to enhance performance of ternary CAM arrays in certain applications is more fully described in U.S. application Ser. Nos.: 10/0084,842 to Lien et al., filed Feb. 27, 2002; 10/306,799 to Lien et al., filed Nov. 27, 2002; and 10/323,236 to Park et al., filed Dec. 18, 2002, the disclosures of which are hereby incorporated herein by reference. - As illustrated by the
ternary CAM cell 10D ofFIG. 1D , the layout of the CAM cell ofFIGS. 1A-1B includes two half-cells, left and right. These two half-cells have equivalent transistor count and the source/drain diffusion regions of these half-cells are mirror images of each other. As illustrated more fully byFIG. 1F , these half-cells may be replicated side-by-side in an alternating left/right half-cell sequence to form a row of CAM cells (e.g., a ×80 row). Moreover, theCAM cell 10D ofFIG. 1D and a mirror image of this cell when rotated about the x-axis, will result in a pair of cells that may be replicated side-by-side to define two adjacent rows of CAM cells within a CAM array. These two adjacent rows of CAM cells may be stacked vertically to define an array having a large number of rows and columns ofCAM cells 10D therein. -
FIG. 1D also illustrates how the layout of theternary CAM cells 10A-10D results in a width-to-height layout aspect ratio that is substantially square. In particular, in order to enhance scalability and uniformity of wiring pitch (in both x and y directions), it is preferred that the width/height aspect ratio be in a range from between about 1.08 and about 1.20 and, more preferably, about 1.14. Factors which influence the aspect ratio include the placement, size and orientation of the sixteen transistors within a cell. As described more fully hereinbelow, the placement and orientation is chosen so that the resulting CAM cell has essentially identical left and right half-cells. These half-cells may share all ML, Vss and Vdd vias with adjacent half-cells in a same row of a CAM array, and also share all bit line and data line vias (e.g., BXB, BX, BYB, BY, D and DB) with adjoining cells in a same column of the CAM array. Moreover, using deep sub-micron CMOS processes, including the Nexsys™ 90-nanometer process technology developed by Taiwan Semiconductor Manufacturing Company, Ltd., a small layout footprint in a range from between about 3.0 μm2 and about 3.6 μm2 can be achieved for the CAM cells illustrated herein. This 90-nanometer process technology supports a core supply voltage (Vdd) ranging from 1.0 Volts to 1.2 Volts with an I/O and analog block supply voltage ranging from 1.8 Volts to 3.3 Volts. - The sixteen transistors within the
ternary CAM cell 10D are also sized to achieve preferred operating characteristics including high soft-error immunity characteristics. A proper balance is also struck between the contribution of each cell to the bit line, data line and match line capacitance and cell speed. One significant design consideration is the speed/power tradeoff between the match line pull-down strength of each cell and its contribution to match line capacitance, which is a significant consumer of match line power during search operations. To achieve a proper balance of these and other design parameters, the first and second pairs of access transistors are equivalently-sized NMOS transistors and the NMOS transistors within the 4T compare circuit are also equivalently-sized. More particularly, the first and second pairs of access transistors N9-N10 and N11-N12 are equivalently-sized NMOS transistors having a first width/length (W/L) ratio. The 4T compare circuit comprises four equivalently-sized NMOS transistors N5-N8 having a second width/length ratio that is greater than the first width/length ratio. It is preferable that the first width/length ratio be less than about 1.15 and the second width/length ratio be greater than about 1.15. More preferably, the first width/length ratio is about 1.04 and the second width/length ratio is about 1.25, as illustrated byFIG. 1D . - The first and second pairs of cross-coupled inverters are also configured to have equivalently-sized NMOS pull-down transistors N1-N2 and N3-N4 having a third width/length ratio, and equivalently-sized PMOS pull-up transistors P1-P2 and P3-P4 having a fourth width/length ratio. The third width/length ratio is greater than the fourth width/length ratio. It is preferable that the third width/length ratio is greater than about 1.5 and the fourth width/length ratio is less than about 1.25. More preferably, the third width/length ratio is about 1.8 and the fourth width/length ratio is about 1.0, as illustrated by
FIG. 1D . - Referring now to
FIG. 1E , the layout patterns of theCAM cells FIGS. 1B and 1D are shown as being divided into four quadrants, I-IV, which occupy a layout footprint of 3.3 μm2. Quadrant I is illustrated as including the right pair of access transistors and the right half of the 4T compare circuit. Similarly, Quadrant II is illustrated as including the left pair of access transistors and the left half of the 4T compare circuit. Quadrant IV is illustrated as including two cross-coupled inverters, which define a storage element within an SRAM cell. These two cross-coupled inverters are defined by two NMOS pull-down transistors and two PMOS pull-up transistors, shown as N3-N4 and P3-P4 inFIGS. 1A-1C . Similarly, Quadrant III is illustrated as including two cross-coupled inverters, which comprise two NMOS pull-down transistors and two PMOS pull-up transistors, shown as N1-N2 and P1-P2 inFIGS. 1A-1C . Thus, each quadrant of theCAM cell FIG. 1E contains an equivalent number of transistors. - In
FIG. 1F , two pairs of CAM half-cells that are arranged within a row of a CAM array are identified by thereference numeral 10F. These half-cells are similar to those illustrated byFIG. 1D , however, numerous via connection patterns have been added to highlight the extensive via sharing between adjacent half-cells in both the x and y directions, when the half-cells are joined together to define a two-dimensional array of CAM cells. These via connections may illustrate: CO contact holes from first level metallization (M1) to the poly gate patterns or source/drain diffusion patterns, VIA1 holes connecting the first level metallization to second level metallization (M2) (not shown) or VIA2 holes connection the second level metallization to third level metallization (not shown). For example, the poly gates of NMOS transistors N6 and N7, which are illustrated by the reference labels D and DB inFIG. 1B , are illustrated as being connected through CO contact holes to respective first level metallization patterns that have been added toFIG. 1F . These first level metallization patterns are are shaded in the reverse direction relative to the poly gate patterns. Moreover, according to preferred aspects of these half-cell layouts, the via connections to power supply lines (Vdd), ground reference lines (Vss), match lines (ML), and bit and data lines (shown as BYB, BY, BXB, BX, D and DB) are positioned along the outer periphery of each half-cell in order to achieve high degrees of via sharing (½Via or ¼Via) between adjacent half-cells in both the x and y directions. This high degree of via sharing contributes to a smaller layout footprint having a substantially square aspect ratio. - In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.
Claims (57)
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US11/137,163 US7110275B2 (en) | 2003-06-30 | 2005-05-25 | High speed NAND-type content addressable memory (CAM) |
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Cited By (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070195570A1 (en) * | 2006-02-23 | 2007-08-23 | Laurence Hager Cooke | Serial content addressable memory |
US20100097831A1 (en) * | 2006-02-23 | 2010-04-22 | Cooke Laurence H | Iterative serial content addressable memory |
US20120262979A1 (en) * | 2011-04-15 | 2012-10-18 | Semiconductor Energy Laboratory Co., Ltd. | Memory device |
US8448102B2 (en) | 2006-03-09 | 2013-05-21 | Tela Innovations, Inc. | Optimizing layout of irregular structures in regular layout context |
US8453094B2 (en) | 2008-01-31 | 2013-05-28 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
US8471391B2 (en) | 2008-03-27 | 2013-06-25 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
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US8549455B2 (en) | 2007-08-02 | 2013-10-01 | Tela Innovations, Inc. | Methods for cell phasing and placement in dynamic array architecture and implementation of the same |
US8552508B2 (en) | 2008-03-13 | 2013-10-08 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer |
US8653857B2 (en) | 2006-03-09 | 2014-02-18 | Tela Innovations, Inc. | Circuitry and layouts for XOR and XNOR logic |
US8658542B2 (en) | 2006-03-09 | 2014-02-25 | Tela Innovations, Inc. | Coarse grid design methods and structures |
US8661392B2 (en) | 2009-10-13 | 2014-02-25 | Tela Innovations, Inc. | Methods for cell boundary encroachment and layouts implementing the Same |
US8667443B2 (en) | 2007-03-05 | 2014-03-04 | Tela Innovations, Inc. | Integrated circuit cell library for multiple patterning |
US8680626B2 (en) | 2007-10-26 | 2014-03-25 | Tela Innovations, Inc. | Methods, structures, and designs for self-aligning local interconnects used in integrated circuits |
US8756551B2 (en) | 2007-08-02 | 2014-06-17 | Tela Innovations, Inc. | Methods for designing semiconductor device with dynamic array section |
US8823062B2 (en) | 2006-03-09 | 2014-09-02 | Tela Innovations, Inc. | Integrated circuit with offset line end spacings in linear gate electrode level |
US8839175B2 (en) | 2006-03-09 | 2014-09-16 | Tela Innovations, Inc. | Scalable meta-data objects |
US8863063B2 (en) | 2009-05-06 | 2014-10-14 | Tela Innovations, Inc. | Finfet transistor circuit |
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US9122832B2 (en) | 2008-08-01 | 2015-09-01 | Tela Innovations, Inc. | Methods for controlling microloading variation in semiconductor wafer layout and fabrication |
US9159627B2 (en) | 2010-11-12 | 2015-10-13 | Tela Innovations, Inc. | Methods for linewidth modification and apparatus implementing the same |
US9230910B2 (en) | 2006-03-09 | 2016-01-05 | Tela Innovations, Inc. | Oversized contacts and vias in layout defined by linearly constrained topology |
US9563733B2 (en) | 2009-05-06 | 2017-02-07 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
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Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4336625B2 (en) * | 2004-06-17 | 2009-09-30 | 株式会社日立製作所 | Packet transfer device |
US7136006B2 (en) * | 2004-12-16 | 2006-11-14 | Texas Instruments Incorporated | Systems and methods for mismatch cancellation in switched capacitor circuits |
US7304874B2 (en) * | 2005-03-08 | 2007-12-04 | Lsi Corporation | Compact ternary and binary CAM bitcell architecture with no enclosed diffusion areas |
US7170769B1 (en) * | 2005-10-03 | 2007-01-30 | Texas Instruments Incorporated | High performance and reduced area architecture for a fully parallel search of a TCAM cell |
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US7825777B1 (en) | 2006-03-08 | 2010-11-02 | Integrated Device Technology, Inc. | Packet processors having comparators therein that determine non-strict inequalities between applied operands |
US7298636B1 (en) | 2006-03-08 | 2007-11-20 | Integrated Device Technology, Inc. | Packet processors having multi-functional range match cells therein |
US7355890B1 (en) | 2006-10-26 | 2008-04-08 | Integrated Device Technology, Inc. | Content addressable memory (CAM) devices having NAND-type compare circuits |
US7840783B1 (en) | 2007-09-10 | 2010-11-23 | Netlogic Microsystems, Inc. | System and method for performing a register renaming operation utilizing hardware which is capable of operating in at least two modes utilizing registers of multiple widths |
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US7944724B2 (en) * | 2009-04-28 | 2011-05-17 | Netlogic Microsystems, Inc. | Ternary content addressable memory having reduced leakage effects |
US7920397B1 (en) | 2010-04-30 | 2011-04-05 | Netlogic Microsystems, Inc. | Memory device having bit line leakage compensation |
US8553441B1 (en) | 2010-08-31 | 2013-10-08 | Netlogic Microsystems, Inc. | Ternary content addressable memory cell having two transistor pull-down stack |
US8582338B1 (en) | 2010-08-31 | 2013-11-12 | Netlogic Microsystems, Inc. | Ternary content addressable memory cell having single transistor pull-down stack |
US8625320B1 (en) | 2010-08-31 | 2014-01-07 | Netlogic Microsystems, Inc. | Quaternary content addressable memory cell having one transistor pull-down stack |
US8462532B1 (en) | 2010-08-31 | 2013-06-11 | Netlogic Microsystems, Inc. | Fast quaternary content addressable memory cell |
US8773880B2 (en) | 2011-06-23 | 2014-07-08 | Netlogic Microsystems, Inc. | Content addressable memory array having virtual ground nodes |
US8837188B1 (en) | 2011-06-23 | 2014-09-16 | Netlogic Microsystems, Inc. | Content addressable memory row having virtual ground and charge sharing |
US8891273B2 (en) | 2012-12-26 | 2014-11-18 | Qualcomm Incorporated | Pseudo-NOR cell for ternary content addressable memory |
US8958226B2 (en) | 2012-12-28 | 2015-02-17 | Qualcomm Incorporated | Static NAND cell for ternary content addressable memory (TCAM) |
US8934278B2 (en) | 2012-12-28 | 2015-01-13 | Qualcomm Incorporated | Hybrid ternary content addressable memory |
US9041428B2 (en) | 2013-01-15 | 2015-05-26 | International Business Machines Corporation | Placement of storage cells on an integrated circuit |
US9201727B2 (en) | 2013-01-15 | 2015-12-01 | International Business Machines Corporation | Error protection for a data bus |
US9021328B2 (en) | 2013-01-15 | 2015-04-28 | International Business Machines Corporation | Shared error protection for register banks |
US9043683B2 (en) | 2013-01-23 | 2015-05-26 | International Business Machines Corporation | Error protection for integrated circuits |
US9824756B2 (en) | 2013-08-13 | 2017-11-21 | Globalfoundries Inc. | Mapping a lookup table to prefabricated TCAMS |
US9449667B2 (en) | 2014-03-31 | 2016-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory circuit having shared word line |
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EP3295331A4 (en) | 2015-05-11 | 2019-04-17 | Cambou, Bertrand, F. | Memory circuit using dynamic random access memory arrays |
US9588908B2 (en) | 2015-06-02 | 2017-03-07 | Bertrand F. Cambou | Memory circuit using resistive random access memory arrays in a secure element |
US9728258B1 (en) | 2016-10-04 | 2017-08-08 | National Tsing Hua University | Ternary content addressable memory |
US9916889B1 (en) * | 2016-12-01 | 2018-03-13 | Intel Corporation | Memory circuitry with row-wise gating capabilities |
JP2019033161A (en) * | 2017-08-07 | 2019-02-28 | ルネサスエレクトロニクス株式会社 | Semiconductor memory device |
US11437320B2 (en) | 2019-07-23 | 2022-09-06 | Samsung Electronics Co., Ltd. | Semiconductor devices |
Citations (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5699288A (en) * | 1996-07-18 | 1997-12-16 | International Business Machines Corporation | Compare circuit for content-addressable memories |
US6188594B1 (en) * | 1999-06-09 | 2001-02-13 | Neomagic Corp. | Reduced-pitch 6-transistor NMOS content-addressable-memory cell |
US6240004B1 (en) * | 2000-06-19 | 2001-05-29 | James B. Kuo | Low-voltage content addressable memory cell with a fast tag-compare capability using partially-depleted SOI CMOS dynamic-threshold techniques |
US6256216B1 (en) * | 2000-05-18 | 2001-07-03 | Integrated Device Technology, Inc. | Cam array with minimum cell size |
US6262907B1 (en) * | 2000-05-18 | 2001-07-17 | Integrated Device Technology, Inc. | Ternary CAM array |
US6362993B1 (en) * | 1999-01-15 | 2002-03-26 | Fast-Chip Incorporated | Content addressable memory device |
US6370052B1 (en) * | 2000-07-19 | 2002-04-09 | Monolithic System Technology, Inc. | Method and structure of ternary CAM cell in logic process |
US6374325B1 (en) * | 1998-02-17 | 2002-04-16 | Texas Instruments Incorporated | Content addressable memory (CAM) |
US6385070B1 (en) * | 2001-03-13 | 2002-05-07 | Tality, L.P. | Content Addressable Memory array, cell, and method using 5-transistor compare circuit and avoiding crowbar current |
US6430073B1 (en) * | 2000-12-06 | 2002-08-06 | International Business Machines Corporation | Dram CAM cell with hidden refresh |
US20020141218A1 (en) * | 2001-04-03 | 2002-10-03 | Richard Foss | Content addressable memory cell |
US6480406B1 (en) * | 2001-08-22 | 2002-11-12 | Cypress Semiconductor Corp. | Content addressable memory cell |
US6496398B2 (en) * | 2000-12-15 | 2002-12-17 | International Business Machines Corporation | Content addressable memory |
US6515884B1 (en) * | 2001-12-18 | 2003-02-04 | Cypress Semiconductor Corporation | Content addressable memory having reduced current consumption |
US6522562B2 (en) * | 2001-04-03 | 2003-02-18 | Mosaid Technologies Incorporated | Content addressable memory cell having improved layout |
US20030035331A1 (en) * | 2000-03-03 | 2003-02-20 | Foss Richard C. | High density memory cell |
US6563727B1 (en) * | 2002-07-31 | 2003-05-13 | Alan Roth | Method and structure for reducing noise effects in content addressable memories |
US6678184B2 (en) * | 2002-06-05 | 2004-01-13 | Stmicroelectronics, Inc. | CAM cell having compare circuit formed over two active regions |
US6760249B2 (en) * | 2001-06-21 | 2004-07-06 | Pien Chien | Content addressable memory device capable of comparing data bit with storage data bit |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5859791A (en) * | 1997-01-09 | 1999-01-12 | Northern Telecom Limited | Content addressable memory |
US6078987A (en) * | 1997-09-30 | 2000-06-20 | Sun Microsystems, Inc. | Translation look aside buffer having separate RAM arrays which are accessable with separate enable signals |
US6044005A (en) * | 1999-02-03 | 2000-03-28 | Sibercore Technologies Incorporated | Content addressable memory storage device |
US6166938A (en) * | 1999-05-21 | 2000-12-26 | Sandisk Corporation | Data encoding for content addressable memories |
US6195278B1 (en) * | 1999-12-30 | 2001-02-27 | Nortel Networks Limited | Content addressable memory cells and words |
JP4298104B2 (en) * | 2000-01-18 | 2009-07-15 | Okiセミコンダクタ株式会社 | Associative memory |
DE60123542T2 (en) * | 2000-09-23 | 2007-05-10 | International Business Machines Corp. | Associative memory circuit for retrieval in a data processing system |
US6349049B1 (en) * | 2001-03-22 | 2002-02-19 | Sun Microsystems, Inc. | High speed low power content addressable memory |
JP5072145B2 (en) * | 2001-04-05 | 2012-11-14 | 富士通セミコンダクター株式会社 | Associative memory |
US6707694B2 (en) * | 2001-07-06 | 2004-03-16 | Micron Technology, Inc. | Multi-match detection circuit for use with content-addressable memories |
-
2003
- 2003-06-30 US US10/609,756 patent/US6900999B1/en not_active Expired - Lifetime
-
2004
- 2004-06-17 JP JP2006518651A patent/JP4823901B2/en not_active Expired - Fee Related
- 2004-06-17 WO PCT/US2004/019148 patent/WO2005006343A2/en active Application Filing
- 2004-06-17 CN CN2004800186522A patent/CN1849669B/en not_active Expired - Fee Related
- 2004-06-24 TW TW093118317A patent/TWI266319B/en not_active IP Right Cessation
-
2005
- 2005-05-25 US US11/137,163 patent/US7110275B2/en not_active Expired - Lifetime
Patent Citations (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5699288A (en) * | 1996-07-18 | 1997-12-16 | International Business Machines Corporation | Compare circuit for content-addressable memories |
US6374325B1 (en) * | 1998-02-17 | 2002-04-16 | Texas Instruments Incorporated | Content addressable memory (CAM) |
US6362993B1 (en) * | 1999-01-15 | 2002-03-26 | Fast-Chip Incorporated | Content addressable memory device |
US6188594B1 (en) * | 1999-06-09 | 2001-02-13 | Neomagic Corp. | Reduced-pitch 6-transistor NMOS content-addressable-memory cell |
US20030035331A1 (en) * | 2000-03-03 | 2003-02-20 | Foss Richard C. | High density memory cell |
US6256216B1 (en) * | 2000-05-18 | 2001-07-03 | Integrated Device Technology, Inc. | Cam array with minimum cell size |
US6262907B1 (en) * | 2000-05-18 | 2001-07-17 | Integrated Device Technology, Inc. | Ternary CAM array |
US6240004B1 (en) * | 2000-06-19 | 2001-05-29 | James B. Kuo | Low-voltage content addressable memory cell with a fast tag-compare capability using partially-depleted SOI CMOS dynamic-threshold techniques |
US6370052B1 (en) * | 2000-07-19 | 2002-04-09 | Monolithic System Technology, Inc. | Method and structure of ternary CAM cell in logic process |
US6430073B1 (en) * | 2000-12-06 | 2002-08-06 | International Business Machines Corporation | Dram CAM cell with hidden refresh |
US6496398B2 (en) * | 2000-12-15 | 2002-12-17 | International Business Machines Corporation | Content addressable memory |
US6385070B1 (en) * | 2001-03-13 | 2002-05-07 | Tality, L.P. | Content Addressable Memory array, cell, and method using 5-transistor compare circuit and avoiding crowbar current |
US20020141218A1 (en) * | 2001-04-03 | 2002-10-03 | Richard Foss | Content addressable memory cell |
US6522562B2 (en) * | 2001-04-03 | 2003-02-18 | Mosaid Technologies Incorporated | Content addressable memory cell having improved layout |
US6760249B2 (en) * | 2001-06-21 | 2004-07-06 | Pien Chien | Content addressable memory device capable of comparing data bit with storage data bit |
US6480406B1 (en) * | 2001-08-22 | 2002-11-12 | Cypress Semiconductor Corp. | Content addressable memory cell |
US6515884B1 (en) * | 2001-12-18 | 2003-02-04 | Cypress Semiconductor Corporation | Content addressable memory having reduced current consumption |
US6678184B2 (en) * | 2002-06-05 | 2004-01-13 | Stmicroelectronics, Inc. | CAM cell having compare circuit formed over two active regions |
US6563727B1 (en) * | 2002-07-31 | 2003-05-13 | Alan Roth | Method and structure for reducing noise effects in content addressable memories |
Cited By (117)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070195570A1 (en) * | 2006-02-23 | 2007-08-23 | Laurence Hager Cooke | Serial content addressable memory |
US7369422B2 (en) | 2006-02-23 | 2008-05-06 | Laurence Hager Cooke | Serial content addressable memory |
US20080209121A1 (en) * | 2006-02-23 | 2008-08-28 | Laurence Hager Cooke | Serial Content Addressable Memory |
US7649759B2 (en) | 2006-02-23 | 2010-01-19 | Cooke Laurence H | Serial content addressable memory |
US20100097831A1 (en) * | 2006-02-23 | 2010-04-22 | Cooke Laurence H | Iterative serial content addressable memory |
US8085567B2 (en) | 2006-02-23 | 2011-12-27 | Cooke Laurence H | Iterative serial content addressable memory |
US9741719B2 (en) | 2006-03-09 | 2017-08-22 | Tela Innovations, Inc. | Methods, structures, and designs for self-aligning local interconnects used in integrated circuits |
US9336344B2 (en) | 2006-03-09 | 2016-05-10 | Tela Innovations, Inc. | Coarse grid design methods and structures |
US8921896B2 (en) | 2006-03-09 | 2014-12-30 | Tela Innovations, Inc. | Integrated circuit including linear gate electrode structures having different extension distances beyond contact |
US9673825B2 (en) | 2006-03-09 | 2017-06-06 | Tela Innovations, Inc. | Circuitry and layouts for XOR and XNOR logic |
US8921897B2 (en) | 2006-03-09 | 2014-12-30 | Tela Innovations, Inc. | Integrated circuit with gate electrode conductive structures having offset ends |
US9711495B2 (en) | 2006-03-09 | 2017-07-18 | Tela Innovations, Inc. | Oversized contacts and vias in layout defined by linearly constrained topology |
US10230377B2 (en) | 2006-03-09 | 2019-03-12 | Tela Innovations, Inc. | Circuitry and layouts for XOR and XNOR logic |
US10217763B2 (en) | 2006-03-09 | 2019-02-26 | Tela Innovations, Inc. | Semiconductor chip having region including gate electrode features of rectangular shape on gate horizontal grid and first-metal structures of rectangular shape on at least eight first-metal gridlines of first-metal vertical grid |
US10186523B2 (en) | 2006-03-09 | 2019-01-22 | Tela Innovations, Inc. | Semiconductor chip having region including gate electrode features formed in part from rectangular layout shapes on gate horizontal grid and first-metal structures formed in part from rectangular layout shapes on at least eight first-metal gridlines of first-metal vertical grid |
US10141334B2 (en) | 2006-03-09 | 2018-11-27 | Tela Innovations, Inc. | Semiconductor chip including region having rectangular-shaped gate structures and first-metal structures |
US10141335B2 (en) | 2006-03-09 | 2018-11-27 | Tela Innovations, Inc. | Semiconductor CIP including region having rectangular-shaped gate structures and first metal structures |
US8952425B2 (en) | 2006-03-09 | 2015-02-10 | Tela Innovations, Inc. | Integrated circuit including at least four linear-shaped conductive structures having extending portions of different length |
US9917056B2 (en) | 2006-03-09 | 2018-03-13 | Tela Innovations, Inc. | Coarse grid design methods and structures |
US9009641B2 (en) | 2006-03-09 | 2015-04-14 | Tela Innovations, Inc. | Circuits with linear finfet structures |
US9905576B2 (en) | 2006-03-09 | 2018-02-27 | Tela Innovations, Inc. | Semiconductor chip including region having rectangular-shaped gate structures and first metal structures |
US9859277B2 (en) | 2006-03-09 | 2018-01-02 | Tela Innovations, Inc. | Methods, structures, and designs for self-aligning local interconnects used in integrated circuits |
US9035359B2 (en) | 2006-03-09 | 2015-05-19 | Tela Innovations, Inc. | Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods |
US8653857B2 (en) | 2006-03-09 | 2014-02-18 | Tela Innovations, Inc. | Circuitry and layouts for XOR and XNOR logic |
US8658542B2 (en) | 2006-03-09 | 2014-02-25 | Tela Innovations, Inc. | Coarse grid design methods and structures |
US9754878B2 (en) | 2006-03-09 | 2017-09-05 | Tela Innovations, Inc. | Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires |
US9230910B2 (en) | 2006-03-09 | 2016-01-05 | Tela Innovations, Inc. | Oversized contacts and vias in layout defined by linearly constrained topology |
US8946781B2 (en) | 2006-03-09 | 2015-02-03 | Tela Innovations, Inc. | Integrated circuit including gate electrode conductive structures with different extension distances beyond contact |
US9240413B2 (en) | 2006-03-09 | 2016-01-19 | Tela Innovations, Inc. | Methods, structures, and designs for self-aligning local interconnects used in integrated circuits |
US8839175B2 (en) | 2006-03-09 | 2014-09-16 | Tela Innovations, Inc. | Scalable meta-data objects |
US8823062B2 (en) | 2006-03-09 | 2014-09-02 | Tela Innovations, Inc. | Integrated circuit with offset line end spacings in linear gate electrode level |
US8448102B2 (en) | 2006-03-09 | 2013-05-21 | Tela Innovations, Inc. | Optimizing layout of irregular structures in regular layout context |
US9425272B2 (en) | 2006-03-09 | 2016-08-23 | Tela Innovations, Inc. | Semiconductor chip including integrated circuit including four transistors of first transistor type and four transistors of second transistor type with electrical connections between various transistors and methods for manufacturing the same |
US9425145B2 (en) | 2006-03-09 | 2016-08-23 | Tela Innovations, Inc. | Oversized contacts and vias in layout defined by linearly constrained topology |
US9425273B2 (en) | 2006-03-09 | 2016-08-23 | Tela Innovations, Inc. | Semiconductor chip including integrated circuit including at least five gate level conductive structures having particular spatial and electrical relationship and method for manufacturing the same |
US9589091B2 (en) | 2006-03-09 | 2017-03-07 | Tela Innovations, Inc. | Scalable meta-data objects |
US9443947B2 (en) | 2006-03-09 | 2016-09-13 | Tela Innovations, Inc. | Semiconductor chip including region having integrated circuit transistor gate electrodes formed by various conductive structures of specified shape and position and method for manufacturing the same |
US8667443B2 (en) | 2007-03-05 | 2014-03-04 | Tela Innovations, Inc. | Integrated circuit cell library for multiple patterning |
US10074640B2 (en) | 2007-03-05 | 2018-09-11 | Tela Innovations, Inc. | Integrated circuit cell library for multiple patterning |
US9633987B2 (en) | 2007-03-05 | 2017-04-25 | Tela Innovations, Inc. | Integrated circuit cell library for multiple patterning |
US8966424B2 (en) | 2007-03-07 | 2015-02-24 | Tela Innovations, Inc. | Methods for cell phasing and placement in dynamic array architecture and implementation of the same |
US9595515B2 (en) | 2007-03-07 | 2017-03-14 | Tela Innovations, Inc. | Semiconductor chip including integrated circuit defined within dynamic array section |
US9910950B2 (en) | 2007-03-07 | 2018-03-06 | Tela Innovations, Inc. | Methods for cell phasing and placement in dynamic array architecture and implementation of the same |
US9424387B2 (en) | 2007-03-07 | 2016-08-23 | Tela Innovations, Inc. | Methods for cell phasing and placement in dynamic array architecture and implementation of the same |
US8756551B2 (en) | 2007-08-02 | 2014-06-17 | Tela Innovations, Inc. | Methods for designing semiconductor device with dynamic array section |
US8549455B2 (en) | 2007-08-02 | 2013-10-01 | Tela Innovations, Inc. | Methods for cell phasing and placement in dynamic array architecture and implementation of the same |
US8759882B2 (en) | 2007-08-02 | 2014-06-24 | Tela Innovations, Inc. | Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos |
US10734383B2 (en) | 2007-10-26 | 2020-08-04 | Tela Innovations, Inc. | Methods, structures, and designs for self-aligning local interconnects used in integrated circuits |
US8680626B2 (en) | 2007-10-26 | 2014-03-25 | Tela Innovations, Inc. | Methods, structures, and designs for self-aligning local interconnects used in integrated circuits |
US8541879B2 (en) | 2007-12-13 | 2013-09-24 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
US9818747B2 (en) | 2007-12-13 | 2017-11-14 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
US10461081B2 (en) | 2007-12-13 | 2019-10-29 | Tel Innovations, Inc. | Super-self-aligned contacts and method for making the same |
US8951916B2 (en) | 2007-12-13 | 2015-02-10 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
US9281371B2 (en) | 2007-12-13 | 2016-03-08 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
US9202779B2 (en) | 2008-01-31 | 2015-12-01 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
US9530734B2 (en) | 2008-01-31 | 2016-12-27 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
US8453094B2 (en) | 2008-01-31 | 2013-05-28 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
US8701071B2 (en) | 2008-01-31 | 2014-04-15 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
US8669595B2 (en) | 2008-03-13 | 2014-03-11 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position, alignment, and offset specifications |
US8735995B2 (en) | 2008-03-13 | 2014-05-27 | Tela Innovations, Inc. | Cross-coupled transistor circuit defined on three gate electrode tracks with diffusion regions of common node on opposing sides of same gate electrode track |
US8866197B2 (en) | 2008-03-13 | 2014-10-21 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through another transistor forming gate level feature |
US10727252B2 (en) | 2008-03-13 | 2020-07-28 | Tela Innovations, Inc. | Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same |
US8853793B2 (en) | 2008-03-13 | 2014-10-07 | Tela Innovations, Inc. | Integrated circuit including gate electrode level region including cross-coupled transistors having gate contacts located over inner portion of gate electrode level region and offset gate level feature line ends |
US8853794B2 (en) | 2008-03-13 | 2014-10-07 | Tela Innovations, Inc. | Integrated circuit within semiconductor chip including cross-coupled transistor configuration |
US9081931B2 (en) | 2008-03-13 | 2015-07-14 | Tela Innovations, Inc. | Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track and gate node connection through single interconnect layer |
US9117050B2 (en) | 2008-03-13 | 2015-08-25 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position and offset specifications |
US10658385B2 (en) | 2008-03-13 | 2020-05-19 | Tela Innovations, Inc. | Cross-coupled transistor circuit defined on four gate electrode tracks |
US10651200B2 (en) | 2008-03-13 | 2020-05-12 | Tela Innovations, Inc. | Cross-coupled transistor circuit defined on three gate electrode tracks |
US8847331B2 (en) | 2008-03-13 | 2014-09-30 | Tela Innovations, Inc. | Semiconductor chip including region having cross-coupled transistor configuration with offset electrical connection areas on gate electrode forming conductive structures and at least two different inner extension distances of gate electrode forming conductive structures |
US9208279B2 (en) | 2008-03-13 | 2015-12-08 | Tela Innovations, Inc. | Semiconductor chip including digital logic circuit including linear-shaped conductive structures having electrical connection areas located within inner region between transistors of different type and associated methods |
US9213792B2 (en) | 2008-03-13 | 2015-12-15 | Tela Innovations, Inc. | Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods |
US8847329B2 (en) | 2008-03-13 | 2014-09-30 | Tela Innovations, Inc. | Cross-coupled transistor circuit defined having diffusion regions of common node on opposing sides of same gate electrode track with at least two non-inner positioned gate contacts |
US8552508B2 (en) | 2008-03-13 | 2013-10-08 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer |
US8836045B2 (en) | 2008-03-13 | 2014-09-16 | Tela Innovations, Inc. | Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track |
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US8835989B2 (en) | 2008-03-13 | 2014-09-16 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate electrode placement specifications |
US8816402B2 (en) | 2008-03-13 | 2014-08-26 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate level feature layout channel including single transistor |
US8558322B2 (en) | 2008-03-13 | 2013-10-15 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through gate level feature |
US8785979B2 (en) | 2008-03-13 | 2014-07-22 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with two inside positioned gate contacts and two outside positioned gate contacts and electrical connection of cross-coupled transistors through same interconnect layer |
US8785978B2 (en) | 2008-03-13 | 2014-07-22 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with electrical connection of cross-coupled transistors through same interconnect layer |
US8772839B2 (en) | 2008-03-13 | 2014-07-08 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer |
US8564071B2 (en) | 2008-03-13 | 2013-10-22 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level feature extensions beyond contact |
US8742462B2 (en) | 2008-03-13 | 2014-06-03 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position specifications |
US8742463B2 (en) | 2008-03-13 | 2014-06-03 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with outer positioned gate contacts |
US8569841B2 (en) | 2008-03-13 | 2013-10-29 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least one gate level feature extending into adjacent gate level feature layout channel |
US9536899B2 (en) | 2008-03-13 | 2017-01-03 | Tela Innovations, Inc. | Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same |
US8575706B2 (en) | 2008-03-13 | 2013-11-05 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level features inner extensions beyond gate electrode |
US8872283B2 (en) | 2008-03-13 | 2014-10-28 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature |
US8735944B2 (en) | 2008-03-13 | 2014-05-27 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with serially connected transistors |
US8729606B2 (en) | 2008-03-13 | 2014-05-20 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels |
US8729643B2 (en) | 2008-03-13 | 2014-05-20 | Tela Innovations, Inc. | Cross-coupled transistor circuit including offset inner gate contacts |
US10020321B2 (en) | 2008-03-13 | 2018-07-10 | Tela Innovations, Inc. | Cross-coupled transistor circuit defined on two gate electrode tracks |
US8680583B2 (en) | 2008-03-13 | 2014-03-25 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within at least nine gate level feature layout channels |
US8669594B2 (en) | 2008-03-13 | 2014-03-11 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within at least twelve gate level feature layout channels |
US8581303B2 (en) | 2008-03-13 | 2013-11-12 | Tela Innovations, Inc. | Integrated circuit including cross-coupled trasistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset relationships and electrical connection of cross-coupled transistors through same interconnect layer |
US8581304B2 (en) | 2008-03-13 | 2013-11-12 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships |
US8592872B2 (en) | 2008-03-13 | 2013-11-26 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors with two transistors of different type having gate electrodes formed by common gate level feature with shared diffusion regions on opposite sides of common gate level feature |
TWI416710B (en) * | 2008-03-13 | 2013-11-21 | Tela Innovations Inc | Cross-coupled transistor layouts in restricted gate level layout architecture |
US9871056B2 (en) | 2008-03-13 | 2018-01-16 | Tela Innovations, Inc. | Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same |
US8587034B2 (en) | 2008-03-13 | 2013-11-19 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer |
US9779200B2 (en) | 2008-03-27 | 2017-10-03 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
US8759985B2 (en) | 2008-03-27 | 2014-06-24 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
US9390215B2 (en) | 2008-03-27 | 2016-07-12 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
US8471391B2 (en) | 2008-03-27 | 2013-06-25 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
US9122832B2 (en) | 2008-08-01 | 2015-09-01 | Tela Innovations, Inc. | Methods for controlling microloading variation in semiconductor wafer layout and fabrication |
US10446536B2 (en) | 2009-05-06 | 2019-10-15 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
US8863063B2 (en) | 2009-05-06 | 2014-10-14 | Tela Innovations, Inc. | Finfet transistor circuit |
US9563733B2 (en) | 2009-05-06 | 2017-02-07 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
US9530795B2 (en) | 2009-10-13 | 2016-12-27 | Tela Innovations, Inc. | Methods for cell boundary encroachment and semiconductor devices implementing the same |
US9269702B2 (en) | 2009-10-13 | 2016-02-23 | Tela Innovations, Inc. | Methods for cell boundary encroachment and layouts implementing the same |
US8661392B2 (en) | 2009-10-13 | 2014-02-25 | Tela Innovations, Inc. | Methods for cell boundary encroachment and layouts implementing the Same |
US9159627B2 (en) | 2010-11-12 | 2015-10-13 | Tela Innovations, Inc. | Methods for linewidth modification and apparatus implementing the same |
US9704845B2 (en) | 2010-11-12 | 2017-07-11 | Tela Innovations, Inc. | Methods for linewidth modification and apparatus implementing the same |
US9230648B2 (en) * | 2011-04-15 | 2016-01-05 | Semiconductor Energy Laboratory Co., Ltd. | Memory device |
US20120262979A1 (en) * | 2011-04-15 | 2012-10-18 | Semiconductor Energy Laboratory Co., Ltd. | Memory device |
WO2020145555A1 (en) * | 2019-01-08 | 2020-07-16 | 울산과학기술원 | Ternary memory cell and memory device comprising same |
Also Published As
Publication number | Publication date |
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WO2005006343A2 (en) | 2005-01-20 |
US7110275B2 (en) | 2006-09-19 |
US6900999B1 (en) | 2005-05-31 |
CN1849669B (en) | 2011-02-02 |
JP4823901B2 (en) | 2011-11-24 |
JP2007527591A (en) | 2007-09-27 |
TW200514083A (en) | 2005-04-16 |
WO2005006343A3 (en) | 2005-03-24 |
CN1849669A (en) | 2006-10-18 |
TWI266319B (en) | 2006-11-11 |
US20050213360A1 (en) | 2005-09-29 |
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