US20050116317A1 - Inductor for a system-on-a-chip and method for manufacturing the same - Google Patents
Inductor for a system-on-a-chip and method for manufacturing the same Download PDFInfo
- Publication number
- US20050116317A1 US20050116317A1 US10/982,782 US98278204A US2005116317A1 US 20050116317 A1 US20050116317 A1 US 20050116317A1 US 98278204 A US98278204 A US 98278204A US 2005116317 A1 US2005116317 A1 US 2005116317A1
- Authority
- US
- United States
- Prior art keywords
- layer
- inductor
- seed layer
- forming
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 title claims abstract description 165
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 238000009713 electroplating Methods 0.000 claims abstract description 24
- 238000007772 electroless plating Methods 0.000 claims abstract description 20
- 238000003491 array Methods 0.000 claims description 93
- 229920002120 photoresistant polymer Polymers 0.000 claims description 83
- 238000009792 diffusion process Methods 0.000 claims description 54
- 230000002265 prevention Effects 0.000 claims description 53
- 239000000758 substrate Substances 0.000 claims description 53
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 25
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 16
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 16
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 16
- 229910045601 alloy Inorganic materials 0.000 claims description 13
- 239000000956 alloy Substances 0.000 claims description 13
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 11
- 239000010949 copper Substances 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- -1 chlorine ions Chemical class 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 239000010931 gold Substances 0.000 claims description 9
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 8
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 claims description 7
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 7
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 claims description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 229910052759 nickel Inorganic materials 0.000 claims description 7
- 229910052763 palladium Inorganic materials 0.000 claims description 7
- 229910052697 platinum Inorganic materials 0.000 claims description 7
- 229910052709 silver Inorganic materials 0.000 claims description 7
- 239000004332 silver Substances 0.000 claims description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- 229910000365 copper sulfate Inorganic materials 0.000 claims description 6
- 230000003667 anti-reflective effect Effects 0.000 claims description 5
- 238000007747 plating Methods 0.000 claims description 5
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 4
- 239000001569 carbon dioxide Substances 0.000 claims description 4
- 229910002092 carbon dioxide Inorganic materials 0.000 claims description 4
- 239000000460 chlorine Substances 0.000 claims description 4
- 229910052801 chlorine Inorganic materials 0.000 claims description 4
- 229910000040 hydrogen fluoride Inorganic materials 0.000 claims description 4
- 229910017604 nitric acid Inorganic materials 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 235000001674 Agaricus brunnescens Nutrition 0.000 claims description 3
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 238000004140 cleaning Methods 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 342
- 239000010408 film Substances 0.000 description 41
- 238000009413 insulation Methods 0.000 description 31
- 229910052715 tantalum Inorganic materials 0.000 description 14
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 14
- 239000010936 titanium Substances 0.000 description 12
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 9
- 239000002356 single layer Substances 0.000 description 9
- 229910052719 titanium Inorganic materials 0.000 description 9
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 8
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 8
- RVSGESPTHDDNTH-UHFFFAOYSA-N alumane;tantalum Chemical compound [AlH3].[Ta] RVSGESPTHDDNTH-UHFFFAOYSA-N 0.000 description 8
- 238000000635 electron micrograph Methods 0.000 description 8
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 8
- WSFSSNUMVMOOMR-UHFFFAOYSA-N Formaldehyde Chemical compound O=C WSFSSNUMVMOOMR-UHFFFAOYSA-N 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 229910021332 silicide Inorganic materials 0.000 description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 6
- HWEYZGSCHQNNEH-UHFFFAOYSA-N silicon tantalum Chemical compound [Si].[Ta] HWEYZGSCHQNNEH-UHFFFAOYSA-N 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- 239000010937 tungsten Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000007738 vacuum evaporation Methods 0.000 description 3
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 2
- MANYRMJQFFSZKJ-UHFFFAOYSA-N bis($l^{2}-silanylidene)tantalum Chemical compound [Si]=[Ta]=[Si] MANYRMJQFFSZKJ-UHFFFAOYSA-N 0.000 description 2
- 239000003638 chemical reducing agent Substances 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- RNRAZTYOQURAEF-UHFFFAOYSA-N iron tantalum Chemical compound [Fe].[Fe].[Fe].[Fe].[Fe].[Fe].[Fe].[Ta].[Ta].[Ta] RNRAZTYOQURAEF-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
- H01F2017/0046—Printed inductances with a conductive path having a bridge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
- H01F41/02—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets
- H01F41/04—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets for manufacturing coils
- H01F41/041—Printed circuit coils
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
An inductor for a system-on-a-chip and a method for manufacturing the inductor are disclosed. The inductor comprises a conductive line formed by connecting a plurality of conductive patterns grown from a seed layer formed on a lower wiring. The method comprises using an electrolytic plating process or an electroless plating process to grow the plurality of adjacent conductive patterns from the seed layer until they become connected. The method also enables adjusting the height and width of the conductive line to desired levels.
Description
- 1. Field of the Invention
- The present invention relates generally to an inductor and a method for manufacturing the inductor. More particularly, the present invention relates to an inductor for radio frequency (RF) devices for a system-on-a-chip (SOC), and a method for manufacturing the inductor.
- A claim of priority is made to Korean Patent Application No. 2003-78195 filed on Nov. 6, 2003, the disclosure of which is incorporated herein by reference in its entirety.
- 2. Description of the Related Art
- An SOC comprises a single microchip integrating together all of the elements of a system. The elements of the system generally comprise independently operating semiconductor devices or circuits. For example, an SOC for wireless communications typically includes a microprocessor, a digital signal processor (DSP), a random access memory (RAM) device, and a read only memory (ROM). Generally, the elements of an SOC are integrated on a large scale integrated (LSI) circuit or an integrated circuit (IC).
- In an SOC for RF communication, semiconductor devices and RF circuits are generally integrated on a single chip. Inductors are typically formed on integrated circuits of the SOC after the integrated circuits are formed on a semiconductor substrate. A thin film type inductor having a spiral or solenoid construction is commonly employed in an SOC because it is easily combined with integrated circuits. In addition, thin film type inductors are employed for various devices such as a voltage controlled oscillator (VCO), a filter, or a converter.
- A conventional thin film type inductor is disclosed in various international patent publications, including, for example, Korean Laid Open Patent Publication No. 2003-20,603, Korean Patent No. 348,250, and Japanese Laid Open Patent Publication No. 1998-241,983.
-
FIGS. 1A to 1C are cross-sectional views illustrating a method of manufacturing a conventional inductor disclosed in the above-mentioned Korean Laid Open Patent Publication. - Referring to
FIG. 1A , a soft magneticthin film 15 is formed on asubstrate 10 formed on a silicon wafer. Soft magneticthin film 15 has a double-layer structure comprising an iron-tantalum nitride (FeTaN) layer and a titanium (Ti) layer. - An
insulation film 20 of silicon oxide is formed on soft magneticthin film 15 and aseed layer 25 for an electroplating process is formed oninsulation film 20.Seed layer 25 has a double-layer structure comprising a copper (Cu) layer and a chromium (Cr) layer. - A
photosensitive film 30 is deposited on theseed layer 25, and then amask 35 is formed over thephotosensitive film 30. Thephotosensitive film 30 is exposed through a pattern inmask 35. The pattern of themask 35 defines an inductor having a coil structure. - Referring to
FIG. 1B , a plurality of holes are formed through thephotosensitive film 30 by developing the exposed portions of thephotosensitive film 30. The holes expose theseed layer 25 which is positioned beneath thephotosensitive film 30. Acoil 40 of the inductor is formed from theseed layer 25 to fill the holes. Thecoil 40 is formed by an electroplating process using a plating solution including copper. - Referring to
FIG. 1C , thephotosensitive film 30 is removed and portions of theseed layer 25 exposed between the loops of thecoil 40 are etched away using a wet etching process to complete thecoil 40 oninsulation film 20. Thecoil 40 is attached to an uppermagnetic film 50 using anadhesive film 45 of epoxy resin to form the inductor on thesubstrate 10. - In the above-described method for manufacturing a conventional inductor, the rate at which the
coil 40 grows from theseed layer 25 to fill the holes in thephotosensitive film 30 decreases significantly as the size of the holes increases. As the width and height of the inductor increase, the rate of coil growth slows accordingly, thus driving up the time and cost of manufacturing for the inductor and the related RF device. However, it is important for the inductor to have sufficient width and height to ensure the desired electrical characteristics of the inductor. - The present invention provides an inductor for an SOC manufactured according to a simplified process. The present invention also provides a low-cost method for manufacturing an inductor for an SOC using a simplified process.
- According to one aspect of the present invention, an inductor comprises a seed layer formed on a substrate and a conductive line formed on the seed layer. The conductive line is formed by connecting a plurality of conductive patterns grown from the seed layer. A diffusion prevention layer is preferably formed between the substrate and the seed layer, and a protection layer is preferably formed on the conductive line. Additionally, a mold layer including hole arrays is preferably filled with the respective conductive patterns.
- According to another aspect of the present invention, an inductor comprises a substrate including a conductive structure, a seed layer formed on the substrate, a mold layer formed on the seed layer, and a conductive line formed on the seed layer. The mold layer includes hole arrays exposing the seed layer, and the conductive line is electrically connected to the conductive structure. The conductive line is formed by connecting a plurality of conductive patterns grown from the seed layer. A protection layer is preferably formed on the conductive line.
- According to still another aspect of the present invention, an inductor comprises a substrate including a conductive structure, a mold layer including hole arrays having inner surfaces formed on the substrate, a seed layer formed on the inner surfaces of the hole arrays, and a conductive line formed on the seed layer. The conductive line is electrically connected to the conductive structure and is formed by connecting a plurality of conductive patterns grown from the seed layer.
- According to still another aspect of the present invention, an inductor comprises a substrate having a conductive structure, a mold layer including hole arrays having inner surfaces formed on the substrate, a first seed layer formed on the inner surfaces of the hole arrays and on the mold layer, a capping layer formed on the first seed layer, a second seed layer formed on portions of the capping layer positioned in the hole arrays, and a conductive line formed on the second seed layer. The conductive line is electrically connected to the conductive structure and is formed by connecting a plurality of conductive patterns grown from the second seed layer.
- According to still another aspect of the present invention, there is provided a method for manufacturing an inductor. The method comprises forming a mold layer on a seed layer, wherein the mold layer includes hole arrays exposing the seed layer. The method further comprises forming conductive patterns on the mold layer from the seed layer to fill the hole arrays. The method further comprises forming a conductive line on the mold layer by growing the conductive patterns on the mold layer and connecting the conductive patterns. Preferably, the method further comprises forming an anti-reflective layer on the mold layer and forming a protection layer on the conductive line.
- According to still another aspect of the present invention, there is provided a method for manufacturing an inductor. The method comprises forming a mold layer including hole arrays having inner surfaces on a substrate including a conductive structure and forming a diffusion prevention layer on the inner surfaces of the hole arrays and on the mold layer. The method further comprises forming seed layer patterns on portions of the diffusion prevention layer positioned in the hole arrays and forming conductive patterns from the seed layer patterns to fill the hole arrays. The method also further comprises forming a conductive line on the mold layer by growing the conductive patterns on the mold layer and by connecting the conductive patterns and forming a protection layer on the conductive line.
- According to still another aspect of the present invention, there is provided a method for manufacturing an inductor. The method comprises forming a mold layer including hole arrays on a substrate including a conductive structure and forming a diffusion prevention layer on the inner surfaces of the hole arrays and on the mold layer. The method further comprises forming a first seed layer on the diffusion prevention layer, forming a capping layer on the first seed layer, and forming second seed layer patterns on portions of the capping layer positioned in the hole arrays. The method further comprises forming conductive patterns from the second seed layer patterns to fill the hole arrays, growing the conductive patterns on the mold layer and connecting the conductive patterns, thereby forming a conductive line on the mold layer, and forming a protection layer on the conductive line.
- According to the present invention, an inductor including spiral conductive lines may be readily manufactured at relatively low cost by employing an electrolytic process or an electroless plating process. The width and height of the conductive lines are adjusted to desired values by adjusting the growth rate of the conductive patterns using the electrolytic plating process or the electroless plating process. The desired height of the conductive lines is often relatively high compared to the height of a conventional inductor. Adjusting the height of the conductive lines permits the inductor formed by the present invention to have a relatively high spiral structure on the substrate.
- The manufacturing time and cost associated with forming the inductor are potentially reduced by a significant margin because an additional process for electrically connecting the inductor to a lower wiring structure formed on the substrate is not required. Accordingly, the inductor is preferably formed directly on a conventional substrate without any additional process so that an inductor having a relatively high spiral structure is readily formed on the substrate at low cost using a conventional apparatus for manufacturing the inductor.
- The accompanying drawings illustrate several selected embodiments of the present invention. In the drawings:
-
FIGS. 1A to 1C are cross-sectional views illustrating a method for manufacturing a conventional inductor; -
FIG. 2 is a planar view illustrating an exemplary inductor formed in accordance with one aspect of the present invention; -
FIGS. 3A to 3E are cross-sectional views of the inductor shown inFIG. 2 taken along the line from I to I′ inFIG. 2 . -
FIGS. 3A to 3E illustrate a method for manufacturing the inductor shown inFIG. 2 ; -
FIG. 4A is a planar view further illustrating the mask element shown inFIG. 3B ; -
FIG. 4B is a planar view further illustrating a mask for forming conductive patterns according to one aspect of the present invention; -
FIG. 5A is an electron micrograph image illustrating cross-sections of the conductive patterns inFIG. 3C ; -
FIG. 5B is an electron micrograph image illustrating a planar view of the inductor inFIG. 3E ; -
FIG. 6 is a cross-sectional view illustrating an exemplary inductor according to another aspect of the present invention; -
FIGS. 7A to 7E are cross-sectional views illustrating a method for manufacturing the exemplary inductor inFIG. 6 ; -
FIG. 8 is an electron micrograph image illustrating cross-sections of conductive patterns inFIG. 7C ; -
FIGS. 9A to 9E are cross-sectional views illustrating a method for manufacturing an inductor according to yet another aspect of the present invention; -
FIGS. 10A and 10B are electron micrograph images illustrating cross-sections of conductive patterns inFIG. 9D ; -
FIG. 11 is a planar view illustrating an exemplary inductor according to still another aspect of the present invention; -
FIG. 12 is a cross-sectional view illustrating a section of the inductor shown inFIG. 11 taken along the line from II to II′; and, -
FIGS. 13A to 13D are cross-sectional views illustrating a method for manufacturing the inductor inFIG. 12 . - The present invention will now be described more fully with reference to the accompanying drawings, in which several embodiments of the present invention are shown. In the drawings, the thickness of layers and regions are exaggerated for clarity and like reference numerals refer to like elements throughout. It will be understood that when an element such as a layer, region or substrate is referred to as being “on” or “onto” another element, the layer is either directly on the other element or intervening elements may also be present.
-
FIG. 2 is a planar view illustrating an inductor according to one aspect of the present invention. InFIG. 2 , aninductor 200 includes a spiralconductive line 190. The spiralconductive line 190 is electrically connected to acontact 160 formed as a part of a lower wiring element formed on a substrate. Thus, the spiralconductive line 190 is positioned over the lower wiring including thecontact 160 and formed in a spiral structure. Theconductive line 190 is preferably formed by connecting a plurality of conductive patterns grown from a seed layer (not shown). - The
inductor 200 typically includes the seed layer formed over the substrate. A multi-layer structure including an insulating interlayer or a conductive layer is typically formed between the substrate and the seed layer. -
FIGS. 3A to 3E are cross-sectional views taken along a line extending from I to I′ inFIG. 2 .FIGS. 3A to 3E illustrate a method for manufacturing the inductor ofFIG. 2 . - Referring to
FIG. 3A , aninsulation layer 150 is formed on a substrate (not shown) including a lower conductive structure. Anopening 155 is formed through theinsulation layer 150 by partially etching theinsulation layer 150 using a photolithography process. The lower conductive structure typically includes a word line, a bit line, a conductive pattern, and a pad. Theopening 155 exposes a portion of a lower wiring (not shown) electrically connected to the lower conductive structure. - A conductive layer is formed on
insulation layer 150 to fill theopening 155. The conductive layer is typically formed using conductive material such as metal or polysilicon doped with impurities. The conductive layer is partially removed by a chemical mechanical polishing (CMP) process, an etch back process, a combination of a CMP process and an etch back process, or a photolithography process, until theinsulation layer 150 is exposed. As a result of partially removing the conductive layer, acontact 160 electrically connected to the lower wiring is formed in theopening 155. The lower wiring including thecontact 160 is electrically connected to the lower conductive structure positioned on the substrate. - A
diffusion prevention layer 165 is formed on thecontact 160 and theinsulation layer 150. Thediffusion prevention layer 165 typically has a single-layer structure or a multi-layer structure. The single layer structure typically uses tantalum (Ta), tantalum nitride (TaN), tantalum-aluminum nitride (TaAlN), tantalum silicide (TaSi2), titanium (Ti), titanium nitride (TiN), titanium-silicon nitride (TiSiN), or tungsten nitride (WN). The multi-layer structure typically uses a mixture including at least two elements from the group consisting of tantalum (Ta), tantalum nitride (TaN), tantalum-aluminum nitride (TaAlN), tantalum silicide (TaSi2), titanium (Ti), titanium nitride (TiN), titanium-silicon nitride (TiSiN), and tungsten nitride (WN). Thediffusion prevention layer 165 typically has a thickness of about 50 to 1,000 Å. Thediffusion prevention layer 165 prevents copper included in a conductive pattern 185 (seeFIG. 3C ) from diffusing into the underlying structure. - A
seed layer 170 is formed on thediffusion prevention layer 165. Theseed layer 170 is typically formed by a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process such as a sputtering process or a vacuum evaporation process. Preferably, theseed layer 170 is formed by a PVD process and has a thickness of about 100 to 5,000 Å. Alternatively, theseed layer 170 is formed using a conductive material that substantially prevents formation of a surface insulation film such as an oxide film or a nitride film. For example, theseed layer 170 is formed using platinum (Pt), palladium (Pd), nickel (Ni), silver (Ag), gold (Au) or an alloy thereof. - A photoresist film is coated on the
seed layer 170. The photoresist film is exposed to light through amask 220 having a plurality of holes as shown inFIG. 3B . The photoresist film serves as a mold layer for forming theconductive line 190, as shown inFIG. 3D . The photoresist film typically has a thickness of about 500 to 30,000 Å so as to sufficiently grow conductive patterns 185 (See,FIG. 3C ). -
FIG. 4A is a planar view further illustrating themask 220 inFIG. 3B . - Referring to
FIGS. 3B and 4A , themask 220 includes apattern 215 having a plurality of hole arrays arranged in a spiral shape so as to form theinductor 200 having theconductive lines 190. When the photoresist film is exposed using themask 220, the photoresist film forms a plurality of hole arrays in the spiral shape of themask 220. After the exposed photoresist film is developed, aphotoresist pattern 175 including a plurality of trenches orhole arrays 180 arranged in the spiral shape of themask 220 is formed on theseed layer 170. - Although
FIG. 4 shows a pair of spiral-shaped hole arrays formed in themask 220, the number and size of the hole arrays is variable, and it changes in accordance with the size and structure of theinductor 200. -
FIG. 4B is a planar view illustrating amask 230 for forming a conductive line according to one particular embodiment of the present invention. - Referring to
FIG. 4B ,mask 230 includes apattern 225 having a plurality of trenches spirally arranged according to a structure of an inductor. The size and number of trenches varies according to the size and structure of the inductor. - Referring now to
FIG. 3B , the photoresist film is exposed and developed usingmask 220 and as a result, aphotoresist pattern 175 havinghole arrays 180 is formed onseed layer 170. Trenches orhole arrays 180 partially exposeseed layer 170. Trenches orhole arrays 180 preferably have a depth of about 500 to 30,000 Å. - According to one aspect of the present invention an anti-reflective layer (ARL) is formed on the photoresist film so as to ensure a process margin in a photolithography process. The
photoresist pattern 175 is then formed on theseed layer 170 by patterning the photoresist film using the ARL as an etching mask. The ARL typically has a thickness of about 50 to 1,000 Å. - In another aspect of the present invention, an etch-stop layer is formed on the
seed layer 170 in consideration of a successive etching process. Thephotoresist pattern 175 is then formed on the etch-stop layer. The etch-stop layer is typically formed using nitride such as silicon nitride. - Referring to
FIG. 3C , a plurality ofconductive patterns 185 is formed on thephotoresist pattern 175 from theseed layer 170 by an electrolytic plating process to fill trenches orhole arrays 180. The electrolytic plating process is typically performed with a current density of about 20 to 40 mA/cm2 using a plating solution including a copper sulfate (CuSO4) solution, a sulfuric acid (H2SO4) solution, and a solution including chlorine ions (Cl−). Theconductive patterns 185 are grown from theseed layer 170 in a direction indicated by arrows inFIG. 3C so that upper portions of theconductive patterns 185 are formed on thephotoresist pattern 175. When theconductive patterns 185 are grown in thehole arrays 180 from theseed layer 170, growth within thehole arrays 180 accelerates in a vertical direction relative to the substrate, whereas the growth within thehole arrays 180 is limited along a horizontal direction relative to the substrate. Once theconductive patterns 185 fill thehole arrays 180, upper portions of theconductive patterns 185 form protrusions on thephotoresist pattern 175. - Referring to
FIG. 3D , the electrolytic plating process used to form theconductive patterns 185 ofFIG. 3C is extended to formconductive line 190 on thephotoresist pattern 175. In other words, theconductive patterns 185 are vertically and horizontally grown on thephotoresist pattern 175 until theconductive patterns 185 become connected to each other, thus forming theconductive line 190 on thephotoresist pattern 175. When theconductive line 190 is formed by extending the electrolytic plating process, an upper portion of theconductive line 190 typically has a mushroom shape. - A summary of the process used to form the
conductive line 190, including some additional details, is now given. Theconductive patterns 185 are vertically grown from theseed layer 170. Next, theconductive patterns 185 are horizontally and vertically grown on thephotoresist pattern 175 as shown inFIGS. 3C and 3D . Then, adjacentconductive patterns 185 are connected to each other on thephotoresist pattern 175 according to their vertical and horizontal growth, resulting in the formation of theconductive line 190. The width and thickness of theconductive line 190 are adjusted to desired values by adjusting the vertical and horizontal growth of theconductive patterns 185. To achieve this result, the electrolytic plating process is extensively performed to further grow theconductive patterns 185 once they have already filled thehole arrays 180. The further growth causes adjacentconductive patterns 185 to become connected to each other, thus forming theconductive line 190 on thephotoresist pattern 175. In order to form theconductive line 190 with the desired width and thickness, the growth of theconductive patterns 185 is advantageously adjusted after filling thehole arrays 180. Theconductive line 190 preferably has a thickness of about 1,000 to 100,000 Å. Theconductive line 190 typically has a sufficient thickness on thephotoresist pattern 175 because the horizontal growth of theconductive patterns 185 is limited in thehole arrays 180. - Referring to
FIG. 3E , thephotoresist pattern 175 is partially removed except for a portion of thephotoresist pattern 175 positioned beneath theconductive line 190. When thephotoresist pattern 175 is partially removed, theseed layer 170 is partially exposed. The exposedseed layer 170 and thediffusion prevention layer 165 are partially removed to complete theconductive lines 190 having spiral structures. Thephotoresist pattern 175, theseed layer 170 and thediffusion prevention layer 165 are partially removed by a wet etching process. The wet etching process is executed using an organic stripper, a solution including ozone (O3) at a relatively high concentration, or a standard cleaning (SC) solution including carbon dioxide (CO2). Alternatively, thephotoresist pattern 175 may be partially removed by an ashing process and/or a stripping process. In one embodiment of the present invention, theseed layer 170 and thediffusion prevention layer 165 may be partially removed using a mixture of a hydrogen fluoride (HF) solution and a hydrogen peroxide (H2O2) solution or a mixture of a hydrogen fluoride (HF) solution and a nitric acid (HNO3) solution. When the ARL is formed on thephotoresist pattern 175, the ARL and thephotoresist pattern 175 are simultaneously removed. - A
protection layer 195 is formed to enclose theconductive line 190, thereby completing theinductor 200, which preferably comprises a plurality of theconductive lines 190. Theinductor 200 has a spiral structure formed by the plurality of theconductive lines 190. Theprotection layer 195 is typically formed using silicon carbide (SiC) or silicon nitride (SiN). Alternatively, theprotection layer 195 has a multi-layer structure including at least two films of silicon carbide, silicon nitride and silicon oxycarbide. Theprotection layer 195 preferably has a thickness of about 100 to 1,000 Å. Theprotection layer 195 is formed on a sidewall of a remaining portion of thediffusion prevention layer 165, a sidewall of a remaining portion of theseed layer 170, a sidewall of a remaining portion of thephotoresist pattern 175, and on theconductive lines 190 of the spiral structure. -
FIG. 5A is an electron micrograph image displaying cross sections of conductive patterns inFIG. 3C .FIG. 5B is an electron micrograph image showing a plan view of the inductor inFIG. 3E . - Referring to
FIGS. 5A and 5B , theconductive patterns 185 are vertically and horizontally grown by the above-described electrolytic plating process to form theinductor 200 including spiralconductive lines 190 on thephotoresist pattern 175. Each of theconductive patterns 185 has an upper portion with a mushroom shape. -
FIG. 6 is a cross sectional view illustrating an inductor according to one aspect of the present invention. According to this aspect, a method for manufacturing conductive lines comprises processes identical to the processes described with reference toFIGS. 3A to 3D. - Referring to
FIG. 6 , a method for manufacturing aninductor 300 is described. Theinductor 300 is manufactured on a substrate having aninsulation layer 250, which has acontact 260 running through it as previously described. A photoresist pattern for formingconductive lines 290 is completely removed and aseed layer 270 and adiffusion prevention layer 265 are partially removed. Thus, lower portions ofconductive lines 290 are exposed. - A
protection layer 295 is formed on theinsulation layer 250, on sidewalls of the exposedseed layer 270 anddiffusion prevention layer 265, and on theconductive lines 290. Theprotection layer 295 typically has a single-layer structure of silicon carbide, silicon oxycarbide, or silicon nitride or a multi-layer structure having layers chosen from the group consisting of silicon carbide, silicon oxycarbide and silicon nitride. Theprotection layer 295 is formed from the upper portions of theconductive lines 290 to theinsulation layer 265 to thereby entirely enclose theconductive lines 290. -
FIGS. 7A to 7E are cross-sectional views illustrating a method of manufacturing the inductor inFIG. 6 . InFIGS. 7A to 7E, a substrate including a lower conductive structure having word lines, bit lines and pads is not shown. - Referring to
FIG. 7A , aninsulation layer 350 is formed on the substrate. Theinsulation layer 350 is partially etched to form anopening 355 that exposes a lower wiring electrically connected to the lower conductive structure. - A conductive layer is formed on the
insulation layer 350 to fill theopening 355. The conductive layer may be formed using metal or doped polysilicon. The conductive layer is then partially removed by a CMP process, an etch back process or a combination of a CMP process and an etch back process. The conductive layer is partially removed until theinsulation layer 350 is exposed. Thus, acontact 360 electrically connected to the lower wiring is formed in theopening 355. The lower wiring including thecontact 360 is electrically connected to the lower conductive structure formed on the substrate. - A
mold layer 365 is formed on theinsulation layer 350 and thecontact 360. Themold layer 365 may be formed using oxide or photoresist. Themold layer 365 is partially etched to form a plurality of trenches orhole arrays 370 that expose thecontact 360 as described above. Themold layer 365 typically has a thickness of about 500 to 30,000 Å so as to easily form a conductive line 400 (seeFIG. 7D ) and to sufficiently isolate the lower conductive structure from theconductive line 400. - When the
mold layer 365 is formed using oxide, a photoresist film is additionally formed on themold layer 365. The photoresist film is exposed using the mask shown inFIG. 4A orFIG. 4B to form a photoresist pattern including a plurality of hole arrays or trenches. After an ARL having a thickness of about 50 to 1,000 Å is additionally formed on the photoresist film, the photoresist pattern is formed on themold layer 365. Subsequently, themold layer 365 is etched using the photoresist pattern as an etching mask to thereby form trenches orhole arrays 370 having depth of about 500 to 1,000 Å through themold layer 365. - When the
mold layer 365 is formed using photoresist, themold layer 365 is preferably directly exposed using the mask inFIG. 4A orFIG. 4B to thereby form the trenches orhole arrays 370 through themold layer 365, wherein the trenches orhole arrays 370 have inner surfaces. - Referring to
FIG. 7B , adiffusion prevention layer 375 is formed on themold layer 365, on thecontact 360, and on the inner surfaces of the trenches orhole arrays 370. Thediffusion prevention layer 375 has a thickness of about 50 to 1,000 Å. Thediffusion prevention layer 375 typically has a single-layer structure or a multi-layer structure. The single-layer structure typically includes tantalum, tantalum nitride, tantalum-aluminum nitride, tantalum-silicon nitride, tantalum silicide, titanium, titanium nitride, tungsten nitride, titanium-silicon nitride, or an alloy thereof. The multi-layer structure typically includes at least two elements from the group consisting of tantalum, tantalum nitride, tantalum-aluminum nitride, tantalum-silicon nitride, tantalum silicide, titanium, titanium nitride, tungsten nitride, titanium-silicon nitride, and any alloy thereof. - A
first seed layer 380 is formed ondiffusion prevention layer 375 by a CVD process or a PVD process such as a sputtering process or a vacuum evaporation process. Thefirst seed layer 380 has a thickness of about 100 to 5,000 Å. Thefirst seed layer 380 is preferably formed using copper, platinum, palladium, nickel, silver, gold, or an alloy thereof. - A
capping layer 385 is formed on thefirst seed layer 380 using a metal such as aluminum. Thecapping layer 385 has a thickness of about 100 to 500 Å. When a portion of asecond seed layer 390 on themold layer 365 is removed, a metal oxide film is formed on thecapping layer 385 as a result of oxidation in metal in thecapping layer 385. That is, an upper portion of thecapping layer 385 except other portion of thecapping layer 385 formed in thehole arrays 370 is converted into an insulation film of metal oxide so that thecapping layer 385 may selectively restrain growth ofconductive patterns 395. (See,FIG. 7C ). Therefore, theconductive patterns 395 may rapidly grow in thehole arrays 370, whereas theconductive patterns 395 may slowly grow on the metal oxide film of thecapping layer 385. Thesecond seed layer 390 is formed on cappinglayer 385 using copper, platinum, palladium, nickel, silver, gold or an alloy thereof. - Referring to
FIG. 7C , to perform a selective electrolytic plating process, a portion of thesecond seed layer 390 positioned on themold layer 365 is removed by a CMP process, an etch back process or a combination of a CMP process and an etch back process. As a result, the secondseed layer patterns 393 are formed on the inner surfaces of thehole arrays 370. Thediffusion prevention layer 375, thefirst seed layer 380, thecapping layer 385 and the secondseed layer patterns 393 are successively formed on the inner surfaces of thehole arrays 370, whereas the secondseed layer patterns 393 are not formed on themold layer 365. - The
conductive patterns 395 selectively and vertically grow from the secondseed layer patterns 393 to fill thehole arrays 370 using the selective electrolytic plating process. The selective electrolytic plating process is carried out with a current density of about 20 to 40 mA/cm2 using a plating solution that includes a copper sulfate solution, a sulfuric acid solution, and a solution including chlorine ions. As described above, since the horizontal growth of theconductive patterns 395 is limited in thehole arrays 370, theconductive patterns 395 are vertically grown from the secondseed layer patterns 393 in thehole arrays 370. When the selective electrolytic plating process is continually performed, theconductive patterns 395 filling thehole arrays 370 grow horizontally and vertically on themold layer 365. Thecapping layer 385 including the metal oxide film restrains the horizontal growth of theconductive patterns 395 in thehole arrays 370. However, because a bottleneck structure is formed at upper portions of thehole arrays 370 due to thecapping layer 385, theconductive patterns 395 grow horizontally and vertically after thehole arrays 370 are filled withconductive patterns 395. Theconductive patterns 395 filling thehole arrays 370 continuously grow in horizontal and vertical directions as indicated by arrows so that adjacentconductive patterns 395 become connected to one another to form theconductive line 400 having a desired width and height. -
FIG. 8 is an electron micrograph image displaying cross-sections of conductive patterns inFIG. 7C . - As shown in
FIGS. 7C and 8 , although the horizontal growth of theconductive patterns 395 is restrained in thehole arrays 370, theconductive patterns 395 grow both vertically and horizontally after fillinghole arrays 370. As a result, adjacentconductive patterns 395 become connected to one another, thereby forming aconductive line 400. - Referring to
FIG. 7D , theconductive line 400 having a desired width and height is formed on themold layer 365 from the secondseed layer patterns 393 by connecting adjacentconductive patterns 395. Theconductive patterns 395 are connected by continuously performing the electrolytic plating process. After theconductive patterns 395 fill thehole arrays 370, the growth rate of theconductive patterns 395 may be advantageously adjusted to form theconductive line 400 having a height of about 1,000 to 100,000 Å. - Referring to
FIG. 7E , thecapping layer 385, thefirst seed layer 380 and thediffusion prevention layer 375 are partially removed except for portions covered byconductive line 400. Aprotection layer 405 is formed to cover theconductive line 400, thereby forming aninductor 430 having a spiral structure including a plurality ofconductive lines 400. Thecapping layer 385, thefirst seed layer 380 and thediffusion prevention layer 375 may be partially removed using a mixture of a hydrogen fluoride solution and a hydrogen peroxide solution, or a mixture of a hydrogen fluoride solution and a nitric acid solution. - In one embodiment of the present invention, after the
mold layer 365 is removed, theprotection layer 405 is formed on theconductive line 400. When themold layer 365 is formed using photoresist, themold layer 365 is preferably removed using an organic stripper, a solution including ozone at relatively high concentration, or an SC solution including carbon dioxide. When themold layer 365 is formed using oxide, themold layer 365 is preferably removed by a wet etching process using a sulfuric acid solution or a dry etching process such as a reactive ion etching process or a plasma etching process. - Referring now to
FIG. 7E , theprotection layer 405 is preferably formed using silicon carbide or silicon nitride. Theprotection layer 405 has a thickness of about 100 to 1,000 Å. Theprotection layer 405 encloses exposed sidewalls of thecapping layer 385, thefirst seed layer 380 and thediffusion prevention layer 375 beneath theconductive line 400. - In one embodiment of the present invention, the
protection layer 405 has a multi-layer structure including at least elements from the group consisting of silicon carbide, silicon nitride and silicon oxycarbide. -
FIGS. 9A through 9E are cross-sectional views illustrating a method of manufacturing an inductor according to one aspect of the present invention. - Referring to
FIG. 9A , aninsulation layer 450 is formed on a substrate including a lower conductive structure. Theinsulation layer 450 is preferably formed using oxide or nitride. Theinsulation layer 450 is partially etched by a photolithography process and then anopening 455 is formed through theinsulation layer 450. The lower conductive structure typically includes word lines, bit lines and pads. Theopening 455 exposes a lower wiring electrically connected to the lower conductive structure. - A conductive layer of metal or doped polysilicon is formed on the
insulation layer 450 to fill theopening 455. The conductive layer is partially removed by a CMP process, an etch back process, or a combination of a CMP process and an etch back process, thereby forming acontact 460 in theopening 455. Thecontact 460 is electrically connected to the lower wiring. Hence, the lower wiring including thecontact 460 is electrically connected to the lower conductive structure. - A
mold layer 465 having a thickness of about 500 to 30,000 Å is formed on theinsulation layer 450 and thecontact 460. Themold layer 465 may be formed using oxide or photoresist. Themold layer 465 is partially etched to form a plurality of trenches orhole arrays 470 exposing thecontact 460 as described above. The trenches or thehole arrays 470 have depth of about 1,000 to 30,000 Å. - When the
mold layer 465 is formed using oxide, a photoresist film is additionally formed on themold layer 465. The photoresist film is exposed using one of the masks shown inFIG. 4A andFIG. 4B to form a photoresist pattern including a plurality of hole arrays or trenches. An ARL having a thickness of about 50 to 1,000 Å is typically also formed on the photoresist film and then the photoresist pattern is formed on themold layer 465. Subsequently, themold layer 465 is etched using the photoresist pattern as an etching mask to thereby form the trenches orhole arrays 470 through themold layer 465. - When
mold layer 465 is formed using photoresist, themold layer 465 is preferably directly exposed using one of the masks inFIG. 4A andFIG. 4B without forming an additional photoresist film, thereby forming the trenches orhole arrays 470 through themold layer 465, wherein the trenches orhole arrays 470 have inner surfaces. An additional ARL is preferably formed on themold layer 465 to ensure a process margin for a photolithography process. - Referring to
FIG. 9B , adiffusion prevention layer 475 having a thickness of about 50 to 1,000 Å is formed on themold layer 465, onvcontact 460 and on the inner surfaces of thehole arrays 470. Thediffusion prevention layer 475 typically has a single-layer structure or a multi-layer structure. The single-layer structure typically includes tantalum, tantalum nitride, tantalum-aluminum nitride, tantalum-silicon nitride, tantalum silicide, titanium, titanium nitride, tungsten nitride, titanium-silicon nitride, or an alloy thereof. The multi-layer structure typically includes at least two elements from the group consisting of tantalum, tantalum nitride, tantalum-aluminum nitride, tantalum-silicon nitride, tantalum silicide, titanium, titanium nitride, tungsten nitride, titanium-silicon nitride, and any alloy thereof. - A
seed layer 480 having a thickness of about 100 to 5,000 Å is formed on thediffusion prevention layer 475 by a CVD process or a PVD process such as a sputtering process or a vacuum evaporation process. Theseed layer 480 is preferably formed using copper, platinum, palladium, nickel, silver, gold, or an alloy thereof. - Referring to
FIG. 9C ,seed layer patterns 483 are formed on thecontact 460 and on thediffusion prevention layer 475 positioned on the inner surfaces of thehole arrays 470 to achieve a selective electroless plating process. Theseed layer patterns 483 are formed by partially removing theseed layer 480 using a CMP process, an etch back process or a combination of a CMP process and an etch back process until thediffusion prevention layer 475 is exposed. As a result, thediffusion prevention layer 475 and theseed layer patterns 483 are positioned on the inner surfaces of thehole arrays 470, whereas only thediffusion prevention layer 475 is positioned on themold layer 465. - Referring to
FIG. 9D , using the selective electroless plating process,conductive patterns 485 are formed from theseed layer patterns 483 to fill thehole arrays 470. The electroless plating process is carried out using a copper sulfate solution including a reducing agent such as formaldehyde or hydrazine. As described above, since the horizontal growth of theconductive patterns 485 is limited in thehole arrays 470, theconductive patterns 485 are vertically grown from theseed layer patterns 483 in thehole arrays 470. When the electroless plating process is continually performed, theconductive patterns 485 fill thehole arrays 470 and then grow horizontally and vertically on themold layer 465. Theconductive patterns 485 filling thehole arrays 470 continuously grow in the horizontal and vertical directions indicated by arrows so that adjacentconductive patterns 485 become connected to one another to form aconductive line 490 having a desired width and height. -
FIGS. 10A and 10B are electron micrograph images illustrating cross sections ofconductive patterns 485 inFIG. 9D . - Referring to
FIGS. 9D, 10A and 10B, as the electroless plating process proceeds, theconductive patterns 485 grow vertically from theseed layer patterns 483 to fill thehole arrays 470. Then, theconductive patterns 485 grow vertically and horizontally on themold layer 465. In the present embodiment, theconductive patterns 485 are formed by the electroless plating process, causingconductive patterns 485 have relatively dense structures. - Referring to
FIG. 9E , the electroless plating process is continually performed to connect adjacentconductive patterns 485 grown from theseed layer patterns 483. Theconductive patterns 485 grow continuously on themold layer 465 in vertical and horizontal directions and as a result adjacentconductive patterns 485 become connected to one another on themold layer 465. As shown inFIGS. 9D, 10A and 10B, after theconductive patterns 485 grow from theseed layer patterns 483 in the vertical direction, they grow on themold layer 465 in vertical and horizontal directions. Theconductive line 490 is formed by connecting theconductive patterns 485. The growth rate of theconductive patterns 485 is typically adjusted after theconductive patterns 485 fill thehole arrays 470, in order to form theconductive line 490 with a desired width and height. - Referring now to
FIG. 9E , aprotection layer 495 having a thickness of about 100 to 1,000 Å is formed on themold layer 465 to enclose theconductive line 490. Theprotection layer 495 may be formed using silicon carbide or silicon nitride. - A portion of the
protection layer 495 positioned on themold layer 465 is removed to complete theprotection layer 495 enclosing theconductive line 490. As a result, aninductor 500 having spiralconductive lines 490 is formed on the substrate. - In one embodiment of the present invention, after the
mold layer 465 is removed, theprotection layer 495 is formed to enclose theconductive line 490. Since thediffusion prevention layer 475 positioned beneath theconductive line 490 is not removed, a sidewall of thediffusion protection layer 475 is also enclosed by theprotection layer 495. -
FIG. 11 is a planar view illustrating an inductor in accordance with one embodiment of the present invention andFIG. 12 is a cross-sectional view illustrating a section of the inductor inFIG. 11 taken along the line extending from II to II′. - Referring to
FIGS. 11 and 12 , aninductor 600 includes a spiralconductive line 590 directly connected to alower wiring 560 includingpads 570 for input-output of electrical signals. In other words, in theinductor 600, spiralconductive line 590 is directly connected to end portions (pads 570) of thelower wiring 560 without an additional electrical contact connecting it to thelower wiring 560. Omitting the additional electrical contact facilitates a simpler, lower-cost manufacturing processes because it eliminates the need for processes forming the contact. - An
opening 515 is formed through a portion of thelower wiring 560 where the spiralconductive line 590 passes over it so as to prevent the spiralconductive line 590 from connecting to thelower wiring 560. The spiralconductive line 590 is directly connected to the end portions (pads 570) of thelower wiring 560, whereas the spiralconductive line 590 has no contact with thelower wiring 560 because theopening 515 is formed through the portion of thelower wiring 560. -
FIGS. 13A to 13D are cross-sectional views illustrating a method for manufacturing the inductor inFIG. 12 . - Referring to
FIG. 13A , aninsulation layer 550 is formed on a substrate including a lower conductive structure. Theinsulation layer 550 is typically formed using oxide or nitride. - A conductive layer is formed on the
insulation layer 550 using metal or doped polysilicon to form alower wiring 560 on theinsulation layer 560. As shown inFIG. 11 , the conductive layer is patterned to form thelower wiring 560, which is electrically connected to the lower conductive structure. Anopening 515 having a predetermined width is simultaneously formed through a portion of thelower wiring 560 where a spiral conductive line 590 (seeFIG. 13C ) passes over it. Theopening 515 preferably has a width slightly greater than a width of the spiralconductive line 590. - Referring to
FIG. 13B , amold layer 565 having a thickness of about 500 to 30,000 Å is formed on thelower wiring 560 to fill theopening 515. Themold layer 565 may be formed using oxide or photoresist. Themold layer 565 is partially etched to form a plurality of holes that simultaneously expose end portions (that is, pads) of thelower wiring 560 and a portion of theinsulation layer 550 through theopening 515. Each of the holes formed through themold layer 565 has a depth of about 500 to 30,000 Å. As described above, a photoresist film is additionally formed on themold layer 565 when themold layer 565 is formed using oxide. The photoresist film is exposed using a mask substantially similar to that ofFIG. 4A orFIG. 4B to form a photoresist pattern including a plurality of holes. An ARL having a thickness of about 50 to 1,000 Å is typically additionally formed on the photoresist film. Themold layer 565 is then etched using the photoresist pattern as an etching mask to form the holes through themold layer 565. When themold layer 565 is formed using photoresist, themold layer 565 may be directly exposed using a mask substantially similar to that ofFIG. 4A orFIG. 4B without forming an additional photoresist film, thereby forming the holes through themold layer 565, wherein the holes have inner surfaces. An additional ARL may be directly formed on themold layer 565 to ensure a process margin of a photolithography process. - A
diffusion prevention layer 575 having a thickness of about 50 to 1,000 Å is formed on the exposed end portions of thelower wiring 560, on the exposed portion of theinsulation layer 550, on the inner surfaces of the holes, and on themold layer 565. Thediffusion prevention layer 575 typically has a single-layer structure or a multi-layer structure. The single-layer structure typically includes tantalum, tantalum nitride, tantalum-aluminum nitride, tantalum-silicon nitride, tantalum silicide, titanium, titanium nitride, tungsten nitride, titanium-silicon nitride, or an alloy thereof. The multi-layer structure typically includes at least two elements from the group consisting of tantalum, tantalum nitride, tantalum-aluminum nitride, tantalum-silicon nitride, tantalum silicide, titanium, titanium nitride, tungsten nitride, titanium-silicon nitride, and any alloy thereof. - A seed layer having a thickness of about 100 to 5,000 Å is formed on the
diffusion prevention layer 575 by a CVD process or a PVD process. The seed layer is preferably formed using copper, platinum, palladium, nickel, silver, gold, or an alloy thereof. - To achieve a selective electrolytic or electroless plating process,
seed layer patterns 580 are formed on the inner surfaces of the holes and the end portions of thelower wiring 560 by removing a portion of the seed layer positioned onmold layer 565. TheSeed layer patterns 580 may be formed by a CMP process, an etch back process, or a combination of a CMP process and an etch back process. Here, thediffusion prevention layer 575, which is positioned on themold layer 565, is not etched. Hence, theseed layer patterns 580 and thediffusion prevention layer 575 are positioned on the inner surfaces of the holes, whereas only thediffusion prevention layer 575 is positioned on themold layer 565. -
Conductive patterns 585 are formed from theseed layer patterns 580 to fill the holes by a selective electrolytic or electroless plating process. The selective electrolytic plating process is preferably performed with a current density of about 20 to about 40 mA/cm2 using a plating solution that includes a copper sulfate solution, a sulfuric acid solution, and a solution including chlorine ions. The selective electroless plating process is preferably carried out using copper sulfate solution that includes a reducing agent such as formaldehyde or hydrazine. - Because horizontal growth of the
conductive patterns 585 may be limited in the holes, theconductive patterns 585 are vertically grown from theseed layer patterns 580 in the holes. The selective electrolytic or electroless plating process is continuously performed until theconductive patterns 585 fill the holes and then it is continued in order to grow theconductive patterns 585 in horizontal and vertical directions on themold layer 565. Theconductive patterns 585 are continuously grown in horizontal and vertical directions indicated by arrows so that adjacentconductive patterns 585 become connected to one another. - The
conductive patterns 585 are electrically connected to the end portions of thelower wiring 560, whereas theconductive patterns 585 are separated from another portion of thelower wiring 560 due to theopening 515. That is, theconductive patterns 585 are electrically isolated from thelower wiring 560 except for the end portions of thelower wiring 560. As a result, the method of manufacturing an inductor 600 (seeFIG. 13C ) may be simplified and performed at lower cost by omitting an additional process involved in the formation of a contact that electrically connects theconductive patterns 585 to thelower wiring 560. - Referring to
FIG. 13C , as the selective electrolytic or electroless plating process proceeds, after theconductive patterns 585 vertically grow from theseed layer patterns 580 to fill the holes, theconductive patterns 585 grow vertically and horizontally on themold layer 565. As a result, aconductive line 590 having a desired width and height is formed on themold layer 565 from theseed layer patterns 580 by connecting theconductive patterns 585. When theconductive patterns 585 are formed by the selective electroless plating process, theconductive patterns 585 may have relatively dense structures. Particularly, theconductive patterns 585 continuously grow on themold layer 565 in the vertical and horizontal directions so that adjacentconductive patterns 585 are connected to one another on themold layer 565. After theconductive patterns 585 grow vertically from theseed layer patterns 580, they grow vertically and horizontally onmold layer 565. Theconductive line 590 is formed by the horizontal and vertical growth of theconductive patterns 585. The growth rate of theconductive patterns 585 is preferably adjusted after theconductive patterns 585 fill the holes to form theconductive line 590 with a desired width and height on themold layer 565. - Referring now to
FIG. 13D , after a portion of thediffusion prevention layer 575 positioned on themold layer 565 is removed, aprotection layer 595 having a thickness of about 100 to 1,000 Å is formed on themold layer 565 to enclose theconductive line 590. Theprotection layer 595 may be formed using silicon carbide or silicon nitride. Thus, theinductor 600, which has a plurality of spiralconductive lines 590, is formed on the substrate. In one embodiment of the present invention, after themold layer 565 is removed, theprotection layer 595 is formed to entirely enclose theconductive line 590. - In summary, according to the present invention, an inductor including spiral conductive lines may be readily manufactured at a relatively low cost by employing an electrolytic process or an electroless plating process.
- The inductor preferably includes a conductive line having a desired width and height obtained by adjusting a growth rate of conductive patterns grown with the electrolytic plating process or the electroless plating process.
- Because the desired height of the conductive line is typically greater than that of a conventional inductor, the inductor may have a spiral structure characterized by a large height on a substrate.
- The manufacturing time and cost required to form the inductor may be greatly reduced because an additional process typically required to electrically connect the inductor to a lower wiring formed on the substrate is omitted. The inductor may be directly formed on a conventional substrate without any additional process so that the inductor having the large height may be readily formed at low cost on the substrate using a conventional apparatus for manufacturing an inductor.
- The preferred embodiments disclosed in the drawings and the corresponding written description are teaching examples. Those of ordinary skill in the art will understand that various changes in form and details may be made to the exemplary embodiments without departing from the scope of the present invention which is defined by the following claims.
Claims (58)
1. An inductor comprising:
a seed layer formed on a substrate; and
a conductive line formed on the seed layer, wherein the conductive line is formed by a plurality of connected conductive patterns grown from the seed layer.
2. The inductor of claim 1 , further comprising:
a diffusion prevention layer formed between the substrate and the seed layer.
3. The inductor of claim 1 , further comprising:
a protection layer formed on the conductive line.
4. The inductor of claim 3 , wherein the protection layer comprises silicon carbide or silicon nitride.
5. The inductor of claim 3 , wherein the protection layer has a thickness of about 100 to 1,000 Å.
6. The inductor of claim 1 , further comprising:
a mold layer comprising hole arrays respectively filled with one of the plurality of conductive patterns.
7. The inductor of claim 6 , wherein the plurality of conductive patterns filling the hole arrays are connected to one another on the mold layer to form the conductive line.
8. The inductor of claim 6 , wherein the mold layer comprises oxide or photoresist.
9. The inductor of claim 6 , wherein the mold layer has a thickness of about 500 to 30,000 Å.
10. The inductor of claim 6 , wherein each of the hole arrays has a depth of about 500 to 30,000 Å.
11. The inductor of claim 1 , further comprising:
a mold layer comprising trenches respectively filled with one of the plurality of conductive patterns.
12. The inductor of claim 11 , wherein the plurality of conductive patterns filling the trenches are connected to one another on the mold layer to form the conductive line.
13. The inductor of claim 11 , wherein the mold layer comprises oxide or photoresist.
14. The inductor of claim 11 , wherein the mold layer has a thickness of about 500 to 30,000 Å.
15. The inductor of claim 11 , wherein each of the trenches has a depth of about 500 to 30,000 Å.
16. The inductor of claim 1 , wherein the conductive line has a rounded upper portion.
17. An inductor comprising:
a substrate comprising a conductive structure;
a seed layer formed on the substrate;
a mold layer formed on the seed layer, wherein the mold layer includes hole arrays exposing the seed layer; and
a conductive line formed on the seed layer, wherein the conductive line is electrically connected to the conductive structure and is formed by a plurality of connected conductive patterns grown from the seed layer.
18. The inductor of claim 17 , further comprising:
a diffusion prevention layer formed between the substrate and the seed layer.
19. The inductor of claim 17 , further comprising:
a protection layer formed on the conductive line.
20. The inductor of claim 17 , wherein the conductive line has an upper portion having a mushroom shaped structure.
21. An inductor comprising:
a substrate including a conductive structure;
a mold layer formed on the substrate, wherein the mold layer comprises hole arrays having inner surfaces;
a seed layer formed on the inner surfaces of the hole arrays; and
a conductive line formed on the seed layer, wherein the conductive line is electrically connected to the conductive structure and is formed by a plurality of connected conductive patterns grown from the seed layer.
22. The inductor of claim 21 , further comprising:
a diffusion prevention layer formed between the seed layer and the substrate including the conductive structure.
23. The inductor of claim 21 , further comprising:
a protection layer formed on the conductive line.
24. The inductor of claim 21 , wherein the conductive line has a rounded upper portion.
25. An inductor comprising:
a substrate including a conductive structure;
a mold layer formed on the substrate, wherein the mold layer comprises trenches having inner surfaces;
a seed layer formed on the inner surfaces of the hole arrays; and
a conductive line formed on the seed layer, wherein the conductive line is electrically connected to the conductive structure and is formed by a plurality of connected conductive patterns grown from the seed layer.
26. The inductor of claim 25 , further comprising:
a diffusion prevention layer formed between the seed layer and the substrate including the conductive structure.
27. The inductor of claim 25 , further comprising:
a protection layer formed on the conductive line.
28. The inductor of claim 25 , wherein the conductive line has a rounded upper portion.
29. An inductor comprising:
a substrate including a conductive structure;
a mold layer formed on the substrate, wherein the mold layer comprises hole arrays having inner surfaces;
a first seed layer formed on the inner surfaces of the hole arrays and on the mold layer;
a capping layer formed on the first seed layer;
a second seed layer formed on portions of the capping layer positioned in the hole arrays; and,
a conductive line formed on the second seed layer, wherein the conductive line is electrically connected to the conductive structure and is formed by a plurality of connected conductive patterns grown from the second seed layer.
30. The inductor of claim 29 , further comprising:
a diffusion prevention layer formed between the first seed layer and the substrate including the conductive structure, and between the first seed layer and the mold layer.
31. The inductor of claim 29 , wherein the first seed layer comprises an element selected from the group consisting of copper (Cu), platinum (Pt), palladium (Pd), nickel (Ni), silver (Ag), gold (Au) and any alloy thereof.
32. The inductor of claim 29 , wherein the capping layer comprises aluminum (Al).
33. The inductor of claim 32 , wherein the capping layer has a thickness of about 100 to 500 Å.
34. The inductor of claim 29 , wherein the second seed layer comprises an element selected from the group consisting of copper, platinum, palladium, nickel, silver, gold and any alloy thereof.
35. The inductor of claim 29 , further comprising a protection layer formed on the conductive line.
36. The inductor of claim 29 , wherein the conductive line has a rounded upper portion.
37. A method for manufacturing an inductor, comprising:
forming a mold layer on a seed layer, wherein the mold layer comprises hole arrays exposing the seed layer;
forming conductive patterns on the mold layer from the seed layer to fill the hole arrays; and
forming a conductive line on the mold layer by growing the conductive patterns on the mold layer and connecting the conductive patterns.
38. The method of claim 37 , wherein forming the mold layer comprises:
forming a photoresist film on the seed layer; and
forming a photoresist pattern on the seed layer by patterning the photoresist film, wherein the photoresist pattern includes the hole arrays that expose the seed layer.
39. The method of claim 38 , wherein forming the photoresist pattern comprises:
placing a mask over the photoresist film, the mask comprising a pattern having hole arrays arranged substantially in parallel; and,
exposing the photoresist film using the mask.
40. The method of claim 38 , further comprising:
forming an anti-reflective layer on the photoresist film.
41. The method of claim 40 , further comprising:
removing the photoresist pattern and the anti-reflective layer after forming the conductive line.
42. The method of claim 41 , wherein the photoresist pattern and the anti-reflective layer are removed using an organic stripper, a solution including ozone at a relatively high concentration, or a standard cleaning solution including carbon dioxide.
43. The method of claim 37 , wherein forming the mold layer comprises:
forming an oxide layer on the seed layer;
forming a photoresist film on the oxide layer;
forming a photoresist pattern on the oxide layer by patterning the photoresist film; and,
forming the hole arrays through the mold layer by etching the mold layer using the photoresist pattern as an etching mask.
44. The method of claim 37 , further comprising:
forming a diffusion prevention layer between the seed layer and an underlying structure.
45. The method of claim 44 , further comprising:
partially removing the seed layer and the diffusion prevention layer except for portions of the seed layer and the diffusion prevention layer positioned beneath the conductive line after forming the conductive line.
46. The method of claim 45 , wherein the seed layer and the diffusion prevention layer are partially removed using a solution including hydrogen fluoride and hydrogen peroxide or hydrogen fluoride and nitric acid.
47. The method of claim 37 , further comprising:
forming a protection layer on the conductive line.
48. The method of claim 37 , wherein the conductive line is formed by an electrolytic plating process or an electroless plating process.
49. The method of claim 48 , wherein the electrolytic plating process is performed with a current density of about 20 to 40 mA/cm2 using a plating solution including a copper sulfate solution, a sulfuric acid solution and a solution including chlorine ions.
50. A method for manufacturing an inductor, comprising:
forming a mold layer on a seed layer, wherein the mold layer comprises trenches exposing the seed layer;
forming conductive patterns on the mold layer from the seed layer to fill the trenches; and
forming a conductive line on the mold layer by growing the conductive patterns on the mold layer and connecting the conductive patterns.
51. The method of claim 50 , wherein forming the mold layer comprises:
forming a photoresist film on the seed layer; and
forming a photoresist pattern on the seed layer by patterning the photoresist film, wherein the photoresist pattern includes the trenches that expose the seed layer.
52. The method of claim 51 , wherein forming the photoresist pattern comprises:
placing a mask over the photoresist film, the mask comprising a pattern having trenches substantially in parallel; and
exposing the photoresist film using the mask.
53. A method of manufacturing an inductor comprising:
forming a mold layer on a substrate comprising a conductive structure, wherein the mold layer comprises hole arrays having inner surfaces;
forming a diffusion prevention layer on the inner surfaces of the hole arrays and on the mold layer;
forming seed layer patterns on portions of the diffusion prevention layer positioned in the hole arrays;
forming conductive patterns from the seed layer patterns to fill the hole arrays;
forming a conductive line on the mold layer by growing the conductive patterns on the mold layer and by connecting the conductive patterns; and
forming a protection layer on the conductive line.
54. The method of claim 53 , wherein forming the seed layer patterns comprises:
forming a seed layer on the diffusion prevention layer; and
removing portions of the seed layer positioned on the mold layer.
55. The method of claim 54 , wherein removing the portions of the seed layer is performed by a chemical mechanical polishing (CMP) process, an etch back process, or a combination of a CMP process and an etch back process.
56. The method of claim 53 , wherein forming the conductive line is performed by an electrolytic plating process or an electroless plating process.
57. A method of manufacturing an inductor comprising:
forming a mold layer on a substrate comprising a conductive structure, wherein the mold layer comprises hole arrays having inner surfaces;
forming a diffusion prevention layer on the inner surfaces of the hole arrays and on the mold layer;
forming a first seed layer on the diffusion prevention layer;
forming a capping layer on the first seed layer;
forming second seed layer patterns on portions of the capping layer positioned in the hole arrays;
forming conductive patterns from the second seed layer patterns to fill the hole arrays;
forming a conductive line on the mold layer by growing the conductive patterns on the mold layer and by connecting the conductive patterns; and
forming a protection layer on the conductive line.
58. The method of claim 57 , wherein forming the second seed layer patterns comprises:
forming a second seed layer on the capping layer; and
removing portions of the second seed layer positioned on the mold layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/968,787 US7807337B2 (en) | 2003-11-06 | 2008-01-03 | Inductor for a system-on-a-chip and a method for manufacturing the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020030078195A KR100689665B1 (en) | 2003-11-06 | 2003-11-06 | Method for manufacturing an inductor for a System On Chip |
KR2003-78195 | 2003-11-06 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/968,787 Division US7807337B2 (en) | 2003-11-06 | 2008-01-03 | Inductor for a system-on-a-chip and a method for manufacturing the same |
Publications (1)
Publication Number | Publication Date |
---|---|
US20050116317A1 true US20050116317A1 (en) | 2005-06-02 |
Family
ID=34431727
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/982,782 Abandoned US20050116317A1 (en) | 2003-11-06 | 2004-11-08 | Inductor for a system-on-a-chip and method for manufacturing the same |
US11/968,787 Active 2025-01-26 US7807337B2 (en) | 2003-11-06 | 2008-01-03 | Inductor for a system-on-a-chip and a method for manufacturing the same |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/968,787 Active 2025-01-26 US7807337B2 (en) | 2003-11-06 | 2008-01-03 | Inductor for a system-on-a-chip and a method for manufacturing the same |
Country Status (6)
Country | Link |
---|---|
US (2) | US20050116317A1 (en) |
EP (1) | EP1530226B1 (en) |
KR (1) | KR100689665B1 (en) |
CN (1) | CN100495703C (en) |
AT (1) | ATE398332T1 (en) |
DE (1) | DE602004014331D1 (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060158302A1 (en) * | 2005-01-03 | 2006-07-20 | Samsung Electronics Co., Ltd. | Inductor and method of forming the same |
US20080122567A1 (en) * | 2006-08-31 | 2008-05-29 | Jun Su | Spiral inductors on a substrate |
US20080277758A1 (en) * | 2007-05-11 | 2008-11-13 | Seiko Epson Corporation | Semiconductor device and method for manufacturing the same |
US20100093176A1 (en) * | 2008-09-12 | 2010-04-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a sacrificial layer |
US20140097515A1 (en) * | 2011-12-06 | 2014-04-10 | Win Semiconductors Corp. | Compound semiconductor integrated circuit with three-dimensionally formed components |
US8956975B2 (en) | 2013-02-28 | 2015-02-17 | International Business Machines Corporation | Electroless plated material formed directly on metal |
US20150311161A1 (en) * | 2014-04-28 | 2015-10-29 | International Business Machines Corporation | Selective plating without photoresist |
US20170133145A1 (en) * | 2015-11-09 | 2017-05-11 | Samsung Electro-Mechanics Co., Ltd. | Coil component and method of manufacturing the same |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100760915B1 (en) * | 2005-12-29 | 2007-09-21 | 동부일렉트로닉스 주식회사 | Inductor Structure of Semiconductor Device and Method of Fabricating the Same |
KR100737155B1 (en) * | 2006-08-28 | 2007-07-06 | 동부일렉트로닉스 주식회사 | Method of manufactruing high frequency inductor in a semiconductor device |
US20120086101A1 (en) | 2010-10-06 | 2012-04-12 | International Business Machines Corporation | Integrated circuit and interconnect, and method of fabricating same |
JP6102578B2 (en) * | 2012-09-27 | 2017-03-29 | Tdk株式会社 | Anisotropic plating method |
KR101503144B1 (en) * | 2013-07-29 | 2015-03-16 | 삼성전기주식회사 | Thin film type inductor and method of manufacturing the same |
KR101483876B1 (en) * | 2013-08-14 | 2015-01-16 | 삼성전기주식회사 | Inductor element and method of manufacturing the same |
US20180371631A1 (en) * | 2015-11-18 | 2018-12-27 | University Of Houston System | Exposed segmented nanostructure arrays |
US11373803B2 (en) * | 2017-08-11 | 2022-06-28 | Applied Materials, Inc. | Method of forming a magnetic core on a substrate |
SG11202012288PA (en) * | 2018-08-24 | 2021-01-28 | Kioxia Corp | Semiconductor device and method of manufacturing same |
CN113218811B (en) * | 2021-04-30 | 2022-08-05 | 哈尔滨工业大学 | Effectively detect TaSi 2 Method of purity |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6031445A (en) * | 1997-11-28 | 2000-02-29 | Stmicroelectronics S.A. | Transformer for integrated circuits |
US6326673B1 (en) * | 1998-08-07 | 2001-12-04 | Windbond Electronics Corp. | Method and structure of manufacturing a high-Q inductor with an air trench |
US6368484B1 (en) * | 2000-05-09 | 2002-04-09 | International Business Machines Corporation | Selective plating process |
US6872579B2 (en) * | 2002-07-24 | 2005-03-29 | Tdk Corporation | Thin-film coil and method of forming same |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5665251A (en) * | 1994-11-23 | 1997-09-09 | International Business Machines Corporation | RIE image transfer process for plating |
US6010829A (en) * | 1996-05-31 | 2000-01-04 | Texas Instruments Incorporated | Polysilicon linewidth reduction using a BARC-poly etch process |
KR100211030B1 (en) * | 1996-12-21 | 1999-07-15 | 정선종 | Inductor device having mos transistor using muti-layer metal interconnection |
JPH10241983A (en) * | 1997-02-26 | 1998-09-11 | Toshiba Corp | Plane inductor element and its manufacturing method |
FI971180A (en) * | 1997-03-20 | 1998-12-23 | Micronas Oy | Stripe-line inductor |
US6117784A (en) | 1997-11-12 | 2000-09-12 | International Business Machines Corporation | Process for integrated circuit wiring |
KR100337950B1 (en) | 1998-09-15 | 2002-10-04 | 한국과학기술원 | Monolithic Manufacturing Method of Solenoid Inductors |
US6610596B1 (en) * | 1999-09-15 | 2003-08-26 | Samsung Electronics Co., Ltd. | Method of forming metal interconnection using plating and semiconductor device manufactured by the method |
KR100348250B1 (en) | 1999-10-11 | 2002-08-09 | 엘지전자 주식회사 | fabrication method for micro passive element |
KR100324209B1 (en) | 2000-01-28 | 2002-02-16 | 오길록 | Fabrication method of silver inductors |
JP2002110453A (en) | 2000-09-28 | 2002-04-12 | Kyocera Corp | Thin-film electronic part and substrate |
KR100368930B1 (en) | 2001-03-29 | 2003-01-24 | 한국과학기술원 | Three-Dimensional Metal Devices Highly Suspended above Semiconductor Substrate, Their Circuit Model, and Method for Manufacturing the Same |
US6905950B2 (en) * | 2001-06-27 | 2005-06-14 | Advanced Micro Devices, Inc. | Growing copper vias or lines within a patterned resist using a copper seed layer |
US6667536B2 (en) * | 2001-06-28 | 2003-12-23 | Agere Systems Inc. | Thin film multi-layer high Q transformer formed in a semiconductor substrate |
KR20030002204A (en) * | 2001-06-30 | 2003-01-08 | 주식회사 하이닉스반도체 | Method for forming the multi spiral inductor in semiconductor device |
KR100440810B1 (en) | 2001-09-04 | 2004-07-21 | 한국전기연구원 | Method for manufacturing a planar inductor having low coil loss |
US6646347B2 (en) * | 2001-11-30 | 2003-11-11 | Motorola, Inc. | Semiconductor power device and method of formation |
US6750750B2 (en) * | 2001-12-28 | 2004-06-15 | Chartered Semiconductor Manufacturing Ltd. | Via/line inductor on semiconductor material |
US6444517B1 (en) * | 2002-01-23 | 2002-09-03 | Taiwan Semiconductor Manufacturing Company | High Q inductor with Cu damascene via/trench etching simultaneous module |
KR100476708B1 (en) * | 2002-12-27 | 2005-03-17 | 매그나칩 반도체 유한회사 | Method of forming inductor |
US6897152B2 (en) * | 2003-02-05 | 2005-05-24 | Enthone Inc. | Copper bath composition for electroless and/or electrolytic filling of vias and trenches for integrated circuit fabrication |
KR100558002B1 (en) * | 2003-09-26 | 2006-03-06 | 삼성전자주식회사 | method of forming metal pattern using selective electro plating process |
-
2003
- 2003-11-06 KR KR1020030078195A patent/KR100689665B1/en not_active IP Right Cessation
-
2004
- 2004-11-05 EP EP04026262A patent/EP1530226B1/en not_active Not-in-force
- 2004-11-05 AT AT04026262T patent/ATE398332T1/en not_active IP Right Cessation
- 2004-11-05 DE DE602004014331T patent/DE602004014331D1/en active Active
- 2004-11-08 CN CNB2004100104187A patent/CN100495703C/en not_active Expired - Fee Related
- 2004-11-08 US US10/982,782 patent/US20050116317A1/en not_active Abandoned
-
2008
- 2008-01-03 US US11/968,787 patent/US7807337B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6031445A (en) * | 1997-11-28 | 2000-02-29 | Stmicroelectronics S.A. | Transformer for integrated circuits |
US6326673B1 (en) * | 1998-08-07 | 2001-12-04 | Windbond Electronics Corp. | Method and structure of manufacturing a high-Q inductor with an air trench |
US6368484B1 (en) * | 2000-05-09 | 2002-04-09 | International Business Machines Corporation | Selective plating process |
US6872579B2 (en) * | 2002-07-24 | 2005-03-29 | Tdk Corporation | Thin-film coil and method of forming same |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7236081B2 (en) * | 2005-01-03 | 2007-06-26 | Samsung Electronics, Co., Ltd. | Inductor and method of forming the same |
US20070216510A1 (en) * | 2005-01-03 | 2007-09-20 | Samsung Electronics Co., Ltd. | Inductor and method of forming the same |
US7405643B2 (en) | 2005-01-03 | 2008-07-29 | Samsung Electronics Co., Ltd. | Inductor and method of forming the same |
US20060158302A1 (en) * | 2005-01-03 | 2006-07-20 | Samsung Electronics Co., Ltd. | Inductor and method of forming the same |
US20080122567A1 (en) * | 2006-08-31 | 2008-05-29 | Jun Su | Spiral inductors on a substrate |
US7714410B2 (en) * | 2007-05-11 | 2010-05-11 | Seiko Epson Corporation | Semiconductor device |
US20080277758A1 (en) * | 2007-05-11 | 2008-11-13 | Seiko Epson Corporation | Semiconductor device and method for manufacturing the same |
US20100093176A1 (en) * | 2008-09-12 | 2010-04-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a sacrificial layer |
US8183162B2 (en) * | 2008-09-12 | 2012-05-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a sacrificial layer |
TWI409871B (en) * | 2008-09-12 | 2013-09-21 | Taiwan Semiconductor Mfg | Method of forming a sacrificial layer |
US20140097515A1 (en) * | 2011-12-06 | 2014-04-10 | Win Semiconductors Corp. | Compound semiconductor integrated circuit with three-dimensionally formed components |
US8956975B2 (en) | 2013-02-28 | 2015-02-17 | International Business Machines Corporation | Electroless plated material formed directly on metal |
US20150311161A1 (en) * | 2014-04-28 | 2015-10-29 | International Business Machines Corporation | Selective plating without photoresist |
US20170133145A1 (en) * | 2015-11-09 | 2017-05-11 | Samsung Electro-Mechanics Co., Ltd. | Coil component and method of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
CN1624916A (en) | 2005-06-08 |
KR20050043341A (en) | 2005-05-11 |
US7807337B2 (en) | 2010-10-05 |
EP1530226A3 (en) | 2006-10-25 |
KR100689665B1 (en) | 2007-03-08 |
DE602004014331D1 (en) | 2008-07-24 |
US20080102409A1 (en) | 2008-05-01 |
CN100495703C (en) | 2009-06-03 |
EP1530226A2 (en) | 2005-05-11 |
ATE398332T1 (en) | 2008-07-15 |
EP1530226B1 (en) | 2008-06-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7807337B2 (en) | Inductor for a system-on-a-chip and a method for manufacturing the same | |
US6492722B1 (en) | Metallized interconnection structure | |
CN108461477B (en) | Metal interconnect for ultra (skip) via integration | |
US6649464B2 (en) | Method for manufacturing semiconductor device having capacitor and via contact | |
JP5255292B2 (en) | Interconnect structure having two-layer metal cap and method of manufacturing the same | |
US7842600B2 (en) | Methods of forming interlayer dielectrics having air gaps | |
US7410894B2 (en) | Post last wiring level inductor using patterned plate process | |
US20070167005A1 (en) | Selective electroless-plated copper metallization | |
US20050009333A1 (en) | Methods of forming metal layers in integrated circuit devices using selective deposition on edges of recesses | |
JP5334616B2 (en) | Method for making an interconnect | |
US20070117378A1 (en) | Method of forming a trench for use in manufacturing a semiconductor device | |
EP1238400A2 (en) | Semiconductor inductor and methods for making the same | |
JP2005340808A (en) | Barrier structure of semiconductor device | |
JP2009135518A (en) | Mutual connection manufacturing method | |
EP0248668A2 (en) | Process for fabricating multilevel metal integrated circuits and structures produced thereby | |
US7955971B2 (en) | Hybrid metallic wire and methods of fabricating same | |
US6458690B2 (en) | Method for manufacturing a multilayer interconnection structure | |
KR20050081008A (en) | Method of manufacturing an inductor | |
JP2001044280A (en) | Multilayer wiring structure and manufacture thereof | |
US20090051005A1 (en) | Method of fabricating inductor in semiconductor device | |
US6841471B2 (en) | Fabrication method of semiconductor device | |
KR100545196B1 (en) | Method for forming metal line of semiconductor device | |
US11189528B2 (en) | Subtractive RIE interconnect | |
WO2023109316A1 (en) | Dual-metal ultra thick metal (utm) structure | |
KR100595396B1 (en) | method of forming metal line of semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, HYO-JONG;SON, HONG-SEONG;LEE, UI-HYOUNG;AND OTHERS;REEL/FRAME:015974/0979 Effective date: 20041103 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |