US20050041518A1 - Method and system for supporting multiple cache configurations - Google Patents
Method and system for supporting multiple cache configurations Download PDFInfo
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- US20050041518A1 US20050041518A1 US10/959,798 US95979804A US2005041518A1 US 20050041518 A1 US20050041518 A1 US 20050041518A1 US 95979804 A US95979804 A US 95979804A US 2005041518 A1 US2005041518 A1 US 2005041518A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
- G06F2212/601—Reconfiguration of cache memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2245—Memory devices with an internal cache buffer
Definitions
- SRAM 20 a static random access memory 20 a
- SRAM 20 b static random access memory 20 b
- SRAM 20 a and SRAM 20 b are identical memory devices. Specifically, both SRAM 20 a and SRAM 20 b have an identical pin arrangement including seven (7) rows and seventeen (17) columns of pins. The first column of pins are shown in FIG. 1 . In the first column of pins, SRAM 20 a includes two (2) output power supply pins 21 a and 27 a, and SRAM 20 b includes two (2) output power supply pins 21 b and 27 b.
- SRAM 20 a includes four (4) synchronous address input pins 22 a, 23 a, 25 a, and 26 a
- SRAM 20 b includes four (4) synchronous address input pins 22 b, 23 b, 25 b, and 26 b.
- Pin 24 a of SRAM 20 a and pin 24 b of SRAM 20 b are not utilized.
- SRAM 20 a is mounted to a front side of a processor card 10
- SRAM 20 b is mounted to a rear side of processor card 10
- SRAM 20 a and SRAM 20 b are positioned with an alignment of pin 21 a and pin 27 b, an alignment of pin 22 a and pin 26 b, an alignment of pin 23 a and pin 25 b, an alignment of pin 24 a and pin 24 b, an alignment of pin 25 a and pin 23 b, an alignment of pin 26 a and pin 22 b, and an alignment of pin 27 a and pin 21 b.
- Pin 22 a and pin 22 b are functionally equivalent and electrically coupled via a conductor 28 a within processor card 10 to concurrently receive a first address bit signal from a microprocessor.
- Pin 23 a and pin 23 b are functionally equivalent and electrically coupled via a conductor 28 b within processor card 10 to concurrently receive a second address bit signal from the microprocessor.
- Pin 25 a and pin 25 b are functionally equivalent and electrically coupled via a conductor 28 c within processor card 10 to concurrently receive a third address bit signal from the microprocessor.
- Pin 26 a and pin 26 b are functionally equivalent and electrically coupled via a conductor 28 d within processor card 10 to concurrently receive a fourth address bit signal from the microprocessor.
- the four (4) address bits signal are selectively provided by the microprocessor as a function of a selected cache configuration.
- a drawback associated with the aforementioned electrical couplings as shown is the length of conductors 28 a - 28 d tends to establish a maximum frequency at which the microprocessor can effectively and efficiently control SRAM 20 a and SRAM 20 b, and the established maximum frequency can be significantly lower than a desired operating frequency of the microprocessor.
- the computer industry is therefore continually striving to improve upon the electrical coupling between the synchronous address input pins of SRAM 20 a and SRAM 20 b whereby a maximum frequency at which a microprocessor can effectively and efficiently control SRAM 20 a and SRAM 20 b matches a desired operating frequency of the microprocessor.
- the computer industry is also continually striving to improve upon the electrical communication of a selected cache configuration from a microprocessor to the synchronous address input pins of SRAM 20 a and SRAM 20 b.
- the present invention generally relates to computer hardware mounted upon a processor card, and in particular to an electrical coupling between memory components for supporting multiple cache configurations and an electrical communication from a microprocessor to the memory components for selecting one of the supported multiple cache configurations.
- One form of the present invention is a processor card having a first memory device and a second memory device mounted thereon.
- the first memory device includes a first address pin and a second address pin.
- the second memory device includes a third address pin and a fourth address pin.
- the first address pin of the first memory device and the third address pin of the second memory device are functionally equivalent address pins.
- the second address pin of the first memory device and the fourth address pin are functionally equivalent address pins.
- the first address pin of the first memory device and the fourth address pin of the second memory device are electrically coupled to thereby concurrently receive a first address bit signal.
- the second address pin of the first memory device and the third address pin of the second memory device are electrically coupled to thereby concurrently receive a second address bit signal.
- Another form of the present invention is a system including a first memory device, a second memory device, and a microprocessor.
- the first memory device includes a first address pin and a second address pin.
- the second memory device includes a third address pin and a fourth address pin.
- the first address pin of the first memory device and the third address pin of the second memory device are functionally equivalent address pins.
- the second address pin of the first memory device and the fourth address pin are functionally equivalent address pins.
- the microprocessor is operable to concurrently provide a first address bit signal to first address pin of the first memory device and the fourth address pin of the second memory device.
- the microprocessor is further operable to concurrently provide a first address bit signal to second address pin of the first memory device and the third address pin of the second memory device.
- FIG. 1 is a fragmented side view of a processor card having a pair of static random accesses memories mounted thereon with an electrical coupling of synchronous address pins as known in the art;
- FIG. 2 is view of the FIG. 1 processor card and FIG. I static random accesses memories with an electrical coupling of synchronous address pins in accordance with the present invention
- FIG. 3A is a general block diagram of a first embodiment of a microprocessor in accordance with the present invention.
- FIG. 3B is a general block diagram of a second embodiment of a microprocessor in accordance with the present invention.
- FIG. 3C is a general block diagram of one embodiment of a microprocessor in accordance with the present invention.
- SRAM 20 a and SRAM 20 b are mounted upon processor card 10 as previously described in connection with FIG. 1 .
- pin 22 a and pin 26 b are electrically coupled via a conductor 29 a within processor card 10 to concurrently receive a first address bit signal.
- Pin 23 a and pin 25 b are electrically coupled via a conductor 29 b within processor card 10 to concurrently receive a second address bit signal.
- Pin 25 a and pin 23 b are electrically coupled via a conductor 29 c within processor card 10 to concurrently receive a third address bit signal.
- Pin 26 a and pin 22 b are electrically coupled via a conductor 29 d within processor card 10 to concurrently receive a fourth address bit signal.
- the length of the conductors 29 a - 29 d facilitate an effective and efficient operation of SRAM 20 a and SRAM 20 b over a wide range of operating frequencies of a microprocessor.
- Microprocessor 30 in accordance with the present invention for selecting between two (2) of the four (4) cache configurations supported by SRAM 20 a and SRAM 20 b is shown.
- Microprocessor 30 includes main logic units 31 for interpreting and executing operating and application programs as would occur to one skilled in the art.
- Microprocessor 30 further includes a controller 32 and a multiplexer 33 .
- Address bus 32 a and address bus 32 b provide electrical communication between controller 32 and multiplexer 33 .
- Address bus 32 a and address bus 32 b each have two (2) address lines.
- Multiplexer 33 has an address bus 33 a with a first address line electrically coupled to pin 22 a ( FIG. 2 ) and pin 26 b ( FIG.
- Table 1 exemplary illustrates an address bit logic utilized by main logic units 31 for electrically communicating a selected cache configuration between an 8 Mbyte cache and a 16 Mbyte cache to SRAM 20 a and SRAM 20 b.
- MSB FIRST SECOND ADDRESS CACHE ADDRESS ADDRESS BUS SIZE LINE (MSB) LINE (LSB) 32a 8 Mbyte net2 net2 32b 16 Mbyte net1 net2
- microprocessor 30 further comprises a configuration register 34 .
- Configuration register 34 provides a control signal to multiplexor 33 via a control bus 34 a in response to a selection signal from main logic units 31 via a data bus 31 a.
- the selection signal is indicative of a selected cache configuration by main logic units 31 during an initial boot of microprocessor 30 .
- the control signal is indicative of the address bus that corresponds to the selected cache configuration. Consequently, multiplexor 33 provides the appropriate address signals via address bus 33 a to SRAM 20 a and SRAM 20 b in response to the selection signal.
- pin 22 a and pin 26 b concurrently receive address signal net1
- pin 26 a and pin 22 b concurrently receive address signal net2 as indicated by Table 1.
- Microprocessor 40 in accordance with the present invention for selecting between three (3) of the four (4) cache configurations supported by SRAM 20 a and SRAM 20 b is shown.
- Microprocessor 40 includes main logic units 41 for interpreting and executing operating and application programs as would occur to one skilled in the art.
- Microprocessor 40 further includes a controller 42 and a multiplexer 43 .
- Address bus 42 a, address bus 42 b, and address bus 42 c provide electrical communication between controller 42 and multiplexer 43 .
- Address bus 42 a address bus 42 b, and address bus 42 c each have three (3) address lines.
- Multiplexer 43 has an address bus 43 a with a first address line electrically coupled to pin 22 a ( FIG.
- Table 2 exemplary illustrates the address bit logic utilized by main logic units 41 for electrically communicating a selected cache configuration between a 4 Mbyte cache, an 8 Mbyte cache and a 16 Mbyte cache to SRAM 20 a and SRAM 20 b.
- microprocessor 40 further comprises a configuration register 44 .
- Configuration register 44 provides a control signal to multiplexor 43 via a control bus 44 a in response to a selection signal from main logic units 41 via a data bus 41 a.
- the selection signal is indicative of a selected cache configuration by main logic units 41 during an initial boot of microprocessor 40 .
- the control signal is indicative of the address bus that corresponds to the selected cache configuration. Consequently, multiplexor 43 provides the appropriate address signals via address bus 43 a to SRAM 20 a and SRAM 20 b in response to the selection signal.
- pin 22 a and pin 26 b concurrently receive address signal net2
- pin 26 a and pin 22 b concurrently receive address signal net2
- pin 23 a and pin 25 b concurrently receive address signal net3 as indicated by Table 2.
- Microprocessor 50 in accordance with the present invention for selecting between all four (4) cache configurations supported by SRAM 20 a and SRAM 20 b is shown.
- Microprocessor 50 includes main logic units 51 for interpreting and executing operating and application programs as would occur to one skilled in the art.
- Microprocessor 50 further includes a controller 52 and a multiplexer 53 .
- Address bus 52 a, address bus 52 b, address bus 52 c, and address bus 52 d provide electrical communication between controller 52 and multiplexer 53 .
- Address bus 52 a address bus 52 b, address bus 52 c, and address bus 52 d each have four (4) address lines.
- Multiplexer 53 has an address bus 53 a with a first address line electrically coupled to pin 22 a ( FIG.
- Table 3 exemplary illustrates the address bit logic utilized by main logic units 51 for electrically communicating a selected cache configuration between a 2 Mbyte cache, a 4 Mbyte cache, an 8 Mbyte cache and a 16 Mbyte cache to SRAM 20 a and SRAM 20 b.
- microprocessor 50 further comprises a configuration register 54 .
- Configuration register 54 provides a control signal to multiplexor 53 via a control bus 54 a in response to a selection signal from main logic units 51 via a data bus 51 a.
- the selection signal is indicative of a selected cache configuration by main logic units 51 during an initial boot of microprocessor 50 .
- the control signal is indicative of the address bus that corresponds to the selected cache configuration. Consequently, multiplexor 53 provides the appropriate address signals via address bus 53 a to SRAM 20 a and SRAM 20 b in response to the selection signal.
- pin 22 a and pin 26 b concurrently receive address signal net2
- pin 26 a and pin 22 b concurrently receive address signal net2
- pin 23 a and pin 25 b concurrently receive address signal net3
- pin 23 b and pin 25 a concurrently receive address signal net4 as indicated by Table 3.
- SRAM 20 a and SRAM 20 b herein in connection with FIG. 2 one skilled in the art will know how to make and use electrical couplings between additional synchronous address pins of SRAM 20 a and SRAM 20 b in accordance with the present invention.
- microprocessors 30 , 40 , and 50 in connection with FIGS. 3A-3C respectively, one skilled in the art will know how to make and use microprocessors in accordance with the present invention for selecting a cache configuration between five or more supported cache configurations.
- SRAM 20 a and SRAM 20 b can vary, and/or SRAM 20 a and SRAM 20 b may include asynchronous address pins. Additionally, SRAM 20 a and SRAM 20 b may be misaligned along the respective sides of processor card 10 , and/or mounted on the same side of processor card 10 . Also, other memory devices may be utilized in lieu of SRAM 20 a and SRAM 20 b, e.g. dynamic static random access memories.
Abstract
A processor card for supporting multiple cache configurations, and a microprocessor for selecting one of the multiple cache configurations is disclosed. The processor card has a first static random access memory mounted on a front side thereof and a second static random access memory mounted on a rear side thereof. The address pins of the memories are aligned. Each pair of aligned address pins are electrically coupled to thereby concurrently receive an address bit signal from the microprocessor. During an initial boot of the microprocessor, the microprocessor includes a multiplexor for providing the address bit signals to the address pins in response to a control signal indicative of a selected cache configuration.
Description
- Referring to
FIG. 1 , an electrical coupling network between a staticrandom access memory 20 a (hereinafter “SRAM 20 a”) and a staticrandom access memory 20 b (hereinafter “SRAM 20b”) is shown. SRAM 20 a and SRAM 20 b are identical memory devices. Specifically, bothSRAM 20 a andSRAM 20 b have an identical pin arrangement including seven (7) rows and seventeen (17) columns of pins. The first column of pins are shown inFIG. 1 . In the first column of pins, SRAM 20 a includes two (2) outputpower supply pins power supply pins SRAM 20 a includes four (4) synchronousaddress input pins SRAM 20 b includes four (4) synchronousaddress input pins Pin 24 a ofSRAM 20 a andpin 24 b ofSRAM 20 b are not utilized. - In support of four (4) cache configurations, SRAM 20 a is mounted to a front side of a
processor card 10, and SRAM 20 b is mounted to a rear side ofprocessor card 10.SRAM 20 a andSRAM 20 b are positioned with an alignment ofpin 21 a andpin 27 b, an alignment ofpin 22 a andpin 26 b, an alignment ofpin 23 a andpin 25 b, an alignment ofpin 24 a andpin 24 b, an alignment ofpin 25 a andpin 23 b, an alignment ofpin 26 a andpin 22 b, and an alignment ofpin 27 a andpin 21 b. -
Pin 22 a andpin 22 b are functionally equivalent and electrically coupled via aconductor 28 a withinprocessor card 10 to concurrently receive a first address bit signal from a microprocessor.Pin 23 a andpin 23 b are functionally equivalent and electrically coupled via aconductor 28 b withinprocessor card 10 to concurrently receive a second address bit signal from the microprocessor.Pin 25 a andpin 25 b are functionally equivalent and electrically coupled via aconductor 28 c withinprocessor card 10 to concurrently receive a third address bit signal from the microprocessor.Pin 26 a andpin 26 b are functionally equivalent and electrically coupled via aconductor 28 d withinprocessor card 10 to concurrently receive a fourth address bit signal from the microprocessor. The four (4) address bits signal are selectively provided by the microprocessor as a function of a selected cache configuration. - A drawback associated with the aforementioned electrical couplings as shown is the length of conductors 28 a-28 d tends to establish a maximum frequency at which the microprocessor can effectively and efficiently control
SRAM 20 a andSRAM 20 b, and the established maximum frequency can be significantly lower than a desired operating frequency of the microprocessor. The computer industry is therefore continually striving to improve upon the electrical coupling between the synchronous address input pins ofSRAM 20 a andSRAM 20 b whereby a maximum frequency at which a microprocessor can effectively and efficiently controlSRAM 20 a andSRAM 20 b matches a desired operating frequency of the microprocessor. The computer industry is also continually striving to improve upon the electrical communication of a selected cache configuration from a microprocessor to the synchronous address input pins ofSRAM 20 a andSRAM 20 b. - The present invention generally relates to computer hardware mounted upon a processor card, and in particular to an electrical coupling between memory components for supporting multiple cache configurations and an electrical communication from a microprocessor to the memory components for selecting one of the supported multiple cache configurations.
- One form of the present invention is a processor card having a first memory device and a second memory device mounted thereon. The first memory device includes a first address pin and a second address pin. The second memory device includes a third address pin and a fourth address pin. The first address pin of the first memory device and the third address pin of the second memory device are functionally equivalent address pins. The second address pin of the first memory device and the fourth address pin are functionally equivalent address pins. The first address pin of the first memory device and the fourth address pin of the second memory device are electrically coupled to thereby concurrently receive a first address bit signal. The second address pin of the first memory device and the third address pin of the second memory device are electrically coupled to thereby concurrently receive a second address bit signal.
- Another form of the present invention is a system including a first memory device, a second memory device, and a microprocessor. The first memory device includes a first address pin and a second address pin. The second memory device includes a third address pin and a fourth address pin. The first address pin of the first memory device and the third address pin of the second memory device are functionally equivalent address pins. The second address pin of the first memory device and the fourth address pin are functionally equivalent address pins. The microprocessor is operable to concurrently provide a first address bit signal to first address pin of the first memory device and the fourth address pin of the second memory device. The microprocessor is further operable to concurrently provide a first address bit signal to second address pin of the first memory device and the third address pin of the second memory device.
- The foregoing and other features and advantages of the invention will become further apparent from the following detailed description of the presently preferred embodiments, read in conjunction with the accompanying drawings. The detailed description and drawings are merely illustrative of the invention rather than limiting, the scope of the invention being defined by the appended claims and equivalents thereof.
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FIG. 1 is a fragmented side view of a processor card having a pair of static random accesses memories mounted thereon with an electrical coupling of synchronous address pins as known in the art; -
FIG. 2 is view of theFIG. 1 processor card and FIG. I static random accesses memories with an electrical coupling of synchronous address pins in accordance with the present invention; -
FIG. 3A is a general block diagram of a first embodiment of a microprocessor in accordance with the present invention; -
FIG. 3B is a general block diagram of a second embodiment of a microprocessor in accordance with the present invention; and -
FIG. 3C is a general block diagram of one embodiment of a microprocessor in accordance with the present invention. - Referring to
FIG. 2 , SRAM 20 a and SRAM 20 b are mounted uponprocessor card 10 as previously described in connection withFIG. 1 . In accordance with the present invention,pin 22 a andpin 26 b are electrically coupled via aconductor 29 a withinprocessor card 10 to concurrently receive a first address bit signal.Pin 23 a andpin 25 b are electrically coupled via aconductor 29 b withinprocessor card 10 to concurrently receive a second address bit signal.Pin 25 a andpin 23 b are electrically coupled via aconductor 29 c withinprocessor card 10 to concurrently receive a third address bit signal.Pin 26 a andpin 22 b are electrically coupled via aconductor 29 d withinprocessor card 10 to concurrently receive a fourth address bit signal. The length of the conductors 29 a-29 d facilitate an effective and efficient operation ofSRAM 20 a andSRAM 20 b over a wide range of operating frequencies of a microprocessor. - Referring to
FIG. 3A , amicroprocessor 30 in accordance with the present invention for selecting between two (2) of the four (4) cache configurations supported by SRAM 20 a and SRAM 20 b is shown.Microprocessor 30 includesmain logic units 31 for interpreting and executing operating and application programs as would occur to one skilled in the art.Microprocessor 30 further includes acontroller 32 and amultiplexer 33.Address bus 32 a andaddress bus 32 b provide electrical communication betweencontroller 32 andmultiplexer 33.Address bus 32 a andaddress bus 32 b each have two (2) address lines.Multiplexer 33 has anaddress bus 33 a with a first address line electrically coupled topin 22 a (FIG. 2 ) andpin 26 b (FIG. 2 ), and a second address line electrically coupled topin 26 a (FIG. 2 ) andpin 22 b (FIG. 2 ). The following Table 1 exemplary illustrates an address bit logic utilized bymain logic units 31 for electrically communicating a selected cache configuration between an 8 Mbyte cache and a 16 Mbyte cache toSRAM 20 a andSRAM 20 b.TABLE 1 FIRST SECOND ADDRESS CACHE ADDRESS ADDRESS BUS SIZE LINE (MSB) LINE (LSB) 32a 8 Mbyte net2 net2 32b 16 Mbyte net1 net2 - Still referring to
FIG. 3A ,microprocessor 30 further comprises aconfiguration register 34.Configuration register 34 provides a control signal tomultiplexor 33 via acontrol bus 34 a in response to a selection signal frommain logic units 31 via adata bus 31 a. The selection signal is indicative of a selected cache configuration bymain logic units 31 during an initial boot ofmicroprocessor 30. The control signal is indicative of the address bus that corresponds to the selected cache configuration. Consequently,multiplexor 33 provides the appropriate address signals viaaddress bus 33 a to SRAM 20 a andSRAM 20 b in response to the selection signal. For example, when the selection signal indicates the 16 Mbyte cache has been selected during an initial boot ofmicroprocessor 30, pin 22 a andpin 26 b concurrently receive address signal net1, and pin 26 a andpin 22 b concurrently receive address signal net2 as indicated by Table 1. - Referring to
FIG. 3B , amicroprocessor 40 in accordance with the present invention for selecting between three (3) of the four (4) cache configurations supported bySRAM 20 a andSRAM 20 b is shown.Microprocessor 40 includesmain logic units 41 for interpreting and executing operating and application programs as would occur to one skilled in the art.Microprocessor 40 further includes acontroller 42 and amultiplexer 43.Address bus 42 a,address bus 42 b, andaddress bus 42 c provide electrical communication betweencontroller 42 andmultiplexer 43.Address bus 42 aaddress bus 42 b, andaddress bus 42 c each have three (3) address lines.Multiplexer 43 has anaddress bus 43 a with a first address line electrically coupled to pin 22 a (FIG. 2 ) andpin 26 b (FIG. 2 ), a second address line electrically coupled to pin 26 a (FIG. 2 ) andpin 22 b (FIG. 2 ), and a third address line electrically coupled to pin 23 a (FIG. 2 ) andpin 25 b (FIG. 2 ). The following Table 2 exemplary illustrates the address bit logic utilized bymain logic units 41 for electrically communicating a selected cache configuration between a 4 Mbyte cache, an 8 Mbyte cache and a 16 Mbyte cache to SRAM 20 a andSRAM 20 b.TABLE 2 FIRST SECOND THIRD ADDRESS CACHE ADDRESS ADDRESS ADDRESS BUS SIZE LINE (MSB) LINE LINE (LSB) 32a 4 Mbyte net3 net3 net3 32b 8 Mbyte net2 net2 net3 32c 16 Mbyte net1 net2 net3 - Still referring to
FIG. 3B ,microprocessor 40 further comprises a configuration register 44. Configuration register 44 provides a control signal tomultiplexor 43 via acontrol bus 44 a in response to a selection signal frommain logic units 41 via adata bus 41 a. The selection signal is indicative of a selected cache configuration bymain logic units 41 during an initial boot ofmicroprocessor 40. The control signal is indicative of the address bus that corresponds to the selected cache configuration. Consequently,multiplexor 43 provides the appropriate address signals viaaddress bus 43 a to SRAM 20 a andSRAM 20 b in response to the selection signal. For example, when the selection signal indicates the 8 Mbyte cache has been selected, pin 22 a andpin 26 b concurrently receive address signal net2, pin 26 a andpin 22 b concurrently receive address signal net2, and pin 23 a andpin 25 b concurrently receive address signal net3 as indicated by Table 2. - Referring to
FIG. 3C , amicroprocessor 50 in accordance with the present invention for selecting between all four (4) cache configurations supported bySRAM 20 a andSRAM 20 b is shown.Microprocessor 50 includesmain logic units 51 for interpreting and executing operating and application programs as would occur to one skilled in the art.Microprocessor 50 further includes acontroller 52 and amultiplexer 53.Address bus 52 a,address bus 52 b,address bus 52 c, andaddress bus 52 d provide electrical communication betweencontroller 52 andmultiplexer 53.Address bus 52 aaddress bus 52 b,address bus 52 c, andaddress bus 52 d each have four (4) address lines.Multiplexer 53 has anaddress bus 53 a with a first address line electrically coupled to pin 22 a (FIG. 2 ) andpin 26 b (FIG. 2 ), a second address line electrically coupled to pin 26 a (FIG. 2 ) andpin 22 b (FIG. 2 ), a third address line electrically coupled to pin 23 a (FIG. 2 ) andpin 25 b (FIG. 2 ), and a fourth address line electrically coupled to pin 23 b (FIG. 2 ) and pin 25 a (FIG. 2 ). The following Table 3 exemplary illustrates the address bit logic utilized bymain logic units 51 for electrically communicating a selected cache configuration between a 2 Mbyte cache, a 4 Mbyte cache, an 8 Mbyte cache and a 16 Mbyte cache to SRAM 20 a andSRAM 20 b.TABLE 3 FIRST SECOND THIRD FOURTH AD- ADDRESS AD- AD- ADDRESS DRESS CACHE LINE DRESS DRESS LINE BUS SIZE (MSB) LINE LINE (LSB) 32a 2 Mbyte net4 net4 net4 net4 32b 4 Mbyte net3 net3 net3 net4 32c 8 Mbyte net2 net2 net3 net4 32d 16 Mbyte net1 net2 net3 net4 - Still referring to
FIG. 3C ,microprocessor 50 further comprises aconfiguration register 54.Configuration register 54 provides a control signal tomultiplexor 53 via acontrol bus 54 a in response to a selection signal frommain logic units 51 via adata bus 51 a. The selection signal is indicative of a selected cache configuration bymain logic units 51 during an initial boot ofmicroprocessor 50. The control signal is indicative of the address bus that corresponds to the selected cache configuration. Consequently,multiplexor 53 provides the appropriate address signals viaaddress bus 53 a to SRAM 20 a andSRAM 20 b in response to the selection signal. For example, when the selection signal indicates the 8 Mbyte cache has been selected, pin 22 a andpin 26 b concurrently receive address signal net2, pin 26 a andpin 22 b concurrently receive address signal net2, pin 23 a andpin 25 b concurrently receive address signal net3, and pin 23 b and pin 25 a concurrently receive address signal net4 as indicated by Table 3. - From the previous description of
SRAM 20 a andSRAM 20 b herein in connection withFIG. 2 , one skilled in the art will know how to make and use electrical couplings between additional synchronous address pins ofSRAM 20 a andSRAM 20 b in accordance with the present invention. From the previous description ofmicroprocessors FIGS. 3A-3C , respectively, one skilled in the art will know how to make and use microprocessors in accordance with the present invention for selecting a cache configuration between five or more supported cache configurations. - While the embodiments of the present invention disclosed herein are presently considered to be preferred, various changes and modifications can be made without departing from the spirit and scope of the invention. The scope of the invention is indicated in the appended claims, and all changes that come within the meaning and range of equivalents are intended to be embraced therein. For examples, the pin configuration and size of
SRAM 20 a andSRAM 20 b can vary, and/orSRAM 20 a andSRAM 20 b may include asynchronous address pins. Additionally,SRAM 20 a andSRAM 20 b may be misaligned along the respective sides ofprocessor card 10, and/or mounted on the same side ofprocessor card 10. Also, other memory devices may be utilized in lieu ofSRAM 20 a andSRAM 20 b, e.g. dynamic static random access memories.
Claims (9)
1-30. (Cancelled)
31. A method of operating a microprocessor for supporting multiple cache configurations, the method comprising:
selecting a first cache configuration among the multiple cache configurations during a first boot of the microprocessor; and
communicating the selection of the first cache configuration among the multiple cache configurations during the first boot of the microprocessor to a first memory device and a second memory device.
32. The method of claims 31, further comprising:
selecting a second cache configuration among the multiple cache configurations during a second boot of the microprocessor; and
communicating the selection of the second cache configuration among the multiple cache configurations during the second boot of the microprocessor to the first memory device and the second memory device.
33-35. (Cancelled)
36. The method of claim 32 wherein the first memory device and the second memory device receive the selection of the second cache configuration concurrently.
37. The method of claim 32 wherein the selection of the second cache configuration is performed by a configuration register in communication with a multiplexor.
38. The method of claim 31 wherein the selection of the first cache configuration is performed by a configuration register in communication with a multiplexor.
39. The method of claim 31 wherein the first memory device and the second memory device receive the selection of the first cache configuration concurrently.
40. A method of selecting a cache configuration, the method comprising:
Selecting a first cache configuration among multiple cache configurations during a first boot of a microprocessor;
Sending a control signal indicative of the first cache configuration to a first memory device and a second memory device such that the first memory device and the second memory device receive the control signal concurrently.
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US10/959,798 US20050041518A1 (en) | 2000-12-07 | 2004-10-06 | Method and system for supporting multiple cache configurations |
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US09/731,869 US6760272B2 (en) | 2000-12-07 | 2000-12-07 | Method and system for supporting multiple cache configurations |
US10/664,455 US7051179B2 (en) | 2000-12-07 | 2003-09-18 | Method and system for supporting multiple cache configurations |
US10/959,798 US20050041518A1 (en) | 2000-12-07 | 2004-10-06 | Method and system for supporting multiple cache configurations |
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US09/731,869 Expired - Fee Related US6760272B2 (en) | 2000-12-07 | 2000-12-07 | Method and system for supporting multiple cache configurations |
US10/664,455 Expired - Fee Related US7051179B2 (en) | 2000-12-07 | 2003-09-18 | Method and system for supporting multiple cache configurations |
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US09/731,869 Expired - Fee Related US6760272B2 (en) | 2000-12-07 | 2000-12-07 | Method and system for supporting multiple cache configurations |
US10/664,455 Expired - Fee Related US7051179B2 (en) | 2000-12-07 | 2003-09-18 | Method and system for supporting multiple cache configurations |
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Cited By (1)
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US20070147121A1 (en) * | 2005-12-28 | 2007-06-28 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
Families Citing this family (6)
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US6760272B2 (en) * | 2000-12-07 | 2004-07-06 | International Business Machines Corporation | Method and system for supporting multiple cache configurations |
US7640383B2 (en) * | 2004-11-05 | 2009-12-29 | Via Technologies Inc. | Method and related apparatus for configuring lanes to access ports |
US7653785B2 (en) * | 2005-06-22 | 2010-01-26 | Lexmark International, Inc. | Reconfigurable cache controller utilizing multiple ASIC SRAMS |
KR20070033714A (en) * | 2005-09-22 | 2007-03-27 | 삼성전자주식회사 | Data transmission line wiring method |
US7523260B2 (en) * | 2005-12-22 | 2009-04-21 | International Business Machines Corporation | Propagating data using mirrored lock caches |
US8379830B1 (en) | 2006-05-22 | 2013-02-19 | Convergys Customer Management Delaware Llc | System and method for automated customer service with contingent live interaction |
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Also Published As
Publication number | Publication date |
---|---|
US7051179B2 (en) | 2006-05-23 |
US6760272B2 (en) | 2004-07-06 |
US20020112120A1 (en) | 2002-08-15 |
US20040062068A1 (en) | 2004-04-01 |
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