US20040251496A1 - Zero threshold voltage pfet and method of making same - Google Patents
Zero threshold voltage pfet and method of making same Download PDFInfo
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- US20040251496A1 US20040251496A1 US10/250,190 US25019003A US2004251496A1 US 20040251496 A1 US20040251496 A1 US 20040251496A1 US 25019003 A US25019003 A US 25019003A US 2004251496 A1 US2004251496 A1 US 2004251496A1
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- 238000004519 manufacturing process Methods 0.000 title abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 239000012212 insulator Substances 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims abstract description 16
- 239000002019 doping agent Substances 0.000 claims description 11
- 230000005669 field effect Effects 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims 2
- 239000010703 silicon Substances 0.000 claims 2
- 239000002243 precursor Substances 0.000 abstract description 11
- 238000000137 annealing Methods 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 description 11
- 238000000034 method Methods 0.000 description 11
- 238000002513 implantation Methods 0.000 description 10
- 239000003990 capacitor Substances 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
A zero threshold voltage (ZVt) pFET (104) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate (112) with a retrograde n-well (116) so that a pocket (136) of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask (168) having a pocket-masking region (184) in the aperture (180) corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well (116′) and then annealing the substrate so as to cause the regions of the lower portion (140′) of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator (128), gate (132), source (120), and drain (124).
Description
- 1. Field of the Invention
- The present invention relates generally to the field of semiconductors. More particularly, the present invention is directed to a zero threshold voltage pFET and a method of making the same.
- 2. Background of the Invention
- Zero, or low, threshold voltage (ZVt) devices are useful in various types of integrated circuits (ICs). For example, ZVt field-effect transistors (FETs) are desirable in certain applications because of their high switching speed and low saturation voltage. ZVt FETs are useful in analog circuits, e.g., amplifiers and power supplies, and in digital circuits, e.g., for power supply decoupling in logic circuits, among other uses.
- In the manufacture of semiconductor ICs, processing often begins with a p-doped wafer. Due to this p-doping, it is a relatively simple matter to form ZVt nFETs without the need to provide any masks in addition to the masks used to form the implanted wells of standard threshold voltage (Std-Vt) FETs. Since there are no additional costs needed for additional masks with respect to ZVt nFETs, Zvt nFETs may be called “free” devices. However, using conventional processing techniques, ZVt pFETs are not free devices, since they would have to be made using an additional counterdoping mask that would not be needed to form the n-well of a Std-Vt pFET. This is illustrated in FIGS. 1 and 2. FIG. 1 illustrates the step of forming a conventional n-well20 in a p-
type substrate 24 using a typical n-well mask 28. After n-well 20 is formed, a Std-Vt pFET 32 may be made by forming shallow trench isolators (STIs) 36,gate insulator 40,gate 44,source 48, anddrain 52, among other things, using conventional techniques. - As shown in FIG. 2, if a
ZVt pFET 56 were desired under conventional thinking, n-well 20 of FIG. 1 would have to be counterdoped to form acounterdoped region 60 beneathgate 44′ that would become the channel of the ZVt PFET. After the counterdoping has been performed, the other structures ofZVt pFET 56, e.g., shallow trench isolators (STIs) 36′,gate insulator 40′,gate 44′,source 48′, anddrain 52′, among other things, may be formed using conventional techniques. This counterdoping of n-well 20 requires anadditional mask 64 to mask regions ofsubstrate 24 where counterdoping is unwanted, e.g., at all regions other than the regions of the ZVt pFETs. Thisadditional mask 64 and associated wafer processing adds to the cost of an IC. Due to these additional costs, ZVt pFETs are not free devices. Since ZVt pFETs are not free devices, IC designers generally avoid using them. It would be beneficial if there were a method of making ZVt pFETs without additional mask and associated processing costs. - An integrated circuit comprising a device that includes a substrate made of a material. The substrate includes a surface, an implanted well having a first dopant type and a lower portion distal from the surface. A pocket consisting of the material is formed within the implanted well between the lower portion of the implanted well and the surface of the substrate. An insulator is located proximate the surface of the substrate above the pocket. An electrode is located proximate the insulator and is located substantially in registration with the pocket.
- A method of forming an integrated circuit device on a substrate made of a material and having a surface. The method comprises the step of providing a mask to the substrate that protects a pocket of the adjacent the surface of the substrate. An implanted well is formed so that the implanted well isolates the pocket. An insulator is formed proximate the surface of the substrate above the pocket. An electrode is formed proximate the insulator above the pocket.
- For the purpose of illustrating the invention, the drawings show a form of the invention that is presently preferred. However, it should be understood that the present invention is not limited to the precise arrangements and instrumentalities shown in the drawings, wherein:
- FIG. 1 is a cross-sectional view of a prior art Std-Vt pFET illustrating the step of forming an n-well in a substrate;
- FIG. 2 is a cross-sectional view of the Std-Vt pFET of FIG. 1 illustrating the step of counterdoping the n-well in order to form a prior art lower-Vt pFET;
- FIG. 3 is a cross-sectional view of an integrated circuit that includes a conventional nFET and a ZVt pFET of the present invention;
- FIG. 4 is a cross-sectional view of the integrated circuit of FIG. 3 during its manufacture, showing the creation of a precursor n-well ring in the substrate for the ZVt pFET;
- FIG. 5 is a cross-sectional view of the integrated circuit of FIG. 3 during its manufacture, showing the merging of the lower portion of the precursor n-well to form a pocket of p-substrate material beneath the gate of the ZVt pFET;
- FIG. 6 is a cross-sectional view of the integrated circuit of FIG. 3 during its manufacture, showing the formation of a p-well for the nFET;
- FIG. 7 is a cross-sectional view of the integrated circuit of FIG. 3 during its manufacture, showing the formation of shallow trench insulators, gate insulators, and gates for the ZVt pFET and nFET;
- FIG. 8 is a cross-sectional view of the integrated circuit of FIG. 3 during its manufacture, showing the formation of the source and drain of the ZVt pFET; and
- FIG. 9 is a cross-sectional view of the integrated circuit of FIG. 3 during its manufacture, showing the formation of the source and drain of the nFET.
- FIG. 3 shows in accordance with the present invention an integrated circuit (IC), denoted generally by the
numeral 100. Importantly, IC 100 includes a unique zero, or low, threshold voltage (ZVt)pFET 104 that, as described below, can be made without any masks in addition to the masks that would otherwise be used in forming the various devices of the IC. As those skilled in the art will appreciate, IC 100 may have any type and number of devices, e.g., capacitors, standard threshold voltage (Std-Vt) FETs, and ZVt nFETs, among others, appropriate for the application of the IC. However, for convenience, only a small portion ofIC 100 is shown to illustrate the inventive method of formingZVt pFET 104. Also for convenience,ZVt pFET 104 is shown proximate a Std-Vt nFET 108 to illustrate the making of the ZVt pFET in conjunction with another device. Those skilled in the art will understand that generally only basic components ofZVt pFET 104 and Std-Vt nFET 108 are shown. Components not shown, e.g., insulating layers, contacts, and conductors, are well known in the art and do not need to be shown for those skilled in the art to understand the scope of the present invention. - IC100 generally includes a
substrate 112, such as a p-doped wafer or combination of one or more epitaxial layers and a wafer, that provides the basic structure ofZVt pFET 104 and Std-Vt nFET 108. ZVtpFET 104 includes an n-well 116, asource 120, adrain 124, agate insulator 128, agate 132, and apocket 136 of p-substrate material located between the gate and thelower portion 140 of the n-well. The formation ofpocket 136 is an important aspect of the present invention, since this may be accomplished without additional masks. Thus,ZVt pFET 104 may be considered a “free device,” as described in the background section above. Std-Vt nFET 108 may be a conventional nFET that includes a p-well 144, asource 148, adrain 152, agate insulator 156, and agate 160.STIs 164 may be provided aroundZVt pFET 100 and Std-Vt nFET 108 as needed to isolate the regions of these devices from one another and other surrounding devices (not shown).STIs 164 may be formed using any of the well-known methods practiced in the art. As those skilled in the art will appreciate,STIs 164 may be formed before or after well implanting is performed. - FIGS. 4-9 illustrate various steps in the formation of IC100 (FIG. 3) and, particularly,
ZVt pFET 104. Referring to FIG. 4, an n-well mask 168 may be used to implantsubstrate 112 with a generally ring-shaped precursor n-well 116′ in theregion 172 of ZVt pFET 104 (FIG. 3). All other regions not receiving an n-well implant, e.g.,region 176 of nFET, are masked by n-well mask 168. To create ring-shaped precursor n-well 116′, n-well mask 168 includes a generally ring-shapedaperture 180, the inner periphery of which is defined by a “pocket-masking region” 184 that masks the central portion ofZVt pFET region 172 so as to allow the formation of pocket 136 (FIG. 3) of un-implanted substrate material beneathgate 132. After n-well mask 168 has been properly registered with respect tosubstrate 112, the substrate is implanted by bombarding it with suitable n-type dopant atoms in any manner known in the art. It is not necessary to describe implantation techniques in any detail, since such techniques are widely known in the art. - Although not shown, wherever Std-Vt pFETs are desired, n-
well mask 168 would include conventional n-well apertures. Generally, an aperture for formingZVt pFET 104 is the same as a conventional n-well aperture, but with pocket-maskingregion 184, for creating pocket 136 (FIG. 3) during formation of n-well 140. As will be readily appreciated by those skilled in the art, all that is generally required to form n-well 140 andpocket 136 ofZVt pFET 104 is to add a pocket-maskingregion 184 to a conventional n-well mask for each ZVt pFET desired. Therefore, no additional masks are needed to formZVt pFET 104 relative to the number of masks needed to form Sdt-Vt FETs, such asnFET 108, and ZVt nFETs. - As can be seen in FIG. 4, n-well116 (FIG. 3) may be formed by implanting precursor ring-shaped n-well 116′ as a retrograde well. Precursor n-well 116′ generally spreads out in cross-section as the dopant concentration increases with depth. However, the spreading is typically not so great that
lower portion 140′ of precursor n-well 116′ becomes continuous underneath pocket-maskingregion 184 of n-well mask 168. This is most often true when implantation is performed normal to the surface ofsubstrate 112. One way to cause regions oflower portion 140′ of precursor n-well 116′ to merge with one another to form continuous n-well 116 of FIG. 3 is tosubject substrate 112 to annealing temperatures in a manner known in the art. This annealing process causes doping atoms in precursor n-well 116′ to diffuse laterally, causing regions oflower portion 140′ to spread and merge with one another to formpocket 136 of original substrate material above the bottom of the now-continuous n-well 116. Merged n-well 116 is shown in FIG. 5. - Depending upon the width W of pocket-masking
region 184, the depth of n-well 116, and dopant concentration in thelower portion 140 of the n-well, among other variables, skewed implantation may be used to supplement annealing or to eliminate the need to anneal substrate. As is readily apparent, implanting dopant atoms at an angle skewed from normal may be used to implant these atoms farther underneath pocket-maskingregion 184 of n-well mask 168 than implantation performed normal to the surface ofsubstrate 112 could achieve. If width W of pocket-maskingregion 184 is small enough and the angle of implantation is large enough with respect to a normal from the surface ofsubstrate 112, implantation may be great enough that atoms implanted from one side of the pocket-masking region may extend into the region doped with atoms implanted from the opposite side of the pocket-masking region, particularly when implantation is performed at multiple angles in opposing directions. These skewed implantations are represented byarrows 188 in FIG. 4. It is noted that width W of pocket-maskingregion 184 is dependent upon a number of variables, such as the width of gate 132 (FIG. 3) and method of implantation, among others. While these variables exist, it is well within ordinary skill in the art to determine suitable values for these variables without undue experimentation. Therefore, a detailed presentation of interrelation of these variables and an exhaustive list of parameters are not required for those skilled in the art to practice the full scope of the present invention, as defined by the appended claims. - After merged n-well116 has been formed,
substrate 112 may be further processed to form the remaining structures ofZVt pFET 104 and Std-Vt nFET 108. For example, FIG. 6 illustrates the formation of p-well 144 of Std-Vt nFET 108 (FIG. 3) using a p-well mask 192 to mask all regions ofsubstrate 112 where p-doping is not desired, e.g., atregion 172 ofZVt pFET 104. Once p-well mask 192 has been positioned properly,substrate 112 is implanted with suitable p-type dopant atoms in a manner known in the art. FIG. 7 illustrates several steps performed subsequent to the formation of p-well 144.STIs 164 andgate insulators polysilicon gates 132, 160 (electrodes). Each of these steps may be performed in any manner known in the art. Since the techniques used to form these structures are well-known in the art, they need not be described herein. FIGS. 8 and 9 show, respectively, the doping ofsubstrate 112 to form, respectively,source 120 and drain 124 ofZVt pFET 104 andsource 148 and drain 152 of Std-Vt nFET 108 utilizing a ZVt pFET source anddrain mask 196 and an Std-Vt nFET source anddrain mask 200.Sources - Although the invention has been described with respect to forming a
ZVt pFET 104 on a p-dopedsubstrate 112, those skilled in the art will readily appreciate that a ZVt nFET may similarly be formed on a n-doped substrate. In addition, those skilled in the art will understand that IC devices other than ZVt FETs, e.g., ZVt capacitors, may be made in accordance with the present invention. A ZVt capacitor is similar to a ZVt FET but would have a larger “gate” electrode and no source (or drain). - While the present invention has been described in connection with a preferred embodiment, it will be understood that it is not so limited. On the contrary, it is intended to cover all alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined above and in the claims appended hereto.
Claims (17)
1. An integrated circuit, comprising:
a) a device that includes:
i) a substrate made of a material and including:
A) a surface;
B) an implanted well having a first dopant type and a lower portion distal from said surface; and
C) a pocket, consisting of said material, formed within said implanted well between said lower portion of said implanted well and said surface of said substrate;
ii) an insulator proximate said surface of said substrate above said pocket; and
iii) an electrode proximate said insulator and located substantially in registration with said pocket.
2. An integrated circuit according to claim 1 , wherein said device is a field effect transistor.
3. An integrated circuit according to claim 2 , wherein said electrode comprises a gate.
4. An integrated circuit according to claim 1 , wherein said substrate is a wafer.
5. An integrated circuit according to claim 4 , wherein said material is p-doped silicon.
6. An integrated circuit according to claim 5 , wherein said implanted well is an n-well.
7. An integrated circuit according to claim 1 , wherein said implanted well is a retrograde well.
8-20: (Canceled)
21. An integrated circuit, comprising:
a) a device that includes:
i) a substrate having an original dopant level, said substrate including:
A) a surface;
B) an implanted well comprising a lower portion distal from said surface; and
C) a pocket leaving said original dopant level and being formed within said implanted well between said lower portion of said implanted well and said surface of said substrate;
ii) an insulator proximate said surface of said substrate and located substantially in registration with said pocket; and
iii) an electrode proximate said insulator and located substantially in registration with said pocket.
22. An integrated circuit according to claim 1 , where said original dopant level is greater than zero.
23. An integrated circuit, comprising:
a) a device that includes;
i) a substrate comprising an original material and including:
A) a surface;
B) an implanted well having a first dopant type and a lower portion distal from said surface; and
C) a pocket, consisting essentially of said original material, formed within said implanted well between said lower portion of said implanted well and said surface of said substrate;
ii) an insulator proximate said surface of said substrate above said pocket; and
iii) an electrode proximate said insulator and located substantially in registration with said pocket.
24. An integrated circuit according to claim 23 , wherein said device is a field effect transistor.
25. An integrated circuit according to claim 24 , wherein said electrode comprises a gate.
26. An integrated circuit according to claim 23 , wherein said substrate is a wafer.
27. An integrated circuit according to claim 26 , wherein said material is p-doped silicon.
28. An integrated circuit according to claim 27 , wherein said implanted well is an n-well.
29. An integrated circuit according to claim 23 , wherein said implanted well is a retrograde well.
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US10/250,190 US6825530B1 (en) | 2003-06-11 | 2003-06-11 | Zero Threshold Voltage pFET and method of making same |
US10/845,835 US7005334B2 (en) | 2003-06-11 | 2004-05-14 | Zero threshold voltage pFET and method of making same |
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US10/250,190 US6825530B1 (en) | 2003-06-11 | 2003-06-11 | Zero Threshold Voltage pFET and method of making same |
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US20050285218A1 (en) * | 2004-06-25 | 2005-12-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming high voltage devices with retrograde well |
US20180331198A1 (en) * | 2017-05-15 | 2018-11-15 | Qualcomm Incorporated | Thin oxide zero threshold voltage (zvt) transistor fabrication |
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US7049667B2 (en) | 2002-09-27 | 2006-05-23 | Hrl Laboratories, Llc | Conductive channel pseudo block process and circuit to inhibit reverse engineering |
AU2003293540A1 (en) * | 2002-12-13 | 2004-07-09 | Raytheon Company | Integrated circuit modification using well implants |
JP2004214575A (en) * | 2003-01-09 | 2004-07-29 | Matsushita Electric Ind Co Ltd | Semiconductor device |
US7242063B1 (en) | 2004-06-29 | 2007-07-10 | Hrl Laboratories, Llc | Symmetric non-intrusive and covert technique to render a transistor permanently non-operable |
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US8168487B2 (en) | 2006-09-28 | 2012-05-01 | Hrl Laboratories, Llc | Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer |
CN111430307B (en) * | 2019-12-17 | 2021-06-25 | 合肥晶合集成电路股份有限公司 | Well preparation method and well injection photomask set of semiconductor integrated device |
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US20050285218A1 (en) * | 2004-06-25 | 2005-12-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming high voltage devices with retrograde well |
US7221021B2 (en) * | 2004-06-25 | 2007-05-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming high voltage devices with retrograde well |
US20180331198A1 (en) * | 2017-05-15 | 2018-11-15 | Qualcomm Incorporated | Thin oxide zero threshold voltage (zvt) transistor fabrication |
Also Published As
Publication number | Publication date |
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US7005334B2 (en) | 2006-02-28 |
US6825530B1 (en) | 2004-11-30 |
US20040251475A1 (en) | 2004-12-16 |
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