US20040127003A1 - Methods for transistor gate fabrication and for reducing high-k gate dielectric roughness - Google Patents
Methods for transistor gate fabrication and for reducing high-k gate dielectric roughness Download PDFInfo
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- US20040127003A1 US20040127003A1 US10/335,557 US33555702A US2004127003A1 US 20040127003 A1 US20040127003 A1 US 20040127003A1 US 33555702 A US33555702 A US 33555702A US 2004127003 A1 US2004127003 A1 US 2004127003A1
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- 238000000034 method Methods 0.000 title claims abstract description 89
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000010410 layer Substances 0.000 claims abstract description 178
- 230000006911 nucleation Effects 0.000 claims abstract description 102
- 238000010899 nucleation Methods 0.000 claims abstract description 102
- 229910052751 metal Inorganic materials 0.000 claims abstract description 62
- 239000002184 metal Substances 0.000 claims abstract description 62
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 50
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 22
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 22
- 239000002356 single layer Substances 0.000 claims abstract description 22
- 229910052914 metal silicate Inorganic materials 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims description 43
- 239000000463 material Substances 0.000 claims description 42
- 230000008569 process Effects 0.000 claims description 34
- 229910052735 hafnium Inorganic materials 0.000 claims description 18
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 18
- 238000005240 physical vapour deposition Methods 0.000 claims description 14
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 claims description 8
- 238000011065 in-situ storage Methods 0.000 claims description 8
- 150000001875 compounds Chemical class 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims 2
- 239000003989 dielectric material Substances 0.000 abstract description 17
- 239000000758 substrate Substances 0.000 abstract description 16
- 230000015572 biosynthetic process Effects 0.000 abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 25
- 238000000151 deposition Methods 0.000 description 22
- 230000008021 deposition Effects 0.000 description 17
- 239000010408 film Substances 0.000 description 11
- 239000000377 silicon dioxide Substances 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 238000005137 deposition process Methods 0.000 description 9
- 239000002243 precursor Substances 0.000 description 8
- 230000009467 reduction Effects 0.000 description 8
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 230000003746 surface roughness Effects 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 230000001737 promoting effect Effects 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000005641 tunneling Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 150000004645 aluminates Chemical class 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 229910052454 barium strontium titanate Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910052746 lanthanum Inorganic materials 0.000 description 2
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 150000004760 silicates Chemical class 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- WSMQKESQZFQMFW-UHFFFAOYSA-N 5-methyl-pyrazole-3-carboxylic acid Chemical compound CC1=CC(C(O)=O)=NN1 WSMQKESQZFQMFW-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910000906 Bronze Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- -1 ZrSiON Chemical class 0.000 description 1
- VNSWULZVUKFJHK-UHFFFAOYSA-N [Sr].[Bi] Chemical compound [Sr].[Bi] VNSWULZVUKFJHK-UHFFFAOYSA-N 0.000 description 1
- WVEIBSXNFJMONP-UHFFFAOYSA-N [Ta].[K] Chemical compound [Ta].[K] WVEIBSXNFJMONP-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- FWGZLZNGAVBRPW-UHFFFAOYSA-N alumane;strontium Chemical compound [AlH3].[Sr] FWGZLZNGAVBRPW-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 description 1
- IQONKZQQCCPWMS-UHFFFAOYSA-N barium lanthanum Chemical compound [Ba].[La] IQONKZQQCCPWMS-UHFFFAOYSA-N 0.000 description 1
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- XBYNNYGGLWJASC-UHFFFAOYSA-N barium titanium Chemical compound [Ti].[Ba] XBYNNYGGLWJASC-UHFFFAOYSA-N 0.000 description 1
- YIMPFANPVKETMG-UHFFFAOYSA-N barium zirconium Chemical compound [Zr].[Ba] YIMPFANPVKETMG-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910002115 bismuth titanate Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- NKZSPGSOXYXWQA-UHFFFAOYSA-N dioxido(oxo)titanium;lead(2+) Chemical compound [Pb+2].[O-][Ti]([O-])=O NKZSPGSOXYXWQA-UHFFFAOYSA-N 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229960004592 isopropanol Drugs 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 229910052451 lead zirconate titanate Inorganic materials 0.000 description 1
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 1
- 239000003446 ligand Substances 0.000 description 1
- GQYHUHYESMUTHG-UHFFFAOYSA-N lithium niobate Chemical compound [Li+].[O-][Nb](=O)=O GQYHUHYESMUTHG-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- ZBSCCQXBYNSKPV-UHFFFAOYSA-N oxolead;oxomagnesium;2,4,5-trioxa-1$l^{5},3$l^{5}-diniobabicyclo[1.1.1]pentane 1,3-dioxide Chemical compound [Mg]=O.[Pb]=O.[Pb]=O.[Pb]=O.O1[Nb]2(=O)O[Nb]1(=O)O2 ZBSCCQXBYNSKPV-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- UKDIAJWKFXFVFG-UHFFFAOYSA-N potassium;oxido(dioxo)niobium Chemical compound [K+].[O-][Nb](=O)=O UKDIAJWKFXFVFG-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 1
- DKDQMLPMKQLBHQ-UHFFFAOYSA-N strontium;barium(2+);oxido(dioxo)niobium Chemical compound [Sr+2].[Ba+2].[O-][Nb](=O)=O.[O-][Nb](=O)=O.[O-][Nb](=O)=O.[O-][Nb](=O)=O DKDQMLPMKQLBHQ-UHFFFAOYSA-N 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
Definitions
- This invention relates generally to semiconductor devices and more particularly to methods for fabricating transistor gate structures and for reducing roughness in high-k gate dielectric layers in the manufacture of semiconductor devices.
- FETs Field effect transistors
- MOSFETs metal-oxide-semiconductor field-effect transistors
- a gate dielectric or gate oxide such as silicon dioxide (SiO 2 )
- SiO 2 silicon dioxide
- a gate electrode or gate contact is then formed over the gate dielectric, and the gate dielectric and gate contact materials are patterned to form a gate structure overlying the channel region of the substrate.
- the gate dielectric is an insulator material, which prevents large currents from flowing from the gate into the channel when a voltage is applied to the gate contact, while allowing such an applied gate voltage to set up an electric field in the channel region in a controllable manner.
- Continuing trends in semiconductor product manufacturing include reduction in electrical device feature sizes (scaling), as well as improvements in device performance in terms of device switching speed and power consumption.
- MOS transistor performance may be improved by reducing the distance between the source and the drain regions under the gate electrode of the device, known as the gate or channel length, and by reducing the thickness of the layer of gate oxide that is formed over the semiconductor surface.
- EOT scaling Because the dielectric constant is higher, a thicker high-k dielectric layer can be deposited to avoid or mitigate tunneling leakage currents, while still achieving the required value of EOT that is comparable to the EOT value of a thinner layer of thermally grown SiO 2 .
- the reduction in transistor gate equivalent oxide thickness is sometimes referred to as EOT scaling.
- High-k dielectrics are typically deposited directly over a silicon substrate to form a gate dielectric layer using chemical vapor deposition (CVD), atomic layer CVD(AL-CVD), plasma enhanced CVD (PECVD) or physical vapor deposition (PVD) processes such as sputtering.
- CVD chemical vapor deposition
- A-CVD atomic layer CVD
- PECVD plasma enhanced CVD
- PVD physical vapor deposition
- thin portions of the resulting gate dielectric suffer from higher leakage currents than thicker portions, while the thicker portions have higher EOT than the thinner portions.
- the upper surface roughness becomes more significant, whereby effective limitations arise in the ability to further scale the dielectric. Therefore, there is a need for improved gate fabrication techniques by which roughness in CVD deposited high-k dielectrics films may be reduced.
- the following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention.
- This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
- the invention relates to methods for fabricating transistor gate structures and high-k dielectric layers therefor using CVD deposition processes, while reducing or avoiding the undesirable effects of high-k dielectric roughness, by which improved device performance and scalability may be achieved.
- nucleation promotion layer comprises a metal, metal silicide, or a metal silicate, which increases the density of nucleation sites on the substrate surface.
- the high density of nucleation sites promotes uniform formation of high-k dielectric material on the substrate with reduced roughness at the top surface of the high-k layer.
- the nucleation promotion layer thus facilitates EOT scaling, gate leakage current reduction, and increased device reliability through improved uniformity in electrical and material properties.
- the nucleation promotion layer may be formed using CVD, PVD or other deposition processes.
- the nucleation promotion layer and the high-k dielectric layer are both formed in-situ in a single chemical vapor deposition process chamber.
- the nucleation promotion layer moreover, may be a very thin film, such as about 10 ⁇ or less in thickness, preferably a monolayer or sub-monolayer.
- the nucleation promotion layer may advantageously comprises the same metal, a silicide of the metal, or a silicate of the metal, so as to facilitate nucleation in the initial stages of high-k CVD deposition.
- Another aspect of the invention provides methods for fabricating a transistor gate structure, which comprises forming an intentional interface layer over the semiconductor body, and forming a nucleation promotion layer over the intentional interface layer. Thereafter, a high-k dielectric layer is formed over the nucleation promotion layer using a chemical vapor deposition process.
- the nucleation promotion layer overlying the intentional interface layer provides an increased number of nucleation sites for deposition of high-k material on the intentional interface, thereby promoting uniform formation of high-k dielectric material without the degree of upper surface roughness found in conventional CVD processes.
- Yet another aspect of the invention provides methods for reducing high-k gate dielectric roughness in the fabrication of a transistor gate structure, comprising forming a nucleation promotion layer over a semiconductor body or an intentional interface layer, where the nucleation promotion layer comprising a metal, a metal silicide, or a metal silicate.
- the method further comprises forming a high-k dielectric layer over the nucleation promotion layer using a chemical vapor deposition process.
- FIG. 1 is a flow diagram illustrating an exemplary method of fabricating transistor gate structures including formation of a nucleation promotion layer over a substrate or other semiconductor body prior to CVD deposition of high-k materials in accordance with one or more aspects of the present invention
- FIGS. 2 - 6 are partial side elevation views in section illustrating an exemplary semiconductor device being processed at various stages of manufacturing in accordance with various aspects of the invention.
- FIG. 7 is a flow diagram illustrating another exemplary method of fabricating transistor gate structures including formation of a nucleation promotion layer over an intentional interface layer before CVD deposition of high-k materials in accordance with one or more aspects of the present invention.
- the invention relates to methods for fabricating gate structures in a semiconductor device, which may be employed in association with any type of semiconductor body, including silicon or other semiconductor substrates, as well as silicon or other semiconductor layers overlying an insulator region or layer in an SOI device.
- islands of high-k materials form in like manner at different locations, which are spatially separated from one another.
- the growth sites or islands eventually coalesce as the CVD process continues.
- the initial nucleation sites are widely dispersed on the surface of the substrate or intentional interface layer due to a low density of nucleation sites in silicon or many intentional interface layers (e.g., SiO 2 or others)
- the growth sites do not coalesce to form a cohesive film until relatively late in the process.
- the high-k material may be several molecule thicknesses at some locations, but only one molecule thickness at the recently joined locations.
- the finished high-k dielectric layer is relatively thin, the deposition process is fairly short, in which case the thickness variation or roughness is present in the top surface of the finished high-k layer. This roughness has been found to be on the order of one or two monolayers or around 3-10 ⁇ in a high-k layer of about 30 ⁇ thickness, because of which the leakage current reduction advantages of using high-k films may not be fully attainable.
- the present invention provides more low energy nucleation sites across the wafer or intentional interface layer, by formation of a nucleation promotion layer to create more uniformity in attracting precursor molecules during subsequent chemical vapor deposition of high-k materials. While not wishing to be tied to any particular theory, it is believed that formation of a thin layer of metal, metal silicide, or metal silicate increases the number of locations or sites where the growth of high-k material begins in a chemical vapor deposition process. Further, it is believed that the closer these initial nucleation sites are, the more likely the high-k deposition will occur through layer-by-layer growth or that the islands of high-k will coalesce to form a cohesive film early in the deposition process, by which variations in the finished high-k layer thickness are reduced or avoided.
- an exemplary method 2 is illustrated for fabricating a transistor gate structure in accordance with one or more aspects of the present invention.
- the methods of the current invention involve the formation of a nucleation promotion layer on a semiconductor body or interface layer in order to enhance nucleation site density and thereby reduce surface roughness or non-uniformity in high-k dielectric material deposited over the nucleation promotion layer.
- the exemplary method 2 and other methods herein are illustrated and described below as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein, in accordance with the invention.
- Gate fabrication in the method 2 begins at 4 , where a wet clean or HF deglaze operation may optionally be performed at 6 to remove any thin dielectric layers from the semiconductor body, such as silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON).
- a wet clean or HF deglaze operation may optionally be performed at 6 to remove any thin dielectric layers from the semiconductor body, such as silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON).
- wet cleaning operations can be performed at 6 , or a dilute HF solution may be employed to deglaze the semiconductor body.
- a dilute HF solution may be employed to deglaze the semiconductor body.
- a dry process is employed comprising a mixture of anhydrous HF and isopropyl-alcohol to remove SiO.
- a gate dielectric is then processed at 8 , including forming a nucleation promotion layer over the semiconductor body at 10 , where the nucleation promotion layer comprises a metal, a metal silicide, or a metal silicate.
- the nucleation promotion layer may be formed at 10 using any appropriate material deposition technique, such as PVD, CVD, or others.
- a high-k dielectric layer is formed at 12 over the nucleation promotion layer using a chemical vapor deposition process.
- the invention may be employed in association with CVD deposition of any high-k dielectric layer material at 12 to any desired thickness, such as 10-100 ⁇ , for example 20-25 ⁇ , where the nucleation promotion layer may be formed at 10 over a silicon or other semiconductor substrate or any type of semiconductor body.
- the high-k dielectric layer comprises a high-k oxide, oxynitride, or nitride, such as hafnium oxide (HfO 2 ), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON) or others.
- HfO 2 hafnium oxide
- HfON hafnium oxynitride
- HfSiON hafnium silicon oxynitride
- High-k materials which may be deposited in association with the present invention may include, but are not limited to binary metal oxides including aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ), lanthanum oxide (La 2 O 3 ), yttrium oxide (Y 2 O 3 ), titanium oxide (TiO 2 ), as well as their silicates and aluminates; metal oxynitrides including aluminum oxynitride (AlON), zirconium oxynitride (ZrON), hafnium oxynitride (HfON), lanthanum oxynitride (LaON), yttrium oxynitride (YON), as well as their silicates and aluminates such as ZrSiON, HfSiON, LaSiON, YsiON etc.; and perovskite-type oxides including a titanate system material such as barium titanate,
- a gate contact layer such as metal, polysilicon, or equivalent, is then deposited at 14 over the high-k dielectric layer, and the gate contact layer and the high-k dielectric layer are patterned using any appropriate photolithographic techniques (e.g., patterned etching, etc.) at 16 to form a gate structure, before the gate fabrication method 2 ends at 18 .
- the method 2 facilitates reduction in the amount of roughness at the upper surface of the high-k dielectric material, which in turn facilitates EOT scaling, gate leakage current reduction, and increased device reliability through improved uniformity in electrical and material properties.
- the nucleation promotion layer formed at 10 may comprise any metal, metal silicate, or metal silicide in accordance with the present invention.
- the nucleation promotion layer preferably comprises the metal, a silicide of the metal, or a silicate of the metal.
- the nucleation promotion layer preferably comprises hafnium, a silicide of hafnium, or a silicate of hafnium.
- the employment of the same metal constituent in the nucleation promotion and high-k dielectric layers is believed to further enhance uniform nucleation of high-k precursor molecules, particularly in the initial stages of CVD deposition at 12 , whereby upper surface roughness is reduced in the deposited high-k dielectric layer.
- the nucleation promotion layer is preferably thin, such as having a thickness of about 10 ⁇ or less.
- the nucleation promotion layer formed at 10 is a monolayer, for example, having an average thickness on the order of one or a few ⁇ .
- the nucleation promotion layer is a sub-monolayer. In this regard, a sub-monolayer need not cover the entire surface of the semiconductor body.
- the sub-monolayer implementation does not provide nucleation promoting metal, metal silicide, or metal silicate over every portion of the semiconductor surface, the provision of some such molecules on the semiconductor body surface at 10 increases the nucleation site density and hence advantageously improves the nucleation of high-k material in the subsequent CVD high-k deposition at 12 .
- the nucleation promotion layer may be formed at 10 using any appropriate material deposition technique, such as PVD, CVD, or others.
- the nucleation promotion layer and the high-k dielectric layer are both formed by CVD processing in-situ in a single chemical vapor deposition process chamber at 10 and 12 .
- process pressures in the range of single digit mtorr up to tens of Torr may be employed, with lower pressure being preferable to facilitate control of the deposited material flux to the surface.
- One example is performed in an inert environment or an oxidizing environment (e.g., Ar or Ar with 0), and other implementations employ a reducing environment, such as hydrogen, ammonia, etc.
- a first step may employ essentially the same or similar process conditions at 10 as used for the bulk high-k deposition process at 12 , but including only a hafnium precursor, for example, at 10 .
- the process step at 10 may be continued to form a sub-monolayer, monolayer, or a thin film.
- a reducing or an oxidizing ambient may be provided (e.g., by co-flowing appropriate hydrogen, ammonia, oxygen, etc.) to clean away all the ligands present on the precursor.
- the nucleation promotion layer is formed by PVD sputter processing at 10 using process pressures in the mtorr range using relatively low RF power, such as less than 100 W across an 8 inch wafer (e.g., power density of about 324 W/cm 2 or less) using an Ar process gas for sputtering a hafnium target.
- FIGS. 2 - 6 an exemplary semiconductor device 102 is illustrated undergoing processing at various stages of manufacturing in accordance with various aspects of the invention, wherein the structures illustrated herein are not necessarily drawn to scale.
- the device 102 is illustrated comprising a wafer having a semiconductor body 104 therein, such as a silicon substrate or a layer of silicon overlying an insulator in an SOI device wafer, wherein the exemplary semiconductor body 104 is a lightly doped p-type silicon substrate.
- STI isolation structures 112 are formed in the body 104 via an isolation process 114 , which separate and provide electrical isolation between active areas, although other isolation structures may be provided, for example, using LOCOS techniques as are known.
- One or more p and/or n-type wells are then formed in the semiconductor body 104 , including an n-well 118 , and an optional wet clean or HF deglaze operation 116 may be performed to clean the top surface of the semiconductor body 104 .
- an intentional interface layer (not shown) may optionally be formed over the semiconductor body 104 via any appropriate process steps before nucleation layer deposition.
- a PVD, CVD or other deposition process 122 is performed to deposit a thin nucleation promotion layer 120 comprising a metal, a metal silicide, or a metal silicate over all or a portion of the upper surface of the semiconductor body 104 (e.g., or over any intentional interface layer or layers, not shown).
- the nucleation promotion layer 120 is a thin hafnium film with a thickness less than about 10 ⁇ .
- Other examples include formation of a nucleation promotion monolayer 120 , for example, having an average thickness on the order of one or a few A.
- the nucleation promotion layer 120 is a sub-monolayer, which need not cover the entire surface of the semiconductor body 104 .
- a high-k dielectric layer 130 is deposited over the nucleation promotion layer 120 via a CVD deposition process 132 as described above, wherein the processes 122 and 132 may, but need not, be performed in-situ in a single CVD process chamber or tool.
- the high-k dielectric layer 130 comprises any appropriate high-k dielectric material, such as those mentioned above, formed to any desired thickness, such as 10-100 ⁇ , for example 20-25 ⁇ .
- a gate contact layer 140 such as metal, polysilicon or equivalent is deposited over the high-k material 130 via a deposition process 142 .
- the gate contact layer 140 and the high-k dielectric layer 130 are then patterned to form a transistor gate structure.
- Source/drain regions 150 are doped with p-type impurities on either side of a channel region 152 in the semiconductor body 104 , and sidewall spacers 160 are formed along the sides of the patterned layers 120 , 130 , and 140 as illustrated in FIG. 8.
- interconnect processing (not shown) is performed to interconnect the illustrated MOS type transistor and other electrical components in the device 102 .
- FIG. 7 another aspect of the invention provides methods for fabricating a transistor gate structure, in which an intentional interface layer is formed over the semiconductor body, and a nucleation promotion layer is formed over the intentional interface layer prior to deposition of high-k gate dielectric material.
- the inventors have appreciated that forming a nucleation promotion layer over the intentional interface layer provides an increased number or higher density of nucleation sites for deposition of high-k material, thereby promoting uniform formation of high-k dielectric material without the degree of upper surface roughness found in conventional CVD processes.
- An exemplary method 202 is illustrated in FIG. 7 in accordance with this aspect of the invention.
- an intentional interface layer is formed at 206 over a substrate or other semiconductor body, using any appropriate materials and deposition or thermal growth techniques as are known. Moreover, the intentional interface may be formed to any desired thickness at 206 in accordance with the present invention.
- a gate dielectric is then created at 208 by forming a nucleation promotion layer over the semiconductor body at 210 and depositing high-k material using a CVD deposition process at 212 .
- the nucleation promotion layer formed comprises a metal, a metal silicide, or a metal silicate, which may be formed at 210 using any appropriate material deposition technique, such as PVD, CVD, or others.
- the high-k dielectric layer comprises a high-k oxide, oxynitride, or nitride, such as hafnium oxide (HfO 2 ), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON) or others, although any of the above-mentioned high-k materials may be employed at 212 .
- HfO 2 hafnium oxide
- HfON hafnium oxynitride
- HfSiON hafnium silicon oxynitride
- a gate contact layer such as metal, polysilicon, or equivalent, is then deposited at 214 over the high-k dielectric layer, and the gate contact layer and the high-k dielectric layer are patterned using any appropriate photolithographic techniques at 216 to form a gate structure, before the gate fabrication method 202 ends at 218 .
- the exemplary method 202 facilitates reduction in the amount of roughness at the upper surface of the high-k dielectric material, which in turn facilitates EOT scaling, gate leakage current reduction, and increased device reliability through improved uniformity in electrical and material properties.
- the nucleation promotion layer formed at 210 may comprise any metal, metal silicate, or metal silicide in accordance with the present invention.
- the nucleation promotion layer preferably comprises the same metal, a silicide of the metal, or a silicate of the metal.
- the nucleation promotion layer preferably comprises hafnium, a silicide of hafnium, or a silicate of hafnium.
- the nucleation promotion layer is preferably thin, such as having a thickness of about 10 ⁇ or less.
- the nucleation promotion layer formed at 210 is a monolayer, for example, having an average thickness on the order of one or a few ⁇ .
- the nucleation promotion layer is a sub-monolayer.
- the nucleation promotion layer may be formed at 210 using any appropriate material deposition technique, such as PVD, CVD, or others.
- the nucleation promotion layer and the high-k dielectric layer are formed at 210 and 212 by CVD processing in-situ in a single chemical vapor deposition process chamber, such as using the process conditions described above.
Abstract
Methods are disclosed for fabricating transistor gate structures in which high-k dielectric layer roughness is reduced by formation of a nucleation promotion layer over the substrate or any intentional interface layers, and a high-k gate dielectric is formed over the nucleation promotion layer. The nucleation promotion layer has a thickness of 10 Å or less, such as a monolayer or a sub-monolayer, comprising a metal, a metal silicide, or a metal silicate, which promotes uniform chemical vapor deposition of high-k gate dielectric materials by increasing the density of nucleation sites on the substrate or intentional interface layer.
Description
- This invention relates generally to semiconductor devices and more particularly to methods for fabricating transistor gate structures and for reducing roughness in high-k gate dielectric layers in the manufacture of semiconductor devices.
- Field effect transistors (FETs) are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. Most common among these are metal-oxide-semiconductor field-effect transistors (MOSFETs), wherein a metal or polysilicon gate contact is energized to create an electric field in a channel region of a semiconductor body, by which current is allowed to conduct between a source region and a drain region of the semiconductor body. The source and drain regions are typically formed by adding dopants to targeted regions on either side of the channel region in a semiconductor substrate. A gate dielectric or gate oxide, such as silicon dioxide (SiO2), is formed over the channel region, typically by thermal oxidation. A gate electrode or gate contact (e.g., metal or doped polysilicon) is then formed over the gate dielectric, and the gate dielectric and gate contact materials are patterned to form a gate structure overlying the channel region of the substrate.
- The gate dielectric is an insulator material, which prevents large currents from flowing from the gate into the channel when a voltage is applied to the gate contact, while allowing such an applied gate voltage to set up an electric field in the channel region in a controllable manner. Continuing trends in semiconductor product manufacturing include reduction in electrical device feature sizes (scaling), as well as improvements in device performance in terms of device switching speed and power consumption. MOS transistor performance may be improved by reducing the distance between the source and the drain regions under the gate electrode of the device, known as the gate or channel length, and by reducing the thickness of the layer of gate oxide that is formed over the semiconductor surface.
- However, there are electrical and physical limitations on the extent to which thickness of gate dielectrics formed of SiO2 can be reduced. For example, very thin SiO2 gate dielectrics are prone to large gate tunneling leakage currents resulting from direct tunneling through the thin gate oxide when a gate voltage is applied. In addition, there are conventional limitations on the ability to form such thin oxide films with uniform thickness. Furthermore, thin SiO2 gate dielectric layers provide a poor diffusion barrier to impurities, for example, and may allow high boron dopant penetration into the underlying channel region of the silicon during fabrication of the source/drain regions.
- To address these shortcomings and limitations, recent efforts directed to MOS device scaling have focused on alternative dielectric materials which can be formed in a thicker layer than scaled SiO2, and yet which produce equivalent field effect performance. These materials generally have a dielectric constant “k” greater than that of SiO2, and are commonly referred to as high-k materials or high-k dielectrics. The relative performance of these high-k materials is often expressed as equivalent oxide thickness (EOT), because the alternative material layer may be thicker, while still providing the equivalent electrical effect of a much thinner layer of SiO2. Because the dielectric constant is higher, a thicker high-k dielectric layer can be deposited to avoid or mitigate tunneling leakage currents, while still achieving the required value of EOT that is comparable to the EOT value of a thinner layer of thermally grown SiO2. The reduction in transistor gate equivalent oxide thickness is sometimes referred to as EOT scaling.
- High-k dielectrics are typically deposited directly over a silicon substrate to form a gate dielectric layer using chemical vapor deposition (CVD), atomic layer CVD(AL-CVD), plasma enhanced CVD (PECVD) or physical vapor deposition (PVD) processes such as sputtering. One shortcoming in forming high-k gate dielectric films using conventional CVD processes is rough surface morphology, leading to limitations of the ability to implement EOT scaling and degradation of device performance. In particular, roughness in the upper surface of the high-k dielectric layer in a transistor gate impedes EOT scaling efforts because the film appears electrically thicker in some locations and thinner in others. In this regard, thin portions of the resulting gate dielectric suffer from higher leakage currents than thicker portions, while the thicker portions have higher EOT than the thinner portions. As the high-k film thickness is scaled down, the upper surface roughness becomes more significant, whereby effective limitations arise in the ability to further scale the dielectric. Therefore, there is a need for improved gate fabrication techniques by which roughness in CVD deposited high-k dielectrics films may be reduced.
- The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. The invention relates to methods for fabricating transistor gate structures and high-k dielectric layers therefor using CVD deposition processes, while reducing or avoiding the undesirable effects of high-k dielectric roughness, by which improved device performance and scalability may be achieved.
- In one aspect of the invention, methods are provided for fabricating transistor gate structures, in which a nucleation promotion layer is formed over a substrate or other semiconductor body. The nucleation promotion layer comprises a metal, metal silicide, or a metal silicate, which increases the density of nucleation sites on the substrate surface. During subsequent CVD deposition of high-k gate dielectric material, the high density of nucleation sites promotes uniform formation of high-k dielectric material on the substrate with reduced roughness at the top surface of the high-k layer. The nucleation promotion layer thus facilitates EOT scaling, gate leakage current reduction, and increased device reliability through improved uniformity in electrical and material properties.
- The nucleation promotion layer may be formed using CVD, PVD or other deposition processes. In one possible implementation, the nucleation promotion layer and the high-k dielectric layer are both formed in-situ in a single chemical vapor deposition process chamber. The nucleation promotion layer, moreover, may be a very thin film, such as about 10 Å or less in thickness, preferably a monolayer or sub-monolayer. In addition, where the high-k dielectric layer is a compound material comprising a metal such as hafnium, the nucleation promotion layer may advantageously comprises the same metal, a silicide of the metal, or a silicate of the metal, so as to facilitate nucleation in the initial stages of high-k CVD deposition.
- Another aspect of the invention provides methods for fabricating a transistor gate structure, which comprises forming an intentional interface layer over the semiconductor body, and forming a nucleation promotion layer over the intentional interface layer. Thereafter, a high-k dielectric layer is formed over the nucleation promotion layer using a chemical vapor deposition process. The nucleation promotion layer overlying the intentional interface layer provides an increased number of nucleation sites for deposition of high-k material on the intentional interface, thereby promoting uniform formation of high-k dielectric material without the degree of upper surface roughness found in conventional CVD processes. Yet another aspect of the invention provides methods for reducing high-k gate dielectric roughness in the fabrication of a transistor gate structure, comprising forming a nucleation promotion layer over a semiconductor body or an intentional interface layer, where the nucleation promotion layer comprising a metal, a metal silicide, or a metal silicate. The method further comprises forming a high-k dielectric layer over the nucleation promotion layer using a chemical vapor deposition process.
- To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.
- FIG. 1 is a flow diagram illustrating an exemplary method of fabricating transistor gate structures including formation of a nucleation promotion layer over a substrate or other semiconductor body prior to CVD deposition of high-k materials in accordance with one or more aspects of the present invention;
- FIGS.2-6 are partial side elevation views in section illustrating an exemplary semiconductor device being processed at various stages of manufacturing in accordance with various aspects of the invention; and
- FIG. 7 is a flow diagram illustrating another exemplary method of fabricating transistor gate structures including formation of a nucleation promotion layer over an intentional interface layer before CVD deposition of high-k materials in accordance with one or more aspects of the present invention; and
- One or more implementations of the present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout. The invention relates to methods for fabricating gate structures in a semiconductor device, which may be employed in association with any type of semiconductor body, including silicon or other semiconductor substrates, as well as silicon or other semiconductor layers overlying an insulator region or layer in an SOI device.
- The inventors have appreciated that mobility, scalability, and other performance and issues are negatively impacted by roughness at the top surface of a gate dielectric layer, which may occur during CVD deposition of high-k dielectric materials in the manufacture of transistor devices. Although not wishing to be tied to any particular theory, these problems are believed to be primarily the result of low nucleation site density on the surface of a semiconductor body or intentional interface layer during initial stages of CVD deposition. As a precursor molecule or atom approaches the surface, it is believed to land on the surface, and may move around on the surface until it finds the lowest energy site. Subsequently, other precursor molecules approaching the surface near the first precursor molecule will preferentially adhere to the substrate near the first precursor, thereby forming an island of high-k material. Islands of high-k materials form in like manner at different locations, which are spatially separated from one another.
- These growth sites or islands eventually coalesce as the CVD process continues. However, where the initial nucleation sites are widely dispersed on the surface of the substrate or intentional interface layer due to a low density of nucleation sites in silicon or many intentional interface layers (e.g., SiO2 or others), the growth sites do not coalesce to form a cohesive film until relatively late in the process. At this point, the high-k material may be several molecule thicknesses at some locations, but only one molecule thickness at the recently joined locations. Where the finished high-k dielectric layer is relatively thin, the deposition process is fairly short, in which case the thickness variation or roughness is present in the top surface of the finished high-k layer. This roughness has been found to be on the order of one or two monolayers or around 3-10 Å in a high-k layer of about 30 Å thickness, because of which the leakage current reduction advantages of using high-k films may not be fully attainable.
- The present invention provides more low energy nucleation sites across the wafer or intentional interface layer, by formation of a nucleation promotion layer to create more uniformity in attracting precursor molecules during subsequent chemical vapor deposition of high-k materials. While not wishing to be tied to any particular theory, it is believed that formation of a thin layer of metal, metal silicide, or metal silicate increases the number of locations or sites where the growth of high-k material begins in a chemical vapor deposition process. Further, it is believed that the closer these initial nucleation sites are, the more likely the high-k deposition will occur through layer-by-layer growth or that the islands of high-k will coalesce to form a cohesive film early in the deposition process, by which variations in the finished high-k layer thickness are reduced or avoided.
- Referring initially to FIG. 1, an
exemplary method 2 is illustrated for fabricating a transistor gate structure in accordance with one or more aspects of the present invention. The methods of the current invention involve the formation of a nucleation promotion layer on a semiconductor body or interface layer in order to enhance nucleation site density and thereby reduce surface roughness or non-uniformity in high-k dielectric material deposited over the nucleation promotion layer. Although theexemplary method 2 and other methods herein are illustrated and described below as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein, in accordance with the invention. In addition, not all illustrated steps may be required to implement a methodology in accordance with the present invention. Furthermore, the methods according to the present invention may be implemented in association with the fabrication and/or processing of the transistor gate structures and high-k dielectric films therefor which are illustrated and described herein as well as in association with other structures and films not illustrated. - Gate fabrication in the
method 2 begins at 4, where a wet clean or HF deglaze operation may optionally be performed at 6 to remove any thin dielectric layers from the semiconductor body, such as silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON). For removing SiO, wet cleaning operations can be performed at 6, or a dilute HF solution may be employed to deglaze the semiconductor body. One example of such an HF deglaze involves dipping the semiconductor in a 1:100 volume dilution of 49% HF at room temperature for a duration that is adequate to completely remove any SiO from the surface. In another example, a dry process is employed comprising a mixture of anhydrous HF and isopropyl-alcohol to remove SiO. - A gate dielectric is then processed at8, including forming a nucleation promotion layer over the semiconductor body at 10, where the nucleation promotion layer comprises a metal, a metal silicide, or a metal silicate. The nucleation promotion layer may be formed at 10 using any appropriate material deposition technique, such as PVD, CVD, or others. Thereafter, a high-k dielectric layer is formed at 12 over the nucleation promotion layer using a chemical vapor deposition process. The invention may be employed in association with CVD deposition of any high-k dielectric layer material at 12 to any desired thickness, such as 10-100 Å, for example 20-25 Å, where the nucleation promotion layer may be formed at 10 over a silicon or other semiconductor substrate or any type of semiconductor body. In one example, the high-k dielectric layer comprises a high-k oxide, oxynitride, or nitride, such as hafnium oxide (HfO2), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON) or others. However, the invention is not limited to these materials.
- High-k materials which may be deposited in association with the present invention may include, but are not limited to binary metal oxides including aluminum oxide (Al2O3), zirconium oxide (ZrO2), hafnium oxide (HfO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), titanium oxide (TiO2), as well as their silicates and aluminates; metal oxynitrides including aluminum oxynitride (AlON), zirconium oxynitride (ZrON), hafnium oxynitride (HfON), lanthanum oxynitride (LaON), yttrium oxynitride (YON), as well as their silicates and aluminates such as ZrSiON, HfSiON, LaSiON, YsiON etc.; and perovskite-type oxides including a titanate system material such as barium titanate, strontium titanate, barium strontium titanate (BST), lead titanate, lead zirconate titanate, lead lanthanum zirconate titanate, barium lanthanum titanate, barium zirconium titanate; a niobate or tantalate system material such as lead magnesium niobate, lithium niobate, lithium tantalate, potassium niobate, strontium aluminum tantalate and potassium tantalum niobate; a tungsten-bronze system material such as barium strontium niobate, lead barium niobate, barium titanium niobate; and Bi-layered perovskite system material such as strontium bismuth tantalate, bismuth titanate as are known in the art.
- A gate contact layer, such as metal, polysilicon, or equivalent, is then deposited at14 over the high-k dielectric layer, and the gate contact layer and the high-k dielectric layer are patterned using any appropriate photolithographic techniques (e.g., patterned etching, etc.) at 16 to form a gate structure, before the
gate fabrication method 2 ends at 18. Themethod 2 facilitates reduction in the amount of roughness at the upper surface of the high-k dielectric material, which in turn facilitates EOT scaling, gate leakage current reduction, and increased device reliability through improved uniformity in electrical and material properties. - The nucleation promotion layer formed at10 may comprise any metal, metal silicate, or metal silicide in accordance with the present invention. In one implementation, where the high-k dielectric layer is a compound material comprising a metal, the nucleation promotion layer preferably comprises the metal, a silicide of the metal, or a silicate of the metal. For example, in the case where the high-k dielectric layer comprises a high-k oxide, oxynitride, or nitride, such as hafnium oxide (HfO2), hafnium oxynitride (HfON), or hafnium silicon oxynitride (HfSiON), etc., the nucleation promotion layer preferably comprises hafnium, a silicide of hafnium, or a silicate of hafnium. In this aspect of the invention, the employment of the same metal constituent in the nucleation promotion and high-k dielectric layers is believed to further enhance uniform nucleation of high-k precursor molecules, particularly in the initial stages of CVD deposition at 12, whereby upper surface roughness is reduced in the deposited high-k dielectric layer.
- The nucleation promotion layer, moreover, is preferably thin, such as having a thickness of about 10 Å or less. In one implementation, the nucleation promotion layer formed at10 is a monolayer, for example, having an average thickness on the order of one or a few Å. In another preferred implementation, the nucleation promotion layer is a sub-monolayer. In this regard, a sub-monolayer need not cover the entire surface of the semiconductor body. Although the sub-monolayer implementation does not provide nucleation promoting metal, metal silicide, or metal silicate over every portion of the semiconductor surface, the provision of some such molecules on the semiconductor body surface at 10 increases the nucleation site density and hence advantageously improves the nucleation of high-k material in the subsequent CVD high-k deposition at 12.
- As discussed above, moreover, the nucleation promotion layer may be formed at10 using any appropriate material deposition technique, such as PVD, CVD, or others. In one implementation, the nucleation promotion layer and the high-k dielectric layer are both formed by CVD processing in-situ in a single chemical vapor deposition process chamber at 10 and 12. For a CVD case, process pressures in the range of single digit mtorr up to tens of Torr may be employed, with lower pressure being preferable to facilitate control of the deposited material flux to the surface. One example is performed in an inert environment or an oxidizing environment (e.g., Ar or Ar with 0), and other implementations employ a reducing environment, such as hydrogen, ammonia, etc. In the in-situ case, a first step may employ essentially the same or similar process conditions at 10 as used for the bulk high-k deposition process at 12, but including only a hafnium precursor, for example, at 10. In this case, the process step at 10 may be continued to form a sub-monolayer, monolayer, or a thin film. Thereafter at 12, a reducing or an oxidizing ambient may be provided (e.g., by co-flowing appropriate hydrogen, ammonia, oxygen, etc.) to clean away all the ligands present on the precursor.
- In either CVD or PVD nucleation promotion layer formation, another possible approach involves two process chambers or tools, such as performing a PVD first step to deposit a thin metal, metal silicide, or metal silicate nucleation promotion layer on the wafer at10, and then transferring the wafer into a CVD chamber for high-k deposition at 12. In one implementation, the nucleation promotion layer is formed by PVD sputter processing at 10 using process pressures in the mtorr range using relatively low RF power, such as less than 100 W across an 8 inch wafer (e.g., power density of about 324 W/cm2 or less) using an Ar process gas for sputtering a hafnium target.
- Referring now to FIGS.2-6, an
exemplary semiconductor device 102 is illustrated undergoing processing at various stages of manufacturing in accordance with various aspects of the invention, wherein the structures illustrated herein are not necessarily drawn to scale. In FIG. 2, thedevice 102 is illustrated comprising a wafer having asemiconductor body 104 therein, such as a silicon substrate or a layer of silicon overlying an insulator in an SOI device wafer, wherein theexemplary semiconductor body 104 is a lightly doped p-type silicon substrate. STI isolation structures 112 (e.g., SiO2) are formed in thebody 104 via an isolation process 114, which separate and provide electrical isolation between active areas, although other isolation structures may be provided, for example, using LOCOS techniques as are known. One or more p and/or n-type wells are then formed in thesemiconductor body 104, including an n-well 118, and an optional wet clean or HF deglazeoperation 116 may be performed to clean the top surface of thesemiconductor body 104. As discussed further below with respect to FIG. 7, an intentional interface layer (not shown) may optionally be formed over thesemiconductor body 104 via any appropriate process steps before nucleation layer deposition. - In FIG. 3, a PVD, CVD or
other deposition process 122 is performed to deposit a thinnucleation promotion layer 120 comprising a metal, a metal silicide, or a metal silicate over all or a portion of the upper surface of the semiconductor body 104 (e.g., or over any intentional interface layer or layers, not shown). In the illustrated example, thenucleation promotion layer 120 is a thin hafnium film with a thickness less than about 10 Å. Other examples include formation of anucleation promotion monolayer 120, for example, having an average thickness on the order of one or a few A. In another preferred implementation, thenucleation promotion layer 120 is a sub-monolayer, which need not cover the entire surface of thesemiconductor body 104. In FIG. 4, a high-k dielectric layer 130 is deposited over thenucleation promotion layer 120 via aCVD deposition process 132 as described above, wherein theprocesses k dielectric layer 130 comprises any appropriate high-k dielectric material, such as those mentioned above, formed to any desired thickness, such as 10-100 Å, for example 20-25 Å. - In FIG. 5, a
gate contact layer 140, such as metal, polysilicon or equivalent is deposited over the high-k material 130 via adeposition process 142. As illustrated in FIG. 5, thegate contact layer 140 and the high-k dielectric layer 130 are then patterned to form a transistor gate structure. Source/drain regions 150 are doped with p-type impurities on either side of achannel region 152 in thesemiconductor body 104, andsidewall spacers 160 are formed along the sides of thepatterned layers device 102. - Referring now to FIG. 7, another aspect of the invention provides methods for fabricating a transistor gate structure, in which an intentional interface layer is formed over the semiconductor body, and a nucleation promotion layer is formed over the intentional interface layer prior to deposition of high-k gate dielectric material. The inventors have appreciated that forming a nucleation promotion layer over the intentional interface layer provides an increased number or higher density of nucleation sites for deposition of high-k material, thereby promoting uniform formation of high-k dielectric material without the degree of upper surface roughness found in conventional CVD processes. An
exemplary method 202 is illustrated in FIG. 7 in accordance with this aspect of the invention. - Beginning at204, an intentional interface layer is formed at 206 over a substrate or other semiconductor body, using any appropriate materials and deposition or thermal growth techniques as are known. Moreover, the intentional interface may be formed to any desired thickness at 206 in accordance with the present invention. A gate dielectric is then created at 208 by forming a nucleation promotion layer over the semiconductor body at 210 and depositing high-k material using a CVD deposition process at 212. As with the above implementations, the nucleation promotion layer formed comprises a metal, a metal silicide, or a metal silicate, which may be formed at 210 using any appropriate material deposition technique, such as PVD, CVD, or others. This aspect of the invention may be employed in association with CVD deposition of any high-k dielectric layer material at 212 to any desired thickness, such as 10-100 Å, for example 20-25 Å, over the nucleation promotion layer. In one example, the high-k dielectric layer comprises a high-k oxide, oxynitride, or nitride, such as hafnium oxide (HfO2), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON) or others, although any of the above-mentioned high-k materials may be employed at 212.
- A gate contact layer, such as metal, polysilicon, or equivalent, is then deposited at214 over the high-k dielectric layer, and the gate contact layer and the high-k dielectric layer are patterned using any appropriate photolithographic techniques at 216 to form a gate structure, before the
gate fabrication method 202 ends at 218. Like the above techniques, theexemplary method 202 facilitates reduction in the amount of roughness at the upper surface of the high-k dielectric material, which in turn facilitates EOT scaling, gate leakage current reduction, and increased device reliability through improved uniformity in electrical and material properties. - The nucleation promotion layer formed at210 may comprise any metal, metal silicate, or metal silicide in accordance with the present invention. In one implementation, where the high-k dielectric layer is a compound material comprising a metal, the nucleation promotion layer preferably comprises the same metal, a silicide of the metal, or a silicate of the metal. For example, in the case where the high-k dielectric layer comprises a high-k oxide, oxynitride, or nitride, such as hafnium oxide (HfO2), hafnium oxynitride (HfON), or hafnium silicon oxynitride (HfSiON), etc., the nucleation promotion layer preferably comprises hafnium, a silicide of hafnium, or a silicate of hafnium. In addition, the nucleation promotion layer is preferably thin, such as having a thickness of about 10 Å or less. In one implementation, the nucleation promotion layer formed at 210 is a monolayer, for example, having an average thickness on the order of one or a few Å. In another preferred implementation, the nucleation promotion layer is a sub-monolayer. Furthermore, the nucleation promotion layer may be formed at 210 using any appropriate material deposition technique, such as PVD, CVD, or others. In one implementation, the nucleation promotion layer and the high-k dielectric layer are formed at 210 and 212 by CVD processing in-situ in a single chemical vapor deposition process chamber, such as using the process conditions described above.
- Although the invention has been illustrated and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term “comprising.”
Claims (26)
1. A method of fabricating a transistor gate structure, comprising:
forming a nucleation promotion layer over a semiconductor body, the nucleation promotion layer comprising a metal, a metal silicide, or a metal silicate;
forming a high-k dielectric layer over the nucleation promotion layer using a chemical vapor deposition process;
forming a gate contact layer over the high-k dielectric layer; and
patterning the gate contact layer and the high-k dielectric layer.
2. The method of claim 1 , wherein forming the nucleation promotion layer and forming the high-k dielectric layer are performed in-situ in a single chemical vapor deposition process chamber.
3. The method of claim 1 , wherein forming the nucleation promotion layer comprises performing one of a chemical vapor deposition process and a physical vapor deposition process.
4. The method of claim 1 , wherein the nucleation promotion layer has a thickness of about 10 Å or less.
5. The method of claim 4 , wherein the nucleation promotion layer is a monolayer.
6. The method of claim 4 , wherein the nucleation promotion layer is a sub-monolayer.
7. The method of claim 1 , wherein the high-k dielectric layer is a compound material comprising a metal, and wherein the nucleation promotion layer comprises the metal, a silicide of the metal, or a silicate of the metal.
8. The method of claim 7 , wherein the metal is hafnium.
9. The method of claim 7 , wherein the nucleation promotion layer has a thickness of about 10 Å or less.
10. The method of claim 9 , wherein the nucleation promotion layer is a monolayer or a sub-monolayer.
11. A method of fabricating a transistor gate structure, comprising:
forming at least one intentional interface layer over a semiconductor body;
forming a nucleation promotion layer over the intentional interface layer, the nucleation promotion layer comprising a metal, a metal silicide, or a metal silicate;
forming a high-k dielectric layer over the nucleation promotion layer using a chemical vapor deposition process;
forming a gate contact layer over the high-k dielectric layer; and
patterning the gate contact layer and the high-k dielectric layer.
12. The method of claim 11 , wherein forming the nucleation promotion layer and forming the high-k dielectric layer are performed in-situ in a single chemical vapor deposition process chamber.
13. The method of claim 11 , wherein forming the nucleation promotion layer comprises performing one of a chemical vapor deposition process and a physical vapor deposition process.
14. The method of claim 11 , wherein the nucleation promotion layer has a thickness of about 10 Å or less.
15. The method of claim 14 , wherein the nucleation promotion layer is a monolayer.
16. The method of claim 14 , wherein the nucleation promotion layer is a sub-monolayer.
17. The method of claim 11 , wherein the high-k dielectric layer is a compound material comprising a metal, and wherein the nucleation promotion layer comprises the metal, a silicide of the metal, or a silicate of the metal.
18. The method of claim 17 , wherein the metal is hafnium.
19. A method of reducing high-k gate dielectric roughness in the fabrication of a transistor gate structure, the method comprising:
forming a nucleation promotion layer over a semiconductor body or an intentional interface layer, the nucleation promotion layer comprising a metal, a metal silicide, or a metal silicate; and
forming a high-k dielectric layer over the nucleation promotion layer using a chemical vapor deposition process.
20. The method of claim 19 , wherein forming the nucleation promotion layer and forming the high-k dielectric layer are performed in-situ in a single chemical vapor deposition process chamber.
21. The method of claim 19 , wherein forming the nucleation promotion layer comprises performing one of a chemical vapor deposition process and a physical vapor deposition process.
22. The method of claim 19 , wherein the nucleation promotion layer has a thickness of about 10 Å or less.
23. The method of claim 22 , wherein the nucleation promotion layer is a monolayer.
24. The method of claim 22 , wherein the nucleation promotion layer is a sub-monolayer.
25. The method of claim 19 , wherein the high-k dielectric layer is a compound material comprising a metal, and wherein the nucleation promotion layer comprises the metal, a silicide of the metal, or a silicate of the metal.
26. The method of claim 25 , wherein the metal is hafnium.
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US10/335,557 US6762114B1 (en) | 2002-12-31 | 2002-12-31 | Methods for transistor gate fabrication and for reducing high-k gate dielectric roughness |
EP03104979A EP1435649A3 (en) | 2002-12-31 | 2003-12-24 | Methods of forming a transistor gate |
JP2003429603A JP2004214661A (en) | 2002-12-31 | 2003-12-25 | Manufacturing of transistor gate and method for decreasing roughness of high dielectric constant gate dielectric |
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US10/335,557 US6762114B1 (en) | 2002-12-31 | 2002-12-31 | Methods for transistor gate fabrication and for reducing high-k gate dielectric roughness |
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JP (1) | JP2004214661A (en) |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050124109A1 (en) * | 2003-12-03 | 2005-06-09 | Texas Instruments Incorporated | Top surface roughness reduction of high-k dielectric materials using plasma based processes |
US20050167768A1 (en) * | 2003-03-17 | 2005-08-04 | Fujitsu Limited | Manufacture of semiconductor device having insulation film of high dielectric constant |
US7709402B2 (en) | 2006-02-16 | 2010-05-04 | Micron Technology, Inc. | Conductive layers for hafnium silicon oxynitride films |
US7759747B2 (en) | 2006-08-31 | 2010-07-20 | Micron Technology, Inc. | Tantalum aluminum oxynitride high-κ dielectric |
US7776765B2 (en) | 2006-08-31 | 2010-08-17 | Micron Technology, Inc. | Tantalum silicon oxynitride high-k dielectrics and metal gates |
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US7915174B2 (en) | 2004-12-13 | 2011-03-29 | Micron Technology, Inc. | Dielectric stack containing lanthanum and hafnium |
US7972974B2 (en) | 2006-01-10 | 2011-07-05 | Micron Technology, Inc. | Gallium lanthanide oxide films |
US7989362B2 (en) | 2006-08-31 | 2011-08-02 | Micron Technology, Inc. | Hafnium lanthanide oxynitride films |
US8084370B2 (en) | 2006-08-31 | 2011-12-27 | Micron Technology, Inc. | Hafnium tantalum oxynitride dielectric |
US20120202358A1 (en) * | 2005-08-30 | 2012-08-09 | Dan Gealy | Graded dielectric structures |
US8278225B2 (en) | 2005-01-05 | 2012-10-02 | Micron Technology, Inc. | Hafnium tantalum oxide dielectrics |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8026161B2 (en) | 2001-08-30 | 2011-09-27 | Micron Technology, Inc. | Highly reliable amorphous high-K gate oxide ZrO2 |
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US7160577B2 (en) | 2002-05-02 | 2007-01-09 | Micron Technology, Inc. | Methods for atomic-layer deposition of aluminum oxides in integrated circuits |
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US7183186B2 (en) | 2003-04-22 | 2007-02-27 | Micro Technology, Inc. | Atomic layer deposited ZrTiO4 films |
US7049192B2 (en) * | 2003-06-24 | 2006-05-23 | Micron Technology, Inc. | Lanthanide oxide / hafnium oxide dielectrics |
US7258895B2 (en) * | 2003-08-06 | 2007-08-21 | Micron Technology, Inc. | Methods of forming material on a substrate, and a method of forming a field effect transistor gate oxide on a substrate |
US7588988B2 (en) | 2004-08-31 | 2009-09-15 | Micron Technology, Inc. | Method of forming apparatus having oxide films formed using atomic layer deposition |
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US7927948B2 (en) | 2005-07-20 | 2011-04-19 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
US20070066021A1 (en) | 2005-09-16 | 2007-03-22 | Texas Instruments Inc. | Formation of gate dielectrics with uniform nitrogen distribution |
JP4868910B2 (en) * | 2006-03-30 | 2012-02-01 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
US7432548B2 (en) | 2006-08-31 | 2008-10-07 | Micron Technology, Inc. | Silicon lanthanide oxynitride films |
US8962078B2 (en) | 2012-06-22 | 2015-02-24 | Tokyo Electron Limited | Method for depositing dielectric films |
Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5861763A (en) * | 1981-10-09 | 1983-04-12 | 武笠 均 | Feel sensor fire fighting apparatus |
US6320238B1 (en) | 1996-12-23 | 2001-11-20 | Agere Systems Guardian Corp. | Gate structure for integrated circuit fabrication |
US6063698A (en) * | 1997-06-30 | 2000-05-16 | Motorola, Inc. | Method for manufacturing a high dielectric constant gate oxide for use in semiconductor integrated circuits |
US6020243A (en) * | 1997-07-24 | 2000-02-01 | Texas Instruments Incorporated | Zirconium and/or hafnium silicon-oxynitride gate dielectric |
US6451677B1 (en) | 1998-02-23 | 2002-09-17 | Texas Instruments Incorporated | Plasma-enhanced chemical vapor deposition of a nucleation layer in a tungsten metallization process |
US6251761B1 (en) | 1998-11-24 | 2001-06-26 | Texas Instruments Incorporated | Process for polycrystalline silicon gates and high-K dielectric compatibility |
US6303940B1 (en) | 1999-01-26 | 2001-10-16 | Agere Systems Guardian Corp. | Charge injection transistor using high-k dielectric barrier layer |
US6297539B1 (en) * | 1999-07-19 | 2001-10-02 | Sharp Laboratories Of America, Inc. | Doped zirconia, or zirconia-like, dielectric film transistor structure and deposition method for same |
US6060755A (en) * | 1999-07-19 | 2000-05-09 | Sharp Laboratories Of America, Inc. | Aluminum-doped zirconium dielectric film transistor structure and deposition method for same |
US6207584B1 (en) * | 2000-01-05 | 2001-03-27 | International Business Machines Corp. | High dielectric constant material deposition to achieve high capacitance |
US6448127B1 (en) | 2000-01-14 | 2002-09-10 | Advanced Micro Devices, Inc. | Process for formation of ultra-thin base oxide in high k/oxide stack gate dielectrics of mosfets |
US6407435B1 (en) | 2000-02-11 | 2002-06-18 | Sharp Laboratories Of America, Inc. | Multilayer dielectric stack and method |
US6271094B1 (en) | 2000-02-14 | 2001-08-07 | International Business Machines Corporation | Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance |
WO2001086708A2 (en) * | 2000-05-09 | 2001-11-15 | Motorola, Inc. | Amorphous metal oxide gate dielectric structure |
US6184072B1 (en) | 2000-05-17 | 2001-02-06 | Motorola, Inc. | Process for forming a high-K gate dielectric |
US6444592B1 (en) | 2000-06-20 | 2002-09-03 | International Business Machines Corporation | Interfacial oxidation process for high-k gate dielectric process integration |
US6380104B1 (en) | 2000-08-10 | 2002-04-30 | Taiwan Semiconductor Manufacturing Company | Method for forming composite gate dielectric layer equivalent to silicon oxide gate dielectric layer |
US6495474B1 (en) * | 2000-09-11 | 2002-12-17 | Agere Systems Inc. | Method of fabricating a dielectric layer |
US6939816B2 (en) | 2000-11-10 | 2005-09-06 | Texas Instruments Incorporated | Method to improve the uniformity and reduce the surface roughness of the silicon dielectric interface |
US6927435B2 (en) * | 2001-01-16 | 2005-08-09 | Renesas Technology Corp. | Semiconductor device and its production process |
US6524651B2 (en) * | 2001-01-26 | 2003-02-25 | Battelle Memorial Institute | Oxidized film structure and method of making epitaxial metal oxide structure |
US6844604B2 (en) * | 2001-02-02 | 2005-01-18 | Samsung Electronics Co., Ltd. | Dielectric layer for semiconductor device and method of manufacturing the same |
US6514828B2 (en) * | 2001-04-20 | 2003-02-04 | Micron Technology, Inc. | Method of fabricating a highly reliable gate oxide |
US6709989B2 (en) * | 2001-06-21 | 2004-03-23 | Motorola, Inc. | Method for fabricating a semiconductor structure including a metal oxide interface with silicon |
US6511925B1 (en) * | 2001-10-19 | 2003-01-28 | Lsi Logic Corporation | Process for forming high dielectric constant gate dielectric for integrated circuit structure |
US6455330B1 (en) | 2002-01-28 | 2002-09-24 | Taiwan Semiconductor Manufacturing Company | Methods to create high-k dielectric gate electrodes with backside cleaning |
US7449385B2 (en) * | 2002-07-26 | 2008-11-11 | Texas Instruments Incorporated | Gate dielectric and method |
-
2002
- 2002-12-31 US US10/335,557 patent/US6762114B1/en not_active Expired - Lifetime
-
2003
- 2003-12-24 EP EP03104979A patent/EP1435649A3/en not_active Withdrawn
- 2003-12-25 JP JP2003429603A patent/JP2004214661A/en not_active Abandoned
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Also Published As
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US6762114B1 (en) | 2004-07-13 |
JP2004214661A (en) | 2004-07-29 |
EP1435649A2 (en) | 2004-07-07 |
EP1435649A3 (en) | 2005-01-05 |
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