US20040108541A1 - Floating gate and method of fabricating the same - Google Patents

Floating gate and method of fabricating the same Download PDF

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US20040108541A1
US20040108541A1 US10/725,050 US72505003A US2004108541A1 US 20040108541 A1 US20040108541 A1 US 20040108541A1 US 72505003 A US72505003 A US 72505003A US 2004108541 A1 US2004108541 A1 US 2004108541A1
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layer
floating gate
protruding
gate
tip
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Ying-Cheng Chuang
Chung-Lin Huang
Chi-Hui Lin
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate

Definitions

  • the invention is related to a floating gate, and more particularly to a floating gate with multiple tips and a method for fabricating the same.
  • Non-volatile semiconductor memory includes read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash EEPROM.
  • ROM read only memory
  • PROM programmable read only memory
  • EPROM erasable programmable read only memory
  • EEPROM electrically erasable programmable read only memory
  • flash EEPROM flash EEPROM
  • EPROM electrically programmed, but for erasing, still requires exposure to ultraviolet (UV) light.
  • EEPROM devices have the advantage of electrical programming and erasing, achieved by charging and discharging actions controlled by the control gate. The actions also affect the conductivity of the channel between source and drain.
  • flash memory has capacity for block-by-block memory erasure. Furthermore, memory erasure is fast, normally taking just 1 to 2 seconds for the complete removal of a whole block of memory. Another advantage of flash memory is low power consumption. The voltages of a control gate, a source, and a drain are adjusted to program or erase in a split gate flash memory.
  • FIGS. 1 a to 1 c are cross-sections of the conventional method for fabricating a floating gate of a split gate flash memory.
  • a silicon substrate 101 is provided.
  • a gate oxide layer 102 , a doped polysilicon layer 103 , and a nitride layer 104 having an opening 105 are sequentially formed on the silicon substrate 101 .
  • the doped polysilicon layer 105 exposed by the opening 105 is oxidized to form an oxide layer 106 with a Bird's Beak shape edge.
  • the nitride layer 104 is removed.
  • the doped polysilicon layer 103 is anisotropically etched to form a floating gate 103 a using the oxide layer 106 as an etching mask.
  • a split gate flash memory is completed after a control gate is formed on the floating gate and the silicon substrate 101 is implanted to form source/drain devices.
  • high voltage is applied between the source and drain. More high voltage is applied to the control gate and goes to the floating gate by the electric capacity coupling, and a high electric field is produced on the film gate oxide layer. The voltage is injected into the floating gate through the film gate oxide layer from the drain.
  • the die size is larger due to the addition of programming circuitry and there are more processing and testing steps involved in the manufacture of these types of memory devices.
  • the present invention is directed to a floating gate with multiple tips and a method for fabricating the same.
  • the present invention provides a method for forming a floating gate.
  • a semiconductor substrate is provided.
  • a gate dielectric layer, a conducting layer, and a patterned hard mask layer are sequentially formed on the surface of the semiconductor substrate.
  • the surface of the conducting layer is covered by the patterned hard mask layer to form a gate.
  • the conducting layer is etched to a predetermined depth to form an indentation using the patterned hard mask layer as a mask.
  • the conducting layer is oxidized to form an oxide layer on the surface of the conducting layer.
  • the oxide layer and the conducting layer are sequentially etched to form a multiple tip conducting layer as a floating gate using the patterned hard mask layer as a mask.
  • the patterned hard mask layer is removed.
  • the present invention also provides a method for forming a floating gate.
  • a semiconductor substrate is provided.
  • a gate dielectric layer, a conducting layer, a hard mask layer, and a patterned resist layer are sequentially formed on the surface of the semiconductor substrate.
  • the surface of the hard mask layer is covered by the patterned resist layer to form a gate.
  • the patterned resist layer is removed.
  • the conducting layer is etched to form a remaining conducting layer using the hard mask layer as a mask.
  • the remaining conducting layer is oxidized to form an oxide layer on the surface of the exposed conducting layer and the exposed remaining conducting layer.
  • the oxide layer and the conducting layer are sequentially etched to form a multiple tip conducting layer as a floating gate using the hard mask layer as a mask.
  • the hard mask layer and the exposed oxide layer are removed.
  • the present invention also provides a floating gate formed on the surface of the semiconductor substrate comprising a conductive base and a conductive protruding layer.
  • the conductive base has a first top portion and a first bottom portion. An edge of the first top portion is a first tip. The first bottom portion contacts the semiconductor substrate.
  • the conductive protruding layer protrudes from the conductive base.
  • the conductive protruding layer has a flat top.
  • the conductive protruding layer has a second top portion and a second bottom portion. An edge of the top portion is a second tip. The second bottom portion contacts the first top portion.
  • the conductive protruding layer has two concave sidewalls.
  • a multiple tip floating gate is composed of the conductive base and the conductive protruding layer.
  • the present invention also provides a floating gate formed on the semiconductor substrate, and a gate dielectric layer is formed between the floating gate and the semiconductor substrate.
  • the floating gate comprises a base poly layer and a protruding poly layer.
  • the base poly layer has a first top portion and a first bottom portion. An edge of the first top portion is a first tip. The first bottom portion contacts the gate dielectric layer.
  • the protruding poly layer protrudes from the base poly layer.
  • the protruding poly layer is flat top.
  • the protruding poly layer has a second top portion and a second bottom portion. An edge of the second portion is a second tip. The second bottom portion contacts the first top portion.
  • the protruding poly layer has two concave sidewalls.
  • a multiple tip floating gate is composed of the base poly layer and the protruding poly layer.
  • FIGS. 1 a to 1 c are cross-sections of the conventional method for fabricating a floating gate of a split gate flash memory
  • FIGS. 2 a to 2 f are cross-sections of the method for fabricating a multiple tip floating gate of a split gate flash memory of the present invention.
  • FIG. 2 g is the cross-section of the multiple tip floating gate of a split gate flash memory of the present invention.
  • FIGS. 2 a to 2 f are cross-sections of the method for fabricating a multiple tip floating gate of a split gate flash memory of the present invention.
  • a semiconductor substrate 201 such as silicon
  • a gate dielectric layer 202 such as gate oxide layer
  • a conducting layer 203 such as poly layer
  • a hard mask layer 204 such as nitride layer
  • a patterned resist layer 205 are sequentially formed on the surface of the semiconductor substrate 201 .
  • the hard mask layer 204 is etched to form a hard mask layer 204 a using the patterned resist 205 as an etching mask.
  • the patterned resist layer 205 is removed.
  • the conducting layer 203 is etched to form a protruding conducting layer 203 a and a remaining conducting layer 203 b using the hard mask layer 204 a as an etching mask.
  • the protruding conducting layer 203 a is formed under the hard mask layer 204 a
  • the remaining conducting layer 203 b is the conducting layer not covered by the hard mask layer 204 a .
  • the thickness of the remaining conducting layer 203 b is less than the protruding conducting layer 203 a.
  • the exposed protruding conducting layer 203 a and the exposed remaining conducting layer 203 b are oxidized to form an oxide layer 206 , such as silicon oxide layer, thereon.
  • the oxidizing process is thermal oxidation.
  • the oxide layer 206 and the remaining conducting layer 203 b are sequentially etched to form the oxide layer 206 a and the conducting layer 203 c using the hard mask layer 204 a as an etching mask.
  • the oxide layer 206 a is formed on the sidewall of the conducting layer 203 c , wherein a top edge of the conducting layer 203 c is a tip by the Bird's beak shape oxide layer, and a bottom edge of the conducting layer 203 c is also a tip.
  • the oxide layer 206 seals against oxygen, such that the conducting layer 203 c covered by the hard mask layer 204 a is not oxidized.
  • FIG. 2 f the hard mask layer 204 a and the exposed gate dielectric layer 202 are removed, and the gate dielectric layer 202 a under the conducting layer 203 c remains.
  • an inter-gate dielectric layer 207 such as oxide layer
  • a control gate 208 are sequentially formed on the multiple tip floating gate, and a complete flash memory is formed.
  • the multiple tip floating gate 203 c of the present invention is composed of a conductive base 203 d and a conductive protruding layer 203 e .
  • the conductive base 203 d has a first top portion and a first bottom portion, wherein an edge of the first top portion is a tip, and the first bottom portion contacts the semiconductor substrate 201 .
  • a gate dielectric layer 202 a is formed between the first bottom portion and the semiconductor substrate 201 .
  • the conductive protruding layer 203 e protrudes from the conductive base 203 d , and the conductive protruding layer 203 e has a flat top.
  • the conductive protruding layer 203 e has a second top portion and a second bottom portion, wherein the second top portion is a second tip, and the second bottom contacts the first top portion.
  • the conductive protruding layer 203 e has two concave sidewalls.
  • a multiple tip floating gate is composed of the conductive base 203 d and the conductive protruding layer 203 e.
  • the floating gate of the present invention provides a conducting layer 203 c with a tip of the top edge by the Bird's beak shape oxide layer and another tip of the bottom edge.

Abstract

A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which a gate dielectric layer, a conducting layer, and a patterned hard mask layer are sequentially formed. The surface of the conducting layer is covered by the patterned hard mask layer to form a gate. The conducting layer is etched to a predetermined depth to form an indentation using the patterned hard mask layer as a mask. The conducting layer is oxidized to form an oxide layer on the surface of the conducting layer. The oxide layer and the conducting layer are etched to form multiple tips using the patterned hard mask layer as a mask.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a divisional of co-pending U.S. application Ser. No. 10/436,800, filed on May 13, 2003.[0001]
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0002]
  • The invention is related to a floating gate, and more particularly to a floating gate with multiple tips and a method for fabricating the same. [0003]
  • 2. Description of the Related Art [0004]
  • Memory devices for non-volatile storage of information are currently in widespread use, in a myriad of applications. A few examples of non-volatile semiconductor memory include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash EEPROM. [0005]
  • An advantage of EPROM is that it is electrically programmed, but for erasing, still requires exposure to ultraviolet (UV) light. [0006]
  • In many circuit designs it is desirable to have a non-volatile memory device that can be erased and reprogrammed in-circuit, without the need to remove the device for erasing and reprogramming. [0007]
  • EEPROM devices have the advantage of electrical programming and erasing, achieved by charging and discharging actions controlled by the control gate. The actions also affect the conductivity of the channel between source and drain. [0008]
  • One of the advantages of flash memory is its capacity for block-by-block memory erasure. Furthermore, memory erasure is fast, normally taking just 1 to 2 seconds for the complete removal of a whole block of memory. Another advantage of flash memory is low power consumption. The voltages of a control gate, a source, and a drain are adjusted to program or erase in a split gate flash memory. [0009]
  • FIGS. 1[0010] a to 1 c are cross-sections of the conventional method for fabricating a floating gate of a split gate flash memory.
  • In FIG. 1[0011] a, a silicon substrate 101 is provided. A gate oxide layer 102, a doped polysilicon layer 103, and a nitride layer 104 having an opening 105 are sequentially formed on the silicon substrate 101.
  • In FIG. 1[0012] b, the doped polysilicon layer 105 exposed by the opening 105 is oxidized to form an oxide layer 106 with a Bird's Beak shape edge.
  • In FIG. 1[0013] c, the nitride layer 104 is removed. The doped polysilicon layer 103 is anisotropically etched to form a floating gate 103 a using the oxide layer 106 as an etching mask.
  • A split gate flash memory is completed after a control gate is formed on the floating gate and the [0014] silicon substrate 101 is implanted to form source/drain devices.
  • In the program step, high voltage is applied between the source and drain. More high voltage is applied to the control gate and goes to the floating gate by the electric capacity coupling, and a high electric field is produced on the film gate oxide layer. The voltage is injected into the floating gate through the film gate oxide layer from the drain. [0015]
  • In the erase step, high voltage is applied between the drain and the control gate. A high electric field is produced on the film gate oxide layer by the electric capacity coupling. The voltage is injected into the drain through the film gate oxide layer from the floating gate. The gate oxide layer is damaged by the high voltage. [0016]
  • When the edge of the floating gate is a tip, the electrical field is easily concentrated, and the point is easily discharged. If the point discharge is increased, erasing effect is stronger. [0017]
  • In addition, the die size is larger due to the addition of programming circuitry and there are more processing and testing steps involved in the manufacture of these types of memory devices. [0018]
    • SUMMARY OF THE INVENTION
  • The present invention is directed to a floating gate with multiple tips and a method for fabricating the same. [0019]
  • Accordingly, the present invention provides a method for forming a floating gate. A semiconductor substrate is provided. A gate dielectric layer, a conducting layer, and a patterned hard mask layer are sequentially formed on the surface of the semiconductor substrate. The surface of the conducting layer is covered by the patterned hard mask layer to form a gate. The conducting layer is etched to a predetermined depth to form an indentation using the patterned hard mask layer as a mask. The conducting layer is oxidized to form an oxide layer on the surface of the conducting layer. The oxide layer and the conducting layer are sequentially etched to form a multiple tip conducting layer as a floating gate using the patterned hard mask layer as a mask. The patterned hard mask layer is removed. [0020]
  • Accordingly, the present invention also provides a method for forming a floating gate. A semiconductor substrate is provided. A gate dielectric layer, a conducting layer, a hard mask layer, and a patterned resist layer are sequentially formed on the surface of the semiconductor substrate. The surface of the hard mask layer is covered by the patterned resist layer to form a gate. The patterned resist layer is removed. The conducting layer is etched to form a remaining conducting layer using the hard mask layer as a mask. The remaining conducting layer is oxidized to form an oxide layer on the surface of the exposed conducting layer and the exposed remaining conducting layer. The oxide layer and the conducting layer are sequentially etched to form a multiple tip conducting layer as a floating gate using the hard mask layer as a mask. The hard mask layer and the exposed oxide layer are removed. [0021]
  • Accordingly, the present invention also provides a floating gate formed on the surface of the semiconductor substrate comprising a conductive base and a conductive protruding layer. The conductive base has a first top portion and a first bottom portion. An edge of the first top portion is a first tip. The first bottom portion contacts the semiconductor substrate. The conductive protruding layer protrudes from the conductive base. The conductive protruding layer has a flat top. The conductive protruding layer has a second top portion and a second bottom portion. An edge of the top portion is a second tip. The second bottom portion contacts the first top portion. The conductive protruding layer has two concave sidewalls. A multiple tip floating gate is composed of the conductive base and the conductive protruding layer. [0022]
  • Accordingly, the present invention also provides a floating gate formed on the semiconductor substrate, and a gate dielectric layer is formed between the floating gate and the semiconductor substrate. The floating gate comprises a base poly layer and a protruding poly layer. The base poly layer has a first top portion and a first bottom portion. An edge of the first top portion is a first tip. The first bottom portion contacts the gate dielectric layer. The protruding poly layer protrudes from the base poly layer. The protruding poly layer is flat top. The protruding poly layer has a second top portion and a second bottom portion. An edge of the second portion is a second tip. The second bottom portion contacts the first top portion. The protruding poly layer has two concave sidewalls. A multiple tip floating gate is composed of the base poly layer and the protruding poly layer.[0023]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • For a better understanding of the present invention, reference is made to a detailed description to be read in conjunction with the accompanying drawings, in which: [0024]
  • FIGS. 1[0025] a to 1 c are cross-sections of the conventional method for fabricating a floating gate of a split gate flash memory;
  • FIGS. 2[0026] a to 2 f are cross-sections of the method for fabricating a multiple tip floating gate of a split gate flash memory of the present invention.
  • FIG. 2[0027] g is the cross-section of the multiple tip floating gate of a split gate flash memory of the present invention.
    • DETAILED DESCRIPTION OF THE INVENTION
  • FIGS. 2[0028] a to 2 f are cross-sections of the method for fabricating a multiple tip floating gate of a split gate flash memory of the present invention.
  • In FIG. 2[0029] a, a semiconductor substrate 201, such as silicon, is provided. A gate dielectric layer 202, such as gate oxide layer, a conducting layer 203, such as poly layer, a hard mask layer 204, such as nitride layer, and a patterned resist layer 205 are sequentially formed on the surface of the semiconductor substrate 201.
  • In FIG. 2[0030] b, the hard mask layer 204 is etched to form a hard mask layer 204 a using the patterned resist 205 as an etching mask. The patterned resist layer 205 is removed.
  • In FIG. 2[0031] c, the conducting layer 203 is etched to form a protruding conducting layer 203 a and a remaining conducting layer 203 b using the hard mask layer 204 a as an etching mask. The protruding conducting layer 203 a is formed under the hard mask layer 204 a, and the remaining conducting layer 203 b is the conducting layer not covered by the hard mask layer 204 a. The thickness of the remaining conducting layer 203 b is less than the protruding conducting layer 203 a.
  • In FIG. 2[0032] d, the exposed protruding conducting layer 203 a and the exposed remaining conducting layer 203 b are oxidized to form an oxide layer 206, such as silicon oxide layer, thereon. The oxidizing process is thermal oxidation.
  • In FIG. 2[0033] e, the oxide layer 206 and the remaining conducting layer 203 b are sequentially etched to form the oxide layer 206 a and the conducting layer 203 c using the hard mask layer 204 a as an etching mask. The oxide layer 206 a is formed on the sidewall of the conducting layer 203 c, wherein a top edge of the conducting layer 203 c is a tip by the Bird's beak shape oxide layer, and a bottom edge of the conducting layer 203 c is also a tip.
  • The [0034] oxide layer 206 seals against oxygen, such that the conducting layer 203 c covered by the hard mask layer 204 a is not oxidized.
  • In FIG. 2[0035] f, the hard mask layer 204 a and the exposed gate dielectric layer 202 are removed, and the gate dielectric layer 202 a under the conducting layer 203 c remains.
  • In FIG. 2[0036] g, an inter-gate dielectric layer 207, such as oxide layer, and a control gate 208 are sequentially formed on the multiple tip floating gate, and a complete flash memory is formed.
  • The multiple [0037] tip floating gate 203 c of the present invention is composed of a conductive base 203 d and a conductive protruding layer 203 e. The conductive base 203 d has a first top portion and a first bottom portion, wherein an edge of the first top portion is a tip, and the first bottom portion contacts the semiconductor substrate 201. A gate dielectric layer 202 a is formed between the first bottom portion and the semiconductor substrate 201. The conductive protruding layer 203 e protrudes from the conductive base 203 d, and the conductive protruding layer 203 e has a flat top. The conductive protruding layer 203 e has a second top portion and a second bottom portion, wherein the second top portion is a second tip, and the second bottom contacts the first top portion. The conductive protruding layer 203 e has two concave sidewalls. A multiple tip floating gate is composed of the conductive base 203 d and the conductive protruding layer 203 e.
  • The floating gate of the present invention provides a [0038] conducting layer 203 c with a tip of the top edge by the Bird's beak shape oxide layer and another tip of the bottom edge.
  • Concentration of the electric field easily occurs in the tip, and the point is easily discharged. Point discharge is increased because of the floating gate's multiple tips in the present invention. Therefore, data erasing for the flash memory having the floating gate with multiple tips is increased. [0039]
  • While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements. [0040]

Claims (4)

What is claimed is:
1. A floating gate formed on the surface of a semiconductor substrate, comprising:
a conductive base having a first top portion and a first bottom portion, wherein an edge of the first top is a first tip, and the first bottom portion contacts to the semiconductor substrate;
a conductive protruding layer protruding from the conductive base, and the conductive protruding layer has a flat top, wherein the conductive protruding layer has a second top portion and a second bottom portion, a edge of the second top portion is a second tip, the second bottom portion is connected to the first top portion, the conductive protruding layer has two concave sidewalls; and
wherein a multiple tip floating gate is composed of the conductive base and the conductive protruding layer.
2. The floating gate of claim 1, wherein the conductive base is a poly layer.
3. The floating gate of claim 1, wherein the conductive protruding layer is a poly layer.
4. A floating gate formed on the surface of a semiconductor substrate, with a gate dielectric layer formed between the floating gate and the semiconductor substrate, comprising:
a base poly layer having a first top portion and a first bottom portion, wherein an edge of the first top portion is a first tip, and the first bottom portion contacts to the gate dielectric layer; and
a protruding poly layer protruding from the base poly layer, and the protruding poly layer has a flat top, wherein the protruding poly layer has a second top portion and a second bottom portion, a edge of the second top portion is a second tip, the second bottom portion contacts the first top portion, the protruding poly layer has two concave sidewalls,
wherein a multiple tip floating gate is composed of the base poly layer and the protruding poly layer.
US10/725,050 2002-08-15 2003-12-01 Floating gate and method of fabricating the same Abandoned US20040108541A1 (en)

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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW544786B (en) * 2002-07-29 2003-08-01 Nanya Technology Corp Floating gate and method therefor
CA2479704C (en) * 2004-08-31 2013-08-13 Nova Chemicals Corporation High density homopolymer blends
KR100731115B1 (en) * 2005-11-04 2007-06-22 동부일렉트로닉스 주식회사 Flash memory device and method for fabricating the same
KR100854504B1 (en) * 2007-03-12 2008-08-26 삼성전자주식회사 Method of fabricating a flash memory device and flash memory device fabricated thereby
KR20090004155A (en) * 2007-07-06 2009-01-12 삼성전자주식회사 Nonvolatile memory device and method of forming the same
KR20110042614A (en) * 2009-10-19 2011-04-27 삼성전자주식회사 Semiconductor devices and methods of forming the same
US20200176609A1 (en) * 2018-11-29 2020-06-04 Vanguard International Semiconductor Corporation Flash memories and methods for forming the same
US11302827B2 (en) * 2020-01-23 2022-04-12 Nanya Technology Corp. Semiconductor device with sidewall oxidized dielectric and method for fabricating the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6136653A (en) * 1998-05-11 2000-10-24 Mosel Vitelic, Inc. Method and device for producing undercut gate for flash memory
US6656796B2 (en) * 2002-01-14 2003-12-02 Taiwan Semiconductor Manufacturing Co., Ltd Multiple etch method for fabricating split gate field effect transistor (FET) device
US20040245564A1 (en) * 2003-05-19 2004-12-09 Takayuki Ogura Semiconductor storage device, semiconductor device and their manufacturing methods, and portable electronic equipment, and IC card

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0141195B1 (en) * 1994-06-08 1998-07-15 김광호 Fabrication method of semiconductor device having low-resistance gate electrod
US5796151A (en) * 1996-12-19 1998-08-18 Texas Instruments Incorporated Semiconductor stack having a dielectric sidewall for prevention of oxidation of tungsten in tungsten capped poly-silicon gate electrodes
US5858840A (en) * 1997-12-22 1999-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming sharp beak of poly by nitrogen implant to improve erase speed for split-gate flash
US6117733A (en) * 1998-05-27 2000-09-12 Taiwan Semiconductor Manufacturing Company Poly tip formation and self-align source process for split-gate flash cell
KR100299386B1 (en) * 1998-12-28 2001-11-02 박종섭 Gate electrode formation method of semiconductor device
US6329685B1 (en) * 1999-09-22 2001-12-11 Silicon Storage Technology, Inc. Self aligned method of forming a semiconductor memory array of floating gate memory cells and a memory array made thereby
KR100311049B1 (en) * 1999-12-13 2001-10-12 윤종용 Nonvolatile semiconductor memory device and manufacturing method thereof
US6528844B1 (en) * 2001-10-31 2003-03-04 National Semiconductor Corporation Split-gate flash memory cell with a tip in the middle of the floating gate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6136653A (en) * 1998-05-11 2000-10-24 Mosel Vitelic, Inc. Method and device for producing undercut gate for flash memory
US6469341B1 (en) * 1998-05-11 2002-10-22 Mosel Vitelic, Inc. Method and device for producing undercut gate for flash memory
US6656796B2 (en) * 2002-01-14 2003-12-02 Taiwan Semiconductor Manufacturing Co., Ltd Multiple etch method for fabricating split gate field effect transistor (FET) device
US20040245564A1 (en) * 2003-05-19 2004-12-09 Takayuki Ogura Semiconductor storage device, semiconductor device and their manufacturing methods, and portable electronic equipment, and IC card

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