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Publication numberUS20040039997 A1
Publication typeApplication
Application numberUS 10/225,284
Publication date26 Feb 2004
Filing date22 Aug 2002
Priority date22 Aug 2002
Also published asUS6708312
Publication number10225284, 225284, US 2004/0039997 A1, US 2004/039997 A1, US 20040039997 A1, US 20040039997A1, US 2004039997 A1, US 2004039997A1, US-A1-20040039997, US-A1-2004039997, US2004/0039997A1, US2004/039997A1, US20040039997 A1, US20040039997A1, US2004039997 A1, US2004039997A1
InventorsMing-Mao Chiang, Ching-Chang Shih, Chin-Cho Tsai, Tien-Yueh Liu, Kuo-Chung Huang
Original AssigneeMing-Mao Chiang, Ching-Chang Shih, Chin-Cho Tsai, Tien-Yueh Liu, Kuo-Chung Huang
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method for multi-threshold voltage cmos process optimization
US 20040039997 A1
Abstract
A method for multi-threshold voltage CMOS process optimization. The method includes the steps of: providing a semiconductor substrate with a plurality of devices of different threshold voltages; establishing a plurality of types of timing models for a timing calculation; obtaining a static timing analysis report through the timing calculation; defining a large and a small setup time margin as a Tl and a Ts; changing the devices whose setup time margins are less than Ts to low threshold devices; changing the devices whose setup time margins are greater than Tl to high threshold devices; checking a setup time of each device; changing the devices whose setup time margin does not meet the enhanced static timing analysis report; performing a first pocket implant process for the normal threshold devices; performing a second pocket implant process for the low threshold devices and performing a third pocket implant process for the high threshold devices.
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Claims(20)
What is claimed is:
1. A method for multi-threshold voltage CMOS process optimization for a semiconductor substrate with a plurality of devices of different threshold voltages, comprising the steps of:
establishing a plurality of types of timing models for a timing calculation, based on the plurality of devices of different threshold voltages;
obtaining a static timing analysis (STA) report through the timing calculation;
defining a large and a small setup time margin as a Tl and a Ts, respectively, based on the static timing analysis report;
changing the devices whose setup time margins are less than Ts to low threshold devices and changing the devices whose setup time margin are greater than Tl to high threshold devices, such that an enhanced static timing analysis report is obtained;
performing a first pocket implant process for the low threshold devices with a first dose density by covering the high threshold devices; and
performing a second pocket implant process for the high threshold devices with a second dose density, greater than the first dose density, by covering the low threshold devices.
2. The method as recited in claim 1, wherein after the step of obtaining the enhanced static timing analysis report, the following steps are performed:
checking a setup time of each device, based on the enhanced static timing analysis report; and
changing the devices whose setup time margin does not meet the enhanced static timing analysis report to the normal devices.
3. The method as recited in claim 1, wherein the Tl is between 1 and 2 nano second.
4. The method as recited in claim 1, wherein the Ts is between 0 and 1 nano second.
5. A method for multi-threshold voltage CMOS process optimization, comprising the steps of:
establishing a plurality of types of timing models for a timing calculation, based on a plurality of devices of different threshold voltages;
obtaining a static timing analysis (STA) report through the timing calculation;
defining a large and a small setup time margin as a Tl and a Ts, respectively, based on the static timing analysis report; and
changing the devices whose setup time margin are less than Ts to low threshold devices and changing the devices whose setup time margins are greater than Tl to high threshold devices, such that a enhanced static timing analysis report is obtained.
6. The method as recited in claim 5, wherein after the step of obtaining the enhanced static timing analysis report, the following steps are performed:
checking a setup time of each device, based on the enhanced static timing analysis report; and
changing the devices whose setup time margin does not meet the enhanced static timing analysis report to the normal devices.
7. The method as recited in claim 5, wherein the Tl is between 1 and 2 nano second.
8. The method as recited in claim 5, wherein the Ts is between 0 and 1 nano second.
9. A method for multi-threshold voltage CMOS process optimization for a semiconductor substrate with a plurality of devices of different threshold voltages, comprising the steps of:
establishing a plurality of types of timing models for a timing calculation, based on the plurality of devices of different threshold voltages;
obtaining a static timing analysis (STA) report through the timing calculation;
defining a large and a small setup time margin as a Tl and a Ts, respectively, based on the static timing analysis report;
changing the devices whose setup time margins are less than Ts to low threshold devices and changing the devices whose setup time margins are greater than Tl to high threshold devices such that a enhanced static timing analysis report is obtained;
checking a setup time of each device, based on the enhanced static timing analysis report;
changing the devices whose setup time margin does not meet the enhanced static timing analysis report to the normal devices;
performing a first pocket implant process for the low threshold devices with a first dose density by covering the high threshold devices; and
performing a second pocket implant process for the high threshold devices with a second dose density, greater than the first dose density, by covering the low threshold devices.
10. The method as recited in claim 9, wherein the Tl is between 1 and 2 nano second.
11. The method as recited in claim 9, wherein the Ts is between 0 and 1 nano second.
12. A method for multi-threshold voltage CMOS process optimization for a semiconductor substrate with a plurality of devices of different threshold voltages, comprising the steps of:
establishing a plurality of types of timing models for a timing, calculation, based on the plurality of devices of different threshold voltages;
obtaining a static timing analysis (STA) report through the timing calculation;
defining a large and a small setup time margin as a Tl and a Ts, respectively, based on the static timing analysis report;
changing the devices whose setup time margins are less than Ts to low threshold devices and changing the devices whose setup time margins are greater than Tl to high threshold devices while the remaining devices are normal threshold devices, such that a enhanced static timing analysis report is obtained;
performing a first pocket implant process for the normal threshold devices with a first dose density by covering the low threshold devices and high threshold devices;
performing a second pocket implant process for the low threshold devices with a second dose density, less than the first dose density, by covering the normal threshold devices and high threshold devices; and
performing a third pocket implant process for the high threshold devices with a third dose density, greater than the first dose density, by covering the normal threshold devices and low threshold devices.
13. The method as recited in claim 12, wherein after the step of obtaining the enhanced static timing analysis report, the following steps are performed:
checking a setup time of each device, based on the enhanced static timing analysis report; and
changing the devices whose setup time margin does not meet the enhanced static timing analysis report to the normal devices.
14. The method as recited in claim 12, wherein the Tl is between 1 and 2 nano second.
15. The method as recited in claim 12, wherein the Ts is between 0 and 1 nano second.
16. A method for multi-threshold voltage CMOS process optimization, comprising the steps of:
establishing a plurality of types of timing models for a timing calculation, based on a plurality of devices of different threshold voltages;
obtaining a static timing analysis (STA) report through the timing calculation;
defining a large and a small setup time margin as a Tl and a Ts, respectively, based on the static timing analysis report; and
changing the devices whose setup time margins are less than Ts to low threshold devices and changing the devices whose setup time margins are greater than Tl to high threshold devices while the remaining devices are normal threshold devices, such that a enhanced static timing analysis report is obtained.
17. The method as recited in claim 16, wherein after the step of obtaining the enhanced static timing analysis report, the following steps are performed:
checking a setup time of each device, based on the enhanced static timing analysis report; and
changing the devices whose setup time margin does not meet the enhanced static timing analysis report to the normal devices.
18. The method as recited in claim 16, wherein the Tl is between 1 and 2 nano second.
19. The method as recited in claim 16, wherein the Ts is between 0 and 1 nano second.
20. A method for multi-threshold voltage CMOS process optimization for a semiconductor substrate with a plurality of devices of different threshold voltages, comprising the steps of:
establishing a plurality of types of timing models for a timing calculation, based on the plurality of devices of different threshold voltages;
obtaining a static timing analysis (STA) report through the timing calculation;
defining a large and a small setup time margin as a Tl and a Ts, respectively, based on the static timing analysis report;
changing the devices whose setup time margins are less than Ts to low threshold devices and changing the devices whose setup time margins are greater than Tl to high threshold devices while the remaining devices are normal threshold devices, such that a enhanced static timing analysis report is obtained;
checking a setup time of each device, based on the enhanced static timing analysis report;
changing the devices whose setup time margin does not meet the enhanced static timing analysis report to the normal devices;
performing a first pocket implant process for the normal threshold devices with a first dose density by covering the low threshold devices and high threshold devices;
performing a second pocket implant process for the low threshold devices with a second dose density, less than the first dose density, by covering the normal threshold devices and high threshold devices; and
performing a third pocket implant process for the high threshold devices with a third dose density, greater than the first dose density, by covering the normal threshold devices and low threshold devices.
Description
    BACKGROUND OF THE INVENTION
  • [0001]
    1. Field of the Invention
  • [0002]
    The present invention relates to the CMOS process, and more particularly to the design algorithm of the CMOS process.
  • [0003]
    2. Description of the Prior Art
  • [0004]
    The CMOS (Complementary Metal Oxide Semiconductor) circuit design has the advantage of low power compared with the BJT (Bipolar Junction Transistor), but has suffered from performance limitations. Because high speed digital design is requisite and designs with a gate count of more than ten millions are on the horizon, the process down sizing to 0.18 um/0.13 um or smaller scale is the trend for performance. However, the static and dynamic current consumption will increase rapidly due to faster devices. From the point of view of reducing power, the operation voltage is made as low as possible and the device threshold voltage is as large as possible. This, however, reduces the IC performance. Reducing the threshold voltage or increasing the saturation current will improve the delay time of the device. In other words, the device will transition from one stage to the other stage more quickly. However, this method will increase the switching current and reduce the noise margin, meaning that the power consumption will become larger.
  • [0005]
    In FIG. 1, a basic MOS structure is formed on a semiconductor substrate 10. The MOS structure includes a gate 12, a gate oxide 14, spacers 19, offset spacers 18, pocket regions 20, HDD regions 22 and source/drain regions 24.
  • [0006]
    A conventional pocket implant process is shown in FIG. 2. In FIG. 2, two MOS devices are formed on a semiconductor substrate 50 and isolated by a shallow trench isolation 52. Each device includes a gate 56, a gate oxide 58 and a well region 54. The conventional pocket implant process with a normal dose density is performed to a predefined region of each device by covering other regions with a photoresistor 60.
  • [0007]
    Obtaining both reduction of power consumption and good performance will inevitably increase the price of the product. Thus, an algorithm that both obtains power and performance enhancement and prevents to too many changes to the process recipes in CMOS design needs to be developed.
  • SUMMARY OF THE INVENTION
  • [0008]
    The object of the present invention is to solve the above-mentioned problems and to provide a method for multi-threshold voltage CMOS process optimization.
  • [0009]
    The present invention achieves the above-indicated object by providing a method for multi-threshold voltage CMOS process optimization comprising the steps of: providing a semiconductor substrate with a plurality of devices of different threshold voltages; establishing a plurality of types of timing models for a timing calculation, based on the plurality of devices of different threshold voltages; obtaining a static timing analysis (STA) report through the timing calculation; defining a large and a small setup time margin as a Tl and a Ts, based on the static timing analysis report; changing the devices whose setup time margin are less than Ts to low threshold devices and changing the devices whose setup time margin are greater than Tl to high threshold devices, such that an enhanced static timing analysis report is obtained; performing a first pocket implant process for the low threshold devices with a first dose density by covering the high threshold devices; performing a second pocket implant process for the high threshold devices with a second dose density, greater than the first dose density, by covering the low threshold devices.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0010]
    The present invention will be described in detail with reference to the illustrated embodiment and the accompanying drawings, in which:
  • [0011]
    [0011]FIG. 1 is a basic MOS structure.
  • [0012]
    [0012]FIG. 2 is a conventional pocket implant process.
  • [0013]
    [0013]FIG. 3 is a timing chart showing the setup time and the hold time under different clock domain.
  • [0014]
    [0014]FIG. 4 is a setup timing region of the devices.
  • [0015]
    [0015]FIGS. 5 and 6 illustrate, in cross-section and in top view respectively, a CMOS structure.
  • [0016]
    [0016]FIG. 7 is a flow chart showing the sequence of steps of multi-threshold voltage CMOS process optimization.
  • [0017]
    [0017]FIGS. 8 through 10 illustrate, in cross-section, the process in accordance with the present invention.
  • DETAILED DESCRIPTION OF THE INVENTION
  • [0018]
    The present invention discloses how to use small process changes to achieve the greatest improvement of speed.
  • [0019]
    In most designs, the performance of the system is dominated by a few critical paths in the integrated circuit. It isn't necessary to enhance the speed of all of the devices in order to obtain a high performance system. In this regard, a method by changing the threshold voltage according to Static Timing Analysis (STA) report is disclosed.
  • [0020]
    In the STA report, the setup time and the hold time under different clock domains, as shown in FIG. 3, need to be checked and the setup/hold time specification will be determined by the standard device timing. The timing calculation for the overall design based on the RC extraction result should be performed for the worst case and best case so the result is safe for the setup/hold time.
  • [0021]
    After finishing the static timing check, the worst case timing for the design can be guaranteed, and the setup timing can be arranged in order, as shown in FIG. 4. Then, Tl is defined as the timing paths that have large setup timing margin, Ts as the timing paths that have small setup timing margin, Tm as the timing path that has maximum setup timing margin and Tc as the timing path that has a setup timing margin criterion. If the devices in the timing paths are greater than Tl, they will be changed by higher threshold voltage devices. If the devices in the timing paths are smaller than Ts, they will be changed by lower threshold voltage devices. The result will centralize the timing window in the setup time safe region 70, and have the advantage of lower power consumption by replacing the device with timing paths greater than Tl and the advantage of the speed by replacing the device with timing paths smaller than Ts.
  • [0022]
    For increasing device speed, the general method is to change the saturation current. Using the saturation current equation described below, a scheme for increasing the current without adding RC loading can be obtained.
  • [0023]
    [0023]FIGS. 5 and 6 illustrate, in cross-section and in top view respectively, a CMOS structure. The CMOS structure is formed on a semiconductor substrate 100 and isolated by a shallow trench isolation 110. The CMOS structure includes a NMOS 114 and a PMOS 116. The NMOS includes a P-well 102, a gate 108 and source/drain regions 106. The PMOS includes a N-well 104, a gate 108 and source/drain regions 106. Numeral 112 represents a channel length and numeral 113 represents a channel width. The following is a saturation current of the CMOS.
  • Idsat˜μnCi(W/L)(VG−VT)2
  • [0024]
    μn: Carrier mobility
  • [0025]
    Ci: Gate Capacitance
  • [0026]
    W: Channel width
  • [0027]
    L: Channel length
  • [0028]
    VG: Gate voltage
  • [0029]
    VT: Threshold voltage
  • [0030]
    and
  • VT˜(2εqNd/Ci 2)1/2VB 1/2
  • [0031]
    ε: Substrate dielectric constant.
  • [0032]
    Nd: Dopant cocentration in well.
  • [0033]
    Ci: Gate capacitance.
  • [0034]
    VB: Substrate bias effect (body effect).
  • [0035]
    From above equation, to increase Idsat without modifying physical dimension, changing VT is a good choice. There are three major methods to change VT.
  • [0036]
    1. Changing P-well (in NMOS) diffusion density.
  • [0037]
    2.Changing HDD (High Density Dopant) diffusion density (Idsat is sensitive to HDD).
  • [0038]
    3.Changing pocket diffusion density. In deep sub-micro process, VT is also sensitive to pocket.
  • [0039]
    [0039]FIG. 7 is a flow chart showing the sequence of steps of multi-threshold voltage CMOS process optimization. In step S100, a semiconductor substrate with a plurality of devices of different threshold voltages is provided.
  • [0040]
    In step S102, based on multiple different threshold voltages, three types of timing model, such as “High”, “Normal”, “Low” for the timing calculation, are established.
  • [0041]
    In step S104, a STA result (setup/hold time) is reported, and then the devices that violate the timing constrains are changed or rerouted to solve the setup/hold time violation.
  • [0042]
    In step S106, the large/small setup time margin Tl and Ts are defined, based on the static timing analysis report.
  • [0043]
    In step S108, the devices whose setup time margins are less than Ts are changed to low threshold devices (high current).
  • [0044]
    In step S110, the devices whose setup time margins are greater than Tl are changed to high threshold devices (low current) while the remaining devices are normal threshold devices, such that a enhanced static timing analysis report is obtained.
  • [0045]
    In step S112, based on the enhanced STA report, setup/hold time is checked. The enhanced STA report is a description file based on the setup/hold time improvement obtained by changing the low threshold devices. Because the substitution of large setup time margin devices for the high threshold devices addresses power consumption concern, the report of the large setup time margin devices need not be changed.
  • [0046]
    In step S114, if the setup/hold time meets the enhanced STA report, the process is go to step S116; otherwise, the devices that violate the timing constrains are changed to normal devices, then go to step S112.
  • [0047]
    In step S116, a first pocket implant process 216 for the normal threshold devices 202 with a first dose density is performed by covering the low threshold devices 204 and high threshold devices 206 with a photoresistor 214, as shown in FIG. 8. Numeral 200 represents the substrate isolated by shallow trench isolations 210. Numeral 212 represents gates and numeral 208 represents well regions.
  • [0048]
    In step S118, a second pocket implant 220 process for the low threshold devices 204 with a second dose density, less than the first dose density, is performed by covering the normal threshold devices 202 and high threshold devices 206 with a photoresistor 218.
  • [0049]
    In step S120, a third pocket implant process 224 for the high threshold devices 206 with a third dose density, greater than the first dose density is performed, by covering the normal threshold devices 202 and low threshold devices 204.
  • [0050]
    While the present invention has been described with reference to three pocket implant processes, the description is not intended to be construed in a limiting sense. Two pocket implant processes of the various threshold devices, as well as other embodiments of the invention, will be apparent to those persons skilled in the art upon reference to this description.
  • [0051]
    The following is an experiment illustrating the multi-threshold optimization. Table 1 is the initial setup time data after STA in a normal procedure and the optimization result based on the multi-threshold optimization. It is obvious that the speed improvement of the flow is about 0.56˜0.78 ns based on Ts=1.0 ns and 5 iterations. Table 2 is the high threshold algorithm results under a setting of Tl=3.5 ns, where there are a total of 20,917 devices changed to high threshold devices, so that, about 25% devices' power consumption of the chip is reduced. In a word, the setup time safe region is fall on the 0.57 ns to 3.5 ns based on the original criterion, and the present invention not only improves the speed of the system but also the power consumption of the chip.
    TABLE 1
    After Before
    Change Change
    Device Device
    Start Capture Timing Timing
    Clock Clock Threshold Slack Slack Improve
    CLK1 CLK1 Low 0.78 ns  0.0 ns 0.78 ns
    CLK2 CLK2 Low 0.79 ns 0.05 ns 0.74 ns
    CLK3 CLK3 Low 0.66 ns  0.1 ns 0.56 ns
    CLK4 CLK4 Low 0.57 ns  0.0 ns 0.57 ns
  • [0052]
    [0052]
    TABLE 2
    After Before
    Optimi- Optimi- Change
    zation zation Change Device
    Clock Thres- Normal Normal Normal Percent-
    Domain hold device (No.) device (No.) (No.) age
    CLK1 High 20737 29825 9088 30.5%
    devices devices
    CLK2 High 25412 32678 7266 22.2%
    devices devices
    CLK3 High 8927 12003 3076 25.6%
    devices devices
    CLK4 High 5233 6720 1487 22.1%
    devices devices
  • [0053]
    It is to be understood that the present invention is not limited to the embodiments described above, but encompasses any and all embodiments within the scope of the following claims.
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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6990645 *29 Apr 200324 Jan 2006International Business Machines CorporationMethod for static timing verification of integrated circuits having voltage islands
US882619522 Jun 20122 Sep 2014Taiwan Semiconductor Manufacturing Co., Ltd.Layout modification method and system
US882621211 Mar 20132 Sep 2014Taiwan Semiconductor Manufacturing Company, Ltd.Method of forming a layout including cells having different threshold voltages, a system of implementing and a layout formed
US91228391 Aug 20141 Sep 2015Taiwan Semiconductor Manufacturing Co., Ltd.Layout modification method and system
US940086624 Aug 201526 Jul 2016Taiwan Semiconductor Manufacturing Co., Ltd.Layout modification method and system
US20040221252 *29 Apr 20034 Nov 2004International Business Machines CorporationMethod for static timing verification of integrated circuits having voltage islands
US20060240579 *19 Sep 200526 Oct 2006Powerchip Seminconductor Corp.Method for reducing threshold voltage variations due to gate length differences
Classifications
U.S. Classification716/134, 257/E21.644, 257/E21.525
International ClassificationG06F17/50, H01L21/66, H01L21/8238
Cooperative ClassificationH01L22/20, H01L21/823892, G06F17/5045
European ClassificationH01L22/20, G06F17/50D, H01L21/8238W
Legal Events
DateCodeEventDescription
22 Aug 2002ASAssignment
Owner name: SILICON INTEGRATED SYSTEMS CORP., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHIANG, MING-MAO;SHIH, CHING-CHANG;TSAI, CHIN-CHO;AND OTHERS;REEL/FRAME:013215/0478;SIGNING DATES FROM 20020725 TO 20020730
11 May 2007FPAYFee payment
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