US20040017674A1 - Low current blow trim fuse - Google Patents

Low current blow trim fuse Download PDF

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Publication number
US20040017674A1
US20040017674A1 US10/602,782 US60278203A US2004017674A1 US 20040017674 A1 US20040017674 A1 US 20040017674A1 US 60278203 A US60278203 A US 60278203A US 2004017674 A1 US2004017674 A1 US 2004017674A1
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Prior art keywords
fuse
region
stepped
oxide
trim
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Abandoned
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US10/602,782
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Gregory Romas
Rex Pirkle
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Individual
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Individual
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49107—Fuse making
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Definitions

  • This invention relates generally to a low current blow trim fuse associated with any integrated circuit that relies on fuses for trimming, and more particularly, to a structure of a trim fuse capable of being blown out easily and reliably at a low current and its associated method of manufacture.
  • trim fuse The minimum amount of current necessary to blow a trim fuse is limited by the cross-sectional area of the metal (or polycrystal silicon (poly)). In some processes, the minimum metal (or poly) width is limited by lithography and process variations that can be quite large. The current required to program the trim fuse(s) can therefore also be very large (i.e. greater than one Ampere for metal fuses).
  • the present invention is directed to a low current blow trim fuse structure and method of forming the trim fuse structure.
  • Oxide steps are placed beneath the trim fuse during prior process steps.
  • the oxide steps will cause the metal (or poly) to thin at the point where the metal (or poly) transitions the step, and thus will reduce its cross-sectional area and current carrying capability, making it easier to program the fuse.
  • the oxide steps will serve a further purpose in that, to some extent, it will thermally isolate the trim fuse, thereby causing local heating, making the fuse easier to blow.
  • a low current blow trim fuse having a reduced cross-sectional area in two dimensions to reduce its current carrying capacity, without adding process steps.
  • a low current blow trim fuse is provided to minimize its reliance on lithography and process variations.
  • a low current blow trim fuse having thermal isolation characteristics that enhance localized heating of the fuse.
  • FIG. 1 is a diagram illustrating a low current blow trim fuse according to one embodiment of the present invention.
  • FIG. 1 While the above-identified drawing FIGURE sets forth a particular embodiment, other embodiments of the present invention are also contemplated, as noted in the discussion. In all cases, this disclosure presents illustrated embodiments of the present invention by way of representation and not limitation. Numerous other modifications and embodiments can be devised by those skilled in the art which fall within the scope and spirit of the principles of this invention.
  • any integrated circuit that relies on fuses for trimming such as precision references, voltage regulators, op-amps and the like, is subjected to electrical stresses during trimming processes, that adversely impacts device reliability. These trimming processes associated with such devices generate currents necessary to program the trimming fuses.
  • the present invention is directed to a technique that will reduce the amount of current needed to program trimming fuses and therefore reduce the electrical stress that a device will undergo during trimming operations and also reduce the stresses on probe cards and associated test circuitry, thus extending their useful life without adding processing steps.
  • the minimum amount of current necessary to blow a trim fuse is limited by the cross-sectional area of the metal (or poly), as stated herein before.
  • the minimum metal (or poly) width is limited by lithography and process variations that can be quite large.
  • the current required to program the trim fuse(s) can therefore also be very large (i.e. greater than one Ampere for metal fuses).
  • FIG. 1 a sectional view diagram illustrates a low current blow trim fuse 10 according to one embodiment of the present invention.
  • the trim fuse 10 is created by first forming thinned diffusion oxide regions 12 on a silicon substrate 14 .
  • One or more field oxide steps are then implemented to build a stepped field oxide region 16 .
  • a metal (or poly) fuse material 18 is deposited over both the thinned diffusion oxide regions 12 and the stepped field oxide region 16 .
  • the stepped field oxide region 16 causes the fuse material 18 to thin in the regions 22 , 24 where the fuse material 18 transitions the stepped field oxide region 16 , which reduces both the cross section and current carrying capacity of the fuse 10 .
  • the cross section at transition region 22 and transition region 24 is reduced in at least two directions, affecting both the horizontal and vertical dimensions.
  • thinned diffusion oxide regions 12 having a thickness of approximately 7,000 ⁇ , a stepped field oxide region 16 having a thickness of approximately 12,000 ⁇ , and a fuse material 18 consisting of Al/Cu having a thickness of approximately 14,000 ⁇ away from the transitions areas 22 , 24 and above the thinned diffusion oxide regions 12 provided a suitable trim fuse.
  • the present invention presents a significant advancement in the art of trim fuses. Further, this invention has been described in considerable detail in order to provide those skilled in the trim fuse art with the information needed to apply the novel principles and to construct and use such specialized components as are required. In view of the foregoing descriptions, it should be apparent that the present invention represents a significant departure from the prior art in construction and operation. However, while particular embodiments of the present invention have been described herein in detail, it is to be understood that various alterations, modifications and substitutions can be made therein without departing in any way from the spirit and scope of the present invention, as defined in the claims which follow.

Abstract

A low current blow trim fuse structure and method of forming the trim fuse structure. Oxide steps are placed beneath a trim fuse during prior processing steps. The oxide steps will cause the metal (or polycrystal silicon (poly)) to thin at the point where the metal (or poly) transitions the step, and thus will reduce its cross-sectional area and current carrying capability, making it easier to program the fuse. The oxide steps will serve a further purpose in that, to some extent, it will thermally isolate the trim fuse, thereby causing local heating, making the fuse easier to blow.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • This invention relates generally to a low current blow trim fuse associated with any integrated circuit that relies on fuses for trimming, and more particularly, to a structure of a trim fuse capable of being blown out easily and reliably at a low current and its associated method of manufacture. [0002]
  • 2. Description of the Prior Art [0003]
  • Any integrated circuit that relies on fuses for trimming, such as precision references, voltage regulators, op-amps and the like, is subjected to electrical stresses during trimming processes, that adversely impacts device reliability. These trimming processes associated with such devices generate currents necessary to program the trimming fuses. In view of the foregoing, a need exists for a technique that will reduce the amount of current needed to program trimming fuses to reduce the electrical stress that a device will undergo during trimming operations and to also reduce the stresses on probe cards and associated test circuitry, thus extending their useful life. [0004]
  • The minimum amount of current necessary to blow a trim fuse is limited by the cross-sectional area of the metal (or polycrystal silicon (poly)). In some processes, the minimum metal (or poly) width is limited by lithography and process variations that can be quite large. The current required to program the trim fuse(s) can therefore also be very large (i.e. greater than one Ampere for metal fuses). [0005]
  • Known solutions to reducing the foregoing electrical stresses associated with trim fuses have concentrated on thinning the width of the metal (or poly) fuse, or putting corners in the fuse. One such solution is disclosed in U.S. Pat. No. 4,984,054, entitled [0006] Electric Fuse For A Redundancy Circuit, issued Jan. 8, 1991 to Yamada et al. These known solutions only address the electrical stress problem to the extent of the minimum reliable metal (or poly) width that can be drawn in a given process. Since the cross-sectional area is most important in determining the amount of current required to program a trim fuse, it is desirable to provide a technique that will enable a designer to minimize the trim fuse cross section in two dimensions, rather than only one, without adding process steps.
    • SUMMARY OF THE INVENTION
  • The present invention is directed to a low current blow trim fuse structure and method of forming the trim fuse structure. Oxide steps are placed beneath the trim fuse during prior process steps. The oxide steps will cause the metal (or poly) to thin at the point where the metal (or poly) transitions the step, and thus will reduce its cross-sectional area and current carrying capability, making it easier to program the fuse. The oxide steps will serve a further purpose in that, to some extent, it will thermally isolate the trim fuse, thereby causing local heating, making the fuse easier to blow. [0007]
  • In one aspect of the invention, a low current blow trim fuse is provided having a reduced cross-sectional area in two dimensions to reduce its current carrying capacity, without adding process steps. [0008]
  • In another aspect of the invention, a low current blow trim fuse is provided to minimize its reliance on lithography and process variations. [0009]
  • In still another aspect of the invention, a low current blow trim fuse is provided having thermal isolation characteristics that enhance localized heating of the fuse. [0010]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Other aspects, features and advantages of the present invention will be readily appreciated as the invention becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawing FIGURE wherein: [0011]
  • FIG. 1 is a diagram illustrating a low current blow trim fuse according to one embodiment of the present invention.[0012]
  • While the above-identified drawing FIGURE sets forth a particular embodiment, other embodiments of the present invention are also contemplated, as noted in the discussion. In all cases, this disclosure presents illustrated embodiments of the present invention by way of representation and not limitation. Numerous other modifications and embodiments can be devised by those skilled in the art which fall within the scope and spirit of the principles of this invention. [0013]
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • As stated herein before, any integrated circuit that relies on fuses for trimming, such as precision references, voltage regulators, op-amps and the like, is subjected to electrical stresses during trimming processes, that adversely impacts device reliability. These trimming processes associated with such devices generate currents necessary to program the trimming fuses. The present invention is directed to a technique that will reduce the amount of current needed to program trimming fuses and therefore reduce the electrical stress that a device will undergo during trimming operations and also reduce the stresses on probe cards and associated test circuitry, thus extending their useful life without adding processing steps. [0014]
  • The minimum amount of current necessary to blow a trim fuse is limited by the cross-sectional area of the metal (or poly), as stated herein before. In some processes, the minimum metal (or poly) width is limited by lithography and process variations that can be quite large. The current required to program the trim fuse(s) can therefore also be very large (i.e. greater than one Ampere for metal fuses). [0015]
  • Known solutions to reducing the foregoing electrical stresses associated with trim fuses have concentrated on thinning the width of the metal (or poly) fuse, or putting corners in the fuse. These known solutions only address the electrical stress problem to the extent of the minimum reliable metal (or poly) width that can be drawn in a given process. Since the cross-sectional area is most important in determining the amount of current required to program a trim fuse, it is desirable to provide a technique that will enable a designer to minimize the trim fuse cross section in two dimensions, rather than only one, without adding process steps. [0016]
  • Looking now at FIG. 1, a sectional view diagram illustrates a low current [0017] blow trim fuse 10 according to one embodiment of the present invention. The trim fuse 10 is created by first forming thinned diffusion oxide regions 12 on a silicon substrate 14. One or more field oxide steps are then implemented to build a stepped field oxide region 16. Finally, a metal (or poly) fuse material 18 is deposited over both the thinned diffusion oxide regions 12 and the stepped field oxide region 16. It can be seen that the stepped field oxide region 16 causes the fuse material 18 to thin in the regions 22, 24 where the fuse material 18 transitions the stepped field oxide region 16, which reduces both the cross section and current carrying capacity of the fuse 10. It can also be seen that the cross section at transition region 22 and transition region 24 is reduced in at least two directions, affecting both the horizontal and vertical dimensions.
  • The present inventors found that thinned [0018] diffusion oxide regions 12 having a thickness of approximately 7,000 Å, a stepped field oxide region 16 having a thickness of approximately 12,000 Å, and a fuse material 18 consisting of Al/Cu having a thickness of approximately 14,000 Å away from the transitions areas 22, 24 and above the thinned diffusion oxide regions 12 provided a suitable trim fuse.
  • In view of the above, it can be seen the present invention presents a significant advancement in the art of trim fuses. Further, this invention has been described in considerable detail in order to provide those skilled in the trim fuse art with the information needed to apply the novel principles and to construct and use such specialized components as are required. In view of the foregoing descriptions, it should be apparent that the present invention represents a significant departure from the prior art in construction and operation. However, while particular embodiments of the present invention have been described herein in detail, it is to be understood that various alterations, modifications and substitutions can be made therein without departing in any way from the spirit and scope of the present invention, as defined in the claims which follow. [0019]

Claims (15)

What is claimed is:
1. A trim fuse comprising:
a semiconductor substrate;
a stepped oxide region formed on a surface of said substrate;
at least one thinned oxide region formed on said surface of said substrate and proximal said stepped oxide region; and
an electrically blowable fuse material formed on said stepped oxide region and said at least one thinned oxide region to form at least one transition region between said stepped oxide region and said at least one thinned oxide region, wherein said fuse material reduces in thickness as it transitions from said at least one thinned oxide region to said stepped oxide region.
2. The trim fuse according to claim 1 wherein said fuse material reduces in thickness in no less than two dimensions as it transitions from said at least one thinned oxide region to said stepped oxide region.
3. The trim fuse according to claim 2 wherein said semiconductor substrate comprises silicon.
4. The trim fuse according to claim 3 wherein said fuse material comprises metal.
5. The trim fuse according to claim 4 wherein said metal comprises Al/Cu.
6. The trim fuse according to claim 3 wherein said fuse material comprises polycrystal silicon.
7. The trim fuse according to claim 1 wherein said stepped oxide region comprises a stepped field oxide.
8. A method of forming a trim fuse comprising the steps of:
forming a stepped oxide region on a semiconductor substrate;
forming at least one thinned oxide region on said semiconductor substrate and proximal said stepped oxide region; and
depositing an electrically blowable fuse material on said stepped oxide region and said at least one thinned oxide region to form at least one transition region such that said fuse material changes in thickness as it transitions between said at least one thinned oxide region and said stepped oxide region.
9. The method according to claim 8 wherein said step of depositing an electrically blowable fuse material on said stepped oxide region and said at least one thinned oxide region comprises forming said at least one transition region such that said fuse material reduces in thickness as it transitions from said at least one thinned oxide region to said stepped oxide region.
10. A trim fuse comprising:
a semiconductor substrate;
a field oxide stepped region formed on a surface of said substrate;
a plurality of thinned oxide regions formed on said surface of said substrate and proximal said field oxide stepped region; and
a fuse material deposited on said field oxide stepped region and said plurality of thinned oxide regions to form a plurality of transition regions between said field oxide stepped region and said plurality of thinned oxide regions, wherein said fuse material reduces in thickness as it transitions from said plurality of thinned oxide regions to said field oxide stepped region.
11. The trim fuse according to claim 10 wherein said fuse material comprises metal.
12. The trim fuse according to claim 11 wherein said metal comprises Al/Cu.
13. The trim fuse according to claim 10 wherein said fuse material comprises polycrystal silicon.
14. The trim fuse according to claim 10 wherein said semiconductor substrate comprises silicon.
15. The trim fuse according to claim 10 wherein said fuse material reduces in thickness in at least two directions as it transitions from said plurality of thinned oxide regions to said field oxide stepped region.
US10/602,782 2001-08-06 2003-06-24 Low current blow trim fuse Abandoned US20040017674A1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060098683A1 (en) * 2004-11-10 2006-05-11 Thaler Patricia A System and method for auto-negotiation in a data communication device
CN102201373A (en) * 2011-04-25 2011-09-28 上海宏力半导体制造有限公司 Manufacture method of SOI (silicon on insulator)-based electronic fuse line
WO2018004633A1 (en) * 2016-06-30 2018-01-04 Intel Corporation Fuse array for integrated circuit

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6960978B2 (en) * 2003-07-16 2005-11-01 Hewlett-Packard Development Company, L.P. Fuse structure
US7215175B1 (en) 2004-09-01 2007-05-08 Sun Microsystems, Inc. Fuse sensing scheme with auto current reduction
US7888771B1 (en) 2007-05-02 2011-02-15 Xilinx, Inc. E-fuse with scalable filament link
US7724600B1 (en) 2008-03-05 2010-05-25 Xilinx, Inc. Electronic fuse programming current generator with on-chip reference
US7834659B1 (en) 2008-03-05 2010-11-16 Xilinx, Inc. Multi-step programming of E fuse cells
US7710813B1 (en) 2008-03-05 2010-05-04 Xilinx, Inc. Electronic fuse array
US8564023B2 (en) * 2008-03-06 2013-10-22 Xilinx, Inc. Integrated circuit with MOSFET fuse element
US7923811B1 (en) 2008-03-06 2011-04-12 Xilinx, Inc. Electronic fuse cell with enhanced thermal gradient
JP2017045839A (en) * 2015-08-26 2017-03-02 ルネサスエレクトロニクス株式会社 Semiconductor device

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4757359A (en) * 1986-04-07 1988-07-12 American Microsystems, Inc. Thin oxide fuse
US4888630A (en) * 1988-03-21 1989-12-19 Texas Instruments Incorporated Floating-gate transistor with a non-linear intergate dielectric
US4984054A (en) * 1986-12-01 1991-01-08 Mitsubishi Denki Kabushiki Kaisha Electric fuse for a redundancy circuit
US5364810A (en) * 1992-07-28 1994-11-15 Motorola, Inc. Methods of forming a vertical field-effect transistor and a semiconductor memory cell
US5374832A (en) * 1992-09-29 1994-12-20 Texas Instruments Incorporated Antifuse having TiW oxide film between two metal layers
US5422289A (en) * 1992-04-27 1995-06-06 National Semiconductor Corporation Method of manufacturing a fully planarized MOSFET and resulting structure
US5682730A (en) * 1996-09-12 1997-11-04 Tenneco Packaging Plastic bag with bottom header
US5972756A (en) * 1995-11-30 1999-10-26 Mitsubishi Denki Kabushiki Kaisha Method of fabricating semiconductor device with a fuse portion
US6227637B1 (en) * 1998-05-14 2001-05-08 Lsi Logic Corporation Circuit and method for encoding and retrieving a bit of information
US6566730B1 (en) * 2000-11-27 2003-05-20 Lsi Logic Corporation Laser-breakable fuse link with alignment and break point promotion structures

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4757359A (en) * 1986-04-07 1988-07-12 American Microsystems, Inc. Thin oxide fuse
US4984054A (en) * 1986-12-01 1991-01-08 Mitsubishi Denki Kabushiki Kaisha Electric fuse for a redundancy circuit
US4888630A (en) * 1988-03-21 1989-12-19 Texas Instruments Incorporated Floating-gate transistor with a non-linear intergate dielectric
US5422289A (en) * 1992-04-27 1995-06-06 National Semiconductor Corporation Method of manufacturing a fully planarized MOSFET and resulting structure
US5364810A (en) * 1992-07-28 1994-11-15 Motorola, Inc. Methods of forming a vertical field-effect transistor and a semiconductor memory cell
US5416736A (en) * 1992-07-28 1995-05-16 Motorola, Inc. Vertical field-effect transistor and a semiconductor memory cell having the transistor
US5374832A (en) * 1992-09-29 1994-12-20 Texas Instruments Incorporated Antifuse having TiW oxide film between two metal layers
US5972756A (en) * 1995-11-30 1999-10-26 Mitsubishi Denki Kabushiki Kaisha Method of fabricating semiconductor device with a fuse portion
US5682730A (en) * 1996-09-12 1997-11-04 Tenneco Packaging Plastic bag with bottom header
US6227637B1 (en) * 1998-05-14 2001-05-08 Lsi Logic Corporation Circuit and method for encoding and retrieving a bit of information
US6566730B1 (en) * 2000-11-27 2003-05-20 Lsi Logic Corporation Laser-breakable fuse link with alignment and break point promotion structures

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060098683A1 (en) * 2004-11-10 2006-05-11 Thaler Patricia A System and method for auto-negotiation in a data communication device
CN102201373A (en) * 2011-04-25 2011-09-28 上海宏力半导体制造有限公司 Manufacture method of SOI (silicon on insulator)-based electronic fuse line
WO2018004633A1 (en) * 2016-06-30 2018-01-04 Intel Corporation Fuse array for integrated circuit
US10811354B2 (en) 2016-06-30 2020-10-20 Intel Corporation Fuse array for integrated circuit

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