US20030178639A1 - Inductive storage capacitor - Google Patents
Inductive storage capacitor Download PDFInfo
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- US20030178639A1 US20030178639A1 US10/413,795 US41379503A US2003178639A1 US 20030178639 A1 US20030178639 A1 US 20030178639A1 US 41379503 A US41379503 A US 41379503A US 2003178639 A1 US2003178639 A1 US 2003178639A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/565—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using capacitive charge storage elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
- H01L29/945—Trench capacitors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
Abstract
A device includes an element (e.g. in the shape of a sleeve) and a core located in an interior volume defined by the element and at least partially surrounded by the element. The element has two portions: one portion overlaps at least a region of the core thereby to form a capacitor, while another portion surrounds the core thereby to form an inductor. The device may further include an additional capacitor formed by another element that is separated from the core but overlaps at least a region of the core when viewed in a direction perpendicular to the core. The two elements substantially surround the core. The core may be used to hold charge in a non-volatile manner, even when no power is supplied to the device. The device can be manufactured in the normal manner, by forming a via hole, depositing a conductive layer in the via hole to form a sleeve-shaped element, forming a dielectric layer over the conductive layer so that the dielectric layer defines an interior volume, and filling the interior volume with a plug of conductive material that forms the core. An additional dielectric layer and an additional conductive layer may be formed to implement the additional capacitor.
Description
- A book entitled “Nonvolatile Semiconductor Memory Technology”, Edited by William D. Brown and Joe. E. Brewer and published by IEEE Press (1998), ISBN 0-7803-1173-6, states, on page 1 “The ultimate solution—a genuine nonvolatile RAM that retains data without external power, can be read from or programmed like a static or dynamic RAM, and still achieve high-speed, high-density, and low power consumptions at an acceptable cost—remains unfeasible to this day.” On page 6, this book describes a class of nonvolatile memory devices that store a charge on a conducting or semiconducting layer (called “floating gate”) that is completely surrounded by dielectric and an opposing layer (called “control gate”) that together form a capacitor (commonly known as “storage capacitor”).
- An article entitled “Applied Materials Introduces New Storage Capacitor Solution for Gigabit DRAMs” dated Jul. 8, 1998 describes use of tantalum pentoxide (Ta2O5) to form storage capacitors in memory devices. Such a storage capacitor cannot hold its charge over an extended period of time and loses a stored data bit unless its charge is refreshed periodically, as described at http://www.ee.cooper.edu/courses/course_pages/past_courses/EE151/MEMS_HO1/. As described therein, the periodic refreshing requires additional memory circuitry and complicates the operation of dynamic random access memory (DRAM) formed from such capacitors.
- The above-described periodic refreshing can be avoided by flash memory. There are several kinds of flash memory, including a single-transistor cell and a two-transistor cell as described in an article in Electronic Design, dated Aug. 9, 1999, and entitled “Feature-Rich Flash Memories Deliver High Density” by Dave Bursky. As described therein, a single-transistor cell is employed in a NOR-like logic structure to form a random-access storage array (called “flash EPROM”). Moreover, the two-transistor (or a merged transistor, dual-gate) cell is also a NOR-style configuration (called “flash EEPROM”). On-chip decoding circuits divide an array of two-transistor cells into small blocks (256 bytes to 4 kbytes) that normally enable a smaller portion of the chip to be erased and reprogrammed.
- Several issues exist with the flash memory as described in the above-identified book by Brown and Brewer, such as slow trapping, polarization, oxide breakdown/leakage, hot-electron injection, and oxide-hopping conduction, as described in Table 6.2 on
page 362 - In accordance with the invention, a semiconductor substrate has formed therein an inductor and a capacitor integrated into a single device (called an “inductive capacitor”). The inductor causes the capacitor to charge faster than the charging of a prior art device that has significant capacitance but negligible inductance (e.g. a device in which the capacitive contribution to the resonant frequency (of an LC circuit formed by such a prior art device) is greater than 90% of the inductive contribution). The device can include any structure that implements the inductive and capacitive functions in an integrated manner. Such a device having a significant inductive effect can be used in any radio-frequency (RF) circuit.
- In one embodiment, the device includes a rod-shaped second element (hereinafter simply “plug”) that is located in an interior space defined by a sleeve-shaped first element (hereinafter simply “sleeve”), thereby to form a capacitor (also called “first capacitor”) and an inductor in the same device. The core is separated from the sleeve by a dielectric material (also called “trap material”) that stores an electrical charge when the device is powered off (such as silicon-silicon dioxide interface). An inductive capacitor that includes a trap material between the two elements is also referred to as an “inductive storage capacitor.” Such an inductive storage capacitor is used to implement a nonvolatile memory cell in one application, and a timing circuit in another application.
- FIG. 1 illustrates in integrated circuit die containing an inductive capacitor in one embodiment of the invention.
- FIG. 2 illustrates flux lines induced in the inductive capacitor of FIG. 1 during operation.
- FIGS. 3 and 5 illustrate, in circuit diagrams, the inductive capacitor of FIG. 1 filled with a trap material, and coupled to a voltage source and a sensor, in two embodiments.
- FIG. 4 illustrates physical structure of one embodiment that integrates an inductive capacitor with a sense capacitor, by use of an additional element.
- FIG. 6 illustrates a symbol for the inductive capacitor.
- FIG. 7 illustrates electron flow on an outer surface of the inductive capacitor of FIG. 1.
- FIG. 8 illustrates an inductive capacitor that does not hold charge when powered down.
- FIG. 9 illustrates a cross section of the inductive storage capacitor.
- FIG. 10 illustrates the cross section of FIG. 9 with superimposed thereon symbols of the circuit elements formed by the structure.
- FIG. 11 illustrates, in an enlarged view, an interface formed between
layers - FIG. 12 illustrates the crystal structure of the silicon-silicon dioxide interface where free electrons are trapped in electrons holes.
- FIGS.13-20 illustrates, in a cross sectional view, formation of various layers in a via hole of a silicon wafer.
- FIG. 21 illustrates a plan view of the inductive storage capacitor structure illustrated in FIG. 20, along the direction A-A via hole on the silicon wafer.
- FIG. 22 illustrates a timing diagram for reading a discharged state and writing a charged state.
- FIG. 23 illustrates a timing diagram for reading a charged state and writing a one state.
- FIG. 24 illustrates a timing diagram for reading a discharged state and writing a discharged state.
- FIG. 25 illustrates a timing diagram for reading a charged state and writing a discharged state.
- FIGS. 26A, 26B, and27-29 illustrate, in cross-sectionional views, various embodiments of an inductive storage capacitor in an upside down configuration relative to FIG. 9.
- FIG. 30 illustrates a cross section of the inductive storage capacitor with another material deposited into the floating element.
- FIG. 31 illustrates, in a block diagram, use of an inductive storage capacitor as a storage element.
- FIG. 32 illustrates, in a circuit diagram, circuit elements that realize the embodiment of FIG. 31.
- FIG. 33 illustrates a memory cell array formed of inductive storage capacitors.
- A semiconductor substrate1 (FIG. 1) in one embodiment has formed therein a
device 2 including afirst element 3 of a conductive material that surrounds asecond element 4 that may be of the same or different conductive material. Depending on the aspect ratio, thesecond element 4 can be in the shape of a coin (that has a height significantly smaller than the diameter, e.g. an order of magnitude smaller), or a needle (that has a height significantly larger than the diameter, e.g. an order of magnitude larger), or a rod (which has an aspect ratio somewhere between a coin and a needle). - As would be apparent to the skilled artisan, a ring-shaped
first element 3 surrounding a coin-shapedsecond element 4 has a negligible capacitive effect and significant inductive effect (e.g. the capacitive contribution to the resonant frequency (of an LC circuit formed by such a device) is less than 10% of the inductive contribution). Such adevice 2 having a significant inductive effect can be used in any radio-frequency (RF) circuit. Anotherdevice 2 having significant inductive as well as capacitive effects can be used as a storage capacitor for nonvolatile memory, as described herein. Although a specific structure is illustrated in FIG. 1,device 2 can include any structure that implements the inductive and capacitive functions in an integrated manner. - In one embodiment, the
device 2 includes a rod-shaped second element 4 (hereinafter simply “plug”) that is located in an interior space defined by a sleeve-shaped first element 3 (hereinafter simply “sleeve”), thereby to form a capacitor (also called “first capacitor”) and an inductor in the same device. A trace (not shown in FIG. 1) is attached to an input terminal 24 (FIG. 2) located at one end ofsleeve 3, to provide current and voltage for operation of the device. As described below, the inductor causes the capacitor to charge faster than the charging of a prior art device that has significant capacitance but negligible inductance (e.g. the capacitive contribution to the resonant frequency (of an LC circuit formed by such a prior art device) is greater than 90% of the inductive contribution). -
Plug 4 is separated fromsleeve 3 by any dielectric material, including, for example a material 5 (also called “trap material”) that stores an electrical charge whendevice 2 is powered off (such as either silicon-silicon dioxide interface, or silicon-silicon nitride interface). An inductive capacitor that includes atrap material 5 betweensleeve 3 andplug 4 is also referred to as an “inductive storage capacitor.” -
Sleeve 3 can have any cross-section, such as circular, rectangular, triangular, etc. Moreover, the sleeve need not be continuous in the cross-sectional view (e.g. such a sleeve may have a cross-section in the shape of the letter “C” of the English alphabet). One end ofsleeve 3 is coupled to a voltage source, so that during operation electrons flow into the device from this end of the sleeve towards the other end, thereby to form an inductor (device in which an electromotive force is induced in it or in a nearby circuit by a change of current in either itself or the nearby circuit).Plug 4 can also have any cross-section, which may or may not be solid, depending on the embodiment. - During operation, an inductive field23 (FIG. 2) is generated between an
inner surface 21 of sleeve 3 (which acts as a coil) and asurface 22 of plug 4 (which acts as a core).Surfaces capacitor 29.Inductive field 23 is used to store a charge intrap material 27 that is located betweensurfaces capacitor 29 charges,inductive field 23 is formed, and causes electron wave movement (a well known phenomenon in physics, as described inChapter 4 entitled “Physical Aspects of Cell operation and reliability” in the book entitled “Flash Memories” by Paolo Cappelletti et al. Kluwer Academic Publishers, 1999, which chapter is incorporated by reference herein in its entirety) or tunneling to occur through trap material 27 (e.g. along the silicon-silicon dioxide interface). - As capacitor29 (also called “storage capacitor”) reaches the level of the voltage supply,
inductive field 23 collapses causing free electrons to be trapped in the silicon-silicon dioxide interface. Therefore, ‘trap to band tunneling’ (well known in the art) is performed by creation and collapse ofinductive field 23. The process is reversed whenstorage capacitor 29 is discharged, and theinductive field 23 is reversed causing the trapped electrons to be removed. Such aninductive storage capacitor 20 is of a different design than a storage capacitor in conventional non-volatile solid state memory devices known to applicant, and uses a new method for programming and reading the levels of the electrons that are stored in the device. - Inductive storage capacitor20 (FIG. 2) forms an electrical circuit 30 (FIG. 3) that in turn can be implemented in other structures apparent to the skilled artisan in view of the disclosure.
Circuit 30 includes acapacitor 33, aninductor 34 coupled in parallel tocapacitor 33, and atrap material 37 located insidecapacitor 33. In one embodiment,inductor 34 is in contact withtrap material 37. However,inductor 34 need not be in contact with, e.g. can be simply adjacent to trap material 37 (if there is another material located therebetween). - Regardless of the relative locations of
inductor 34 andtrap material 37, during operation ofcircuit 30,inductor 34 generates a field (e.g. similar or identical to field 23 discussed above in reference to FIG. 2) passing throughtrap material 37. In this embodiment, asensor 36 is coupled tocapacitor 33, to sense a charge stored in the traps oftrap material 37. In one implementation,capacitor 33,inductor 34,sensor 36 andvoltage source 31 are all coupled to acommon terminal 32 as illustrated in FIG. 3 although in other embodiments, other such couplings may be made. - In one embodiment, an inductive storage capacitor20 (FIG. 4) is located adjacent to an
element 45 to form a device 40 wherein asurface 46 ofelement 45 and asurface 44 ofplug 4 form a capacitor (called “sense capacitor”) 48.Sensing capacitor 48 is separate and distinct from (but coupled in series to) the above-discussed capacitor 29 (FIGS. 2 and 4) ininductive storage capacitor 20. Astrap material 27 becomes filled with electrons, asurface 44 ofplug 4 collects an opposite (i.e. negative) charge and the voltage level of adjacent element 45 (or sensing capacitor) is changed. The voltage level (on sensing capacitor 48) and current flow (through sensing capacitor 48) is used to detect the current state of the storage capacitor. - Device40 (FIG. 4) forms an electrical circuit 50 (FIG. 5) that can also be implemented in other structures apparent to the skilled artisan in view of the disclosure.
Circuit 50 is similar or identical tocircuit 30 described above except for the following differences.Circuit 50 includes an additional capacitor 55 (also called “sense capacitor”) in series with capacitor 33 (also called “storage capacitor” and described above in reference to FIG. 3). Note thatinductor 34 is coupled in parallel to storage capacitor 33 (and in series with sense capacitor 55).Circuit 50 also includes asensor 56 that is coupled to a terminal ofsensor capacitor 55. Although there is no sensor coupled tostorage capacitor 33 in this embodiment, avoltage source 31 is coupled to a terminal 32 (of capacitor 33) that in turn is coupled toinductor 34. Note thattrap material 37 is not presentinside sense capacitor 55, instead a dielectric material may be present. - When voltage source31 (FIG. 5) is coupled to terminal 32 the voltage potential causes current to charge
storage capacitor 33 and in parallel induce an inductive field in theinductor 34. Asvoltage source 31 is applied current flows fromstorage capacitor 33 tosense capacitor 55 causingsense capacitor 55 to charge. The delay in chargingsense capacitor 55 is measured by connectingsense capacitor 55 to asensor 56 to measure the voltage or current on the output ofsense capacitor 55. Such delay is different, depending at least on whether or not trapmaterial 37 holds a charge therein. Therefore, sensing the delay reads the data stored indevice 50. - The inductance, capacitance and density of state (the number of available electron states per unit volume and energy) of
circuit elements circuit 50. Depending on the application, values for such parameters may be different from the values described below in reference to FIGS. 13-20. Such parameters can be calculated as follows. The capacitance of each ofcapacitors - When the
inductor 34 is added in parallel to thestorage capacitor 33, an inductor and capacitor interaction occurs, resulting in a LC circuit having a resonant frequency. Several additional variables (other than those in the previous paragraph) must be used to calculate the charge time for thecapacitor 33 in the presence ofinductor 34. Theinductor 34 has an inductance (measured in henneries) that is calculated using a coil and core model. Such a model may be based on a phenomenon called the “skin effect” as described in “Fundamentals of Electronics” by E. Norman Lurch, John Wiley and Sons, Inc, Second Edition, 1971 at page 236 in Chapter 9 (which chapter is incorporated by reference herein in its entirety). For example, one may calculate inductance using various parameters, such as size of the coil (e.g. area ofsurface 22 in FIG. 4), the volume and density of the material in the core, and the dielectric constant of the trap material, as would be apparent to the skilled artisan. - Once the inductance of the
inductor 34 and the capacitance ofcapacitor 33 is calculated then the time constant of the LC circuit formed by the interaction between thestorage capacitor 33 and theinductor 34 is found (e.g. using a Laplace transform of the type well known in the art). Next, one may compute the difference between the charge time ofcapacitor 33 in the presence and absence of charges intrap material 37. This difference is used bysensor 56 to determine whether or not a charge was stored in trap material 37 (e.g. whether or not a bit 1 is stored incircuit 50 when used as a part of a memory cell). -
Storage capacitor 33,inductor 34 andsense capacitor 55 together are represented, in circuit diagrams of one embodiment, by a single symbol 60 (FIG. 6). Such asymbol 60 may be used, for example, in a programmed computer by circuit modeling software for interpreting instructions in hardware description languages, such as SPICE or VERILOG. Such software (which is normally stored in the memory of the computer) includes instructions to model a capacitor in the normal manner, except that the capacitor charges and discharges significantly faster than (e.g. twice as fast or 10 times as fast as) a conventional capacitor of the same rating. The higher speed effectively models the inductive effect of the inductive storage capacitor represented bysymbol 60. One embodiment of the inductive storage capacitor is operated at speeds above 1 GHz, which overcomes a prior art problem of speed and response time of conventional memory. - Therefore, in one embodiment, engineers that design microprocessors, digital signal processors, logic, or memory may use such a single symbol in a circuit diagram (which may be on paper or on a computer screen, depending on the circumstances) to identify a combination of circuit elements that form an inductive storage capacitor as described herein. Thereafter, when the circuit is realized in a semiconductor wafer, an inductive storage capacitor is fabricated as described elsewhere herein.
- In one embodiment,
symbol 60 has twoparallel line segments 62 and 63 (that represent a capacitor), and a spiral 61 (that represents an inductor) wrapped around the twoparallel line segments 62 and 63 (which may be shown, for example, as vertical lines). Note that in the embodiment illustrated in FIG. 6, a capacitor symbol well known in the art and an inductor symbol well known in the art are overlapped, and an optionalrectangular box 66 is added to represent storage, thereby to form thenew symbol 60. Optionally, the two symbols may be shown connected, at one end, to acommon line segment 69, which represents, for example, an input line to the device (for connection to a voltage source). Note that in the embodiment illustrated in FIG. 6, ahorizontal line 69 is shown connected to each of (1)line segment 62 and (2)spiral 61. -
Symbol 60 optionally has a thirdparallel line segment 64 that is shorter than the twoparallel line segments parallel line segment 64 is set apart fromspiral 61. Also,symbol 60 optionally has a box 66 (which represents trap material 37) located between the twoparallel line segments output line 65 may be connected to the thirdparallel line segment 64, when present. Although specific embodiments ofsymbol 60 are illustrated in FIG. 6, other such symbols will be apparent to the skilled artisan. - When voltage source31 (FIG. 7) is applied to an
input trace 25 connected to a terminal 24 located at one end ofsurface 21 ofconductive sleeve 3, a number of electron waves 26A-26M (wherein A≦J≦M, M being the total number of waves) originate atterminal 24 and travel aroundsurface 21, as shown by waves 28A-28M (which represent waves 26A-26M after a time delay), thereby to form a current flow. Although terminal 24 where electron waves originate is located at the end ofsurface 21 ofsleeve 3, in other embodiments, terminal 24 is separated by a distance from the end, as long as an inductive effect is present. As discussed elsewhere, the inductive effect must be sufficient to move free electrons intotrap material 37. The inductive effect arises from the flow of electrons along a path defined by physics, as they move acrosssurface 21. This movement is defined by Boltzmann's principle which states that electron groups or waves vectors (momentum) move at a velocity and across the conductive surface generating an electromagnetic force (emf) that in turn creates an inductive field 23 (illustrated by flux lines 23A-23N). - The carrier flux or field strength that is created by waves28A-28M is calculated using Newton's Law of Motion. The electrons gain momentum as they move across the
surface 21 they use a spherical parabolic path (as illustrated by waves 26A-26M and 28A-28M) following the laws of motion and follow the band structure of the material. As momentum is gained across the surface the field strength and direction are determined. The field strength and flux are a function of both the capacitor and inductor resonant frequency. As the inductive field 23 (FIG. 7) is built, thesurface 21 collects electrons, and plug 4 has an opposite charge forming thereon. The free electrons migrate away fromsurface 22, toward the center ofplug 4 and become resonant, e.g. atsurface 44. As this build up of charges occurs,surface 46 ofelement 45 is also charging. As the charges collect onelement 45, a voltage is created onelement 45, and this voltage causes a current to start flowing throughsensor 56. - In one embodiment, a dielectric material410 (FIG. 8) between
conductive sleeve 3 and plug 4 may be a single layer of dielectric material (like silicon nitride Si3N4). Such adevice 420 that has a single dielectric layer still contains a capacitor and inductor as described above, but does not have the ability to store a charge. This device operates at resonant frequency and is used in radio frequency (RF) circuits, e.g. for band pass or tuning filters used in communication device. This design has advantages in that the inductor/capacitor is manufactured in a smaller element on the silicon wafer and requires less surface area than conventional RF circuits. - FIG. 9 shows a cross section of an
inductive storage capacitor 100 of the type described above, implemented in a viahole 101 formed in a semiconductor material 102 (such as raw silicon or in an epitaxial layer).Inductive storage capacitor 100 includes afirst layer 191 of aluminum, which forms theconductive sleeve 3, and connected thereto is atrace 190.Inductive storage capacitor 100 also includes atrap material 5 formed at an interface between asecond layer 192 of a silicon (Si) dielectric material and athird layer 193 of silicon dioxide (SiO2). Therefore,trap material 5 of this implementation is a silicon-silicon dioxide (Si—SiO2) interface.Inductive storage capacitor 100 also includes afourth layer 194 of silicon nitride (Si3N4) that provides a dielectric of high value for the storage capacitor and inductor elements.Inductive storage capacitor 100 further includes a fifth material which is a conductive material like aluminum or copper and which forms aplug 195 that is located inside the viahole 101. - Depending on the implementation,
inductive storage capacitor 100 also includes adielectric material 196 located overplug 195, to form the dielectric element ofsense capacitor 48. Note thatdielectric material 196 can be formed of any semiconductor material commonly used for insulation such as silicon and silicon oxide, although in oneembodiment material 196 includes silicon nitride (Si3N4) which ensures that junctions formed therein have better thermal conductivity, and better adhesion than other semiconductor materials. Located overdielectric material 196 is a layer ofconductive material 197, like aluminum or other conductive material, which formssense capacitor 55. Thismaterial 197 is then connected to a sensor through alead 198. In one or more alternative implementations, materials 196-198 are not used and instead, trace 190 is connected to avoltage source 31 and also to asensor 36 as described above. - In one implementation illustrated in FIG. 9, a device (that includes inductive storage capacitor100) has, attached to
conductive sleeve 3, afloor 91 also formed offirst layer 191.Floor 91 overlaps at least a region ofplug 195 when viewed in a direction perpendicular to plug 195. The combination ofsleeve 3 andfloor 91 is also referred to as a “cup-shaped element”, and in one embodiment has an aspect ratio in the range of 1 to 5 although other aspect ratios may be used in other embodiments. -
Conductive layer 197 together withsleeve 3 andfloor 91 substantially encloseplug 195. So, any charge that may be stored in the region (also called “storage tunnel”) betweenplug 195 and such surrounding elements is less likely to be affected by alpha particles than in prior art devices, such as flash memory. At the same time, the storage tunnel holds a charge in a non-volatile manner, even when no power is supplied to the device as described elsewhere. - Instead of
floor 91, aroof 290 may be attached tocapacitor 100 as illustrated in FIGS. 26-28. Roof 290 (FIG. 28) is located at the top of the sleeve (and is also called a “cap”). Note that in another implementation, such a structure does not have a cap or a cup, i.e. has only the sleeve. Referring back to FIG. 9,floor 91 which may be an artifact of a manufacturing process, may be eliminated as discussed below in reference to FIG. 17, thereby to ensure that the resultant device effectively functions as aninductive storage capacitor 100. - Circuit elements of
inductive storage capacitor 100 are shown overlayed onto a cross-sectional view in FIG. 10. The interaction of the coupled devices creates the equivalent circuit to the circuit in FIG. 5. Theinput lead 190 is connected to layer 191 (FIG. 10) which forms afirst terminal 203 of astorage capacitor 33.Conductive sleeve 3 also forms a coil of theinductor 34. Plug 195 forms a core of theinductor 34. During operation,inductor 34 creates anelectrical field 204 around theplug 195. Plug 195 forms anelectrical path 209 from thesecond terminal 207 ofstorage capacitor 33 to aterminal 208 of thesense capacitor 55.Conductive material 197 forms asecond terminal 206 ofsense capacitor 55, which is connected bylead 198 to a sensor. - The storage of electrons in
inductive storage capacitor 100 occurs at an interface 214 (FIG. 11) in trap material 5 (FIG. 1), where theinductive field 204 works with thestorage capacitor 33 to cause the generation of electron hole pairs to occur in a phenomenon known as ‘Trap-to-Band Tunneling (TBT)’. As the input voltage is applied, the electron waves move aroundfirst layer 191, thereby to form aninductive field 204.Storage capacitor 33 causes electron to accumulate alonginterface 214 formed betweensecond layer 192 andthird layer 193. Anotherinterface 215 formed betweenthird layer 193 andfourth layer 194 also provides an electron-trapping interface, although not as strong asinterface 214.Fourth layer 194 provides a high dialectic material to hold the electrons atinterface 215, and to stop the flow of electrons intoplug 195. When the voltage level onfirst layer 191 reaches a maximum, theinductive field 204 collapses causing the electrons to be trapped intrap material 5. - In one embodiment,
trap material 5 at interface 214 (FIG. 12) is made up of silicon atoms 220A-220Z (Z being the number of silicon atoms), and oxygen atoms 221A-221X (X being the number of oxygen atoms), wherein X<Z. Although silicon and oxygen atoms were just described in one example,trap material 5 is any material in an amorphous (and vitreous, meaning that the atomic structure is ordered only over short distances) form having free (or dangling) electron bonds. Another embodiment usestrap material 5 in the form of α-quartz which features a perfectly ordered arrangement of Si atoms located at the center of tetrahedral, and oxygen atoms at the vertexes. Each oxygen atom occupies a bridging location and forms two chemical bonds with Si atoms belonging to adjacent tetrahedral. - In the example illustrated in FIG. 12,
trap material 5 has dangling electron bonds 222A-222P, and also has stretched silicon-to-silicon Si—Si bonds 223A-223L. The dangling electron bonds 222A-222P are randomly distributed, and allow for electrons to rapidly exchange charges, also known as ‘fast surface states,’ and can become hole traps as they can capture and release electron carriers. Hole traps can be of two types: acceptor traps (that are empty holes) and donor traps (that are occupied holes). - When acceptor traps are empty or neutral and a field is generated and electrons start moving, these traps are filled with negatively charged electrons and become donor traps, which are neutral when occupied (and are positively charged). Depending on the implementation, such traps may be filled in, e.g. 327 picoseconds.
Storage capacitor 33 and inductor 34 (FIG. 5) cause an electrical field 204 (FIG. 12) alonginterface 214 to expand and collapse, which in turn causes electrons to move into and become trapped in thisinterface 214. As theelectrical field 204 expands the amount of work or kinetic energy used to move the electrons into the traps is measured by monitoring voltage or current produced by the sense capacitor 55 (FIG. 5). If interface 214 (also called “storage tunnel”) already contains trapped electrons, then more electrons will be free to migrate to thesense capacitor 55 and the output of thesense capacitor 55 will more closely follow thesource 31 of the input voltage. Ifinterface 214 does not contain trapped electrons then most of the kinetic energy will be used to move electrons to interface 214 (FIG. 12) and trap them. The output charge ofsense capacitor 55 will be delayed untilinterface 214 reaches a full or equilateral state. - In one embodiment of the device, a via hole101 (FIG. 13) is created in semiconductor material 102 (such as a wafer of silicon, or germanium) that may be present in a
semiconductor substrate 103. In one example a circular three-micron wide by 10 micronsdeep hole 101 with an aspect ratio of 3 to 10 is created insemiconductor substrate 103. The shape of viahole 101 in cross-section is circular, elliptical, square, triangular or any other shape that allows a conductive sleeve 3 (FIG. 14) to be built separate and distinct from a core 195 (to form an inductor when a trace is coupled to one end of the conductive sleeve 3). Moreover, as noted elsewhere, the sidewall of viahole 101 can be slanted, so thatcore 195 has the shape of a frustrum of a cone. The width W (FIG. 13) of viahole 101 is sufficiently large enough to allowhole 101 to accommodate at least a core, trapping material surrounding the core, and a conductive sleeve surrounding the trapping material (as discussed above in reference to FIG. 1), each of uniform thickness as discussed below. - As process technology evolves the aspect ratio of height to width is changed to allow for the creation of devices of different resonant frequencies. The ratio is determined by the design of the inductive storage capacitor, because the capacitance and the inductance depend on the speed of operation of the device (which in turn is determined by a resonant frequency).
- Thereafter, a layer104 (FIG. 14) of a conductive material, like aluminum or copper, is formed in
hole 101.Conductive sleeve 3 is formed as a sidewall in contact with a surface of viahole 101. Depending on the manufacturing process, the just-described sidewall is perpendicular to thesurface 105 ofsemiconductor substrate 103, but may be angled to reduce faseting and trenching of layers that are to be deposited in the space defined byconductive sleeve 3. An additional step may be performed, to deposit a dielectric material between a surface of viahole 101 andconductive sleeve 3 to protect operation ofsleeve 191 in the presence of impurities insubstrate 102. - A
layer 104 of electrically conductive material (like aluminum, copper, platinum, titanium, or polysilicon) is deposited (FIG. 14) into the viahole 101 using a PVD processing. In one embodiment the sleeve thickness T, e.g. of 10 angstroms of conductive aluminum material was used. A Rapid Thermal Process (RTP) may be used to anneal thesurface 21 if thesurface 21 contains spikes, e.g. created by the physical vapor deposition (PVD) process. - In one embodiment, a second layer192 (FIG. 15) is formed (e.g. of silicon (Si)) on
surface 21 ofconductive layer 191.Second layer 192 is applied using, e.g. chemical vapor deposition (CVD) process to deposit 30 angstroms (or 3 μm) thick silicon. Next a third layer 193 (FIG. 16) is formed, e.g. silicon dioxide (SiO2) is deposited at a thickness of 100 angstroms (or 10 μm) oversecond layer 192 using a CVD process creating trap material 5 (e.g. a silicon-silicon dioxide interface junction). A fourth layer 194 (FIG. 17) is formed, e.g. of silicon nitride (Si3N4) which has a high dielectric value is then deposited using a CVD process, overthird layer 193 at a thickness of 30 angstroms (or 3 μm). After formation oflayer 194, a hole is etched infloor 91, through layers 191-194, in one embodiment to obtain a desired resonant frequency, inductance or capacitance, or to eliminate secondary effects. Next, a plug 4 (FIG. 18) of a conductive material is formed using a PVD process into the viahole 101 to fill the via hole. - The thickness T of the sleeve and the area of surface21 (of sleeve 191) determine the sheet resistance, which can be used (as discussed above in reference to FIGS. 1 and 2) to calculate the inductance and the capacitance of
inductive storage capacitor 100. Such values are used to tune the device to operate at any desired resonant frequency. The resistance and capacitance are used to compute an RC transmission line value, and the circuit delay is calculated therefrom, to determine the proper timing for reading the charge status of the device to determine if the trap material contains a charge. The size (diameter and height) ofplug 4 determines the area ofsurface 180, that in turn is used to calculate the capacitance. The density ofplug 4 is used to calculate the inductance. The area of anend surface 181 ofplug 4 is determined to calculate the capacitance of asense capacitor 48. By changing the height and diameter of the core (formed by plug 4) different values are achieved for each of the inductance, and the two capacitances, to tune the device for a specific resonant frequency for the operation of the device. - In one embodiment, a
dielectric layer 196, e.g. of silicon nitride (Si3N4) (FIG. 19) of high dielectric value, is then deposited using a CVD process, overplug 4 at a thickness of 200 angstroms or 20 μm. A conductive layer 197 (FIG. 20), e.g. of polysilicon (or other conductive material like aluminum) is deposited using a CVD or PVD process over thedielectric layer 196 to formsense capacitor 48. The surface area of a portion oflayer 197 used to formsense capacitor 48 is calculated to determine the capacitance ofsense capacitor 48. - Although other cross-sections may be used in other embodiments, in one embodiment the device illustrated in FIG. 20 has a circular cross-section (FIG. 21) when viewed along the section line AA (FIG. 20). Specifically, each of layers191-194 have circular cross-sections and form concentric circles surrounding one another, with
layer 191 being the outermost layer.Innermost layer 194 surroundscore 195 that also has a circular cross-section. - In one embodiment, during operation,
inductive storage capacitor 100 is charged and discharged as illustrated in FIGS. 22-25. FIG. 22 shows the timing sequence for readinginductive storage capacitor 100 that has a discharged state initially at time t0 (shown on the X axis), and for writing intoinductive storage capacitor 100 a charged state by time t4. Specifically, curves 321-324 represent, along the Y axis the input voltage Vi, inductive flux F, stored charge Cs, and sensor voltage Vs respectively. - At time t0, input voltage Vi, inductive flux F, stored charge Cs, and sensor voltage Vs are all zero. At time t0 a signal of voltage Vmax (e.g. 3V) is applied to trace 25 (FIG. 4), and in response the voltage at terminal 24 starts to rise as shown by
segment 321 a ofcurve 321 until voltage Vmax is reached at time t1. Simultaneously, a voltage-induced inductive flux F is formed as shown bysegment 322 a. This inductive field 23 (FIG. 4) is present between thestorage capacitor elements segment 323 a ofcurve 323. As both capacitor 29 (FIG. 2) charges andinductive field 23 increases, the electron population intrap material 5 increases. Therefore, at time t1, a charge C1 is stored intrap material 5. Charge C1 is smaller than another charge C2 that denotes a charged state. - Simultaneously, in the time period t0-t1,
sense capacitor 48 starts to charge slowly as shown bysegment 324 a because most of the energy injected into theinductive storage capacitor 100 is used to move free electrons into storage tunnel formed atinterface 214. When the voltage level Vi on thestorage capacitor 29 is equal to the supply voltage Vmax at time t1 then theinductive field 23 collapses as shown bysegment 322 b. -
Sense capacitor 48 has an output voltage Vs as shown bysegment 324 a, and this voltage is tested at time t1 to find out if the energy injected into theinductive storage capacitor 100 has caused the output voltage Vs to rise above a threshold Vthresh. In this example, the output voltage Vs is below the threshold Vthresh, and therefore the state of theinductive storage capacitor 100 is discharged. Instead of having just two states of charged and discharged as described above in reference to FIG. 22, aninductive storage capacitor 100 can have one or more intermediate states, e.g. have a total of four states (indicating four levels of stored charge), if the threshold Vthresh is reached at different time intervals from start time t0 as discussed below in reference to FIG. 25. For examples of implementing such multiple states using a single storage capacitor, see Chapter 6 of the book entitled “Flash Memories” by Paolo Cappelletti et al. Kluwer Academic Publishers, 1999, which chapter is incorporated by reference herein in its entirety. - As
inductive field 23 collapses as shown bysegment 322 b a number of free electrons (representing additional charge C2-C1) entertrap material 5 as shown bysegment 323 b (between times t1 and t2) and the opposite charges will rapidly collect onsense capacitor 48 as shown bysegment 324 b (between times t1 and t2). This rapid movement of charges (as shown bysegment 323 b) causes a voltage and current spike as shown bysegments sense capacitor 48. - In this embodiment, the output voltage Vs of
sense capacitor 55 is monitored by sensor 56 a second time, at time t2, in addition to the monitoring at time t1 as discussed above, to verify that storage of charge C2 (indicative of the read process) has occurred, by checking that Vs has exceeded Vthresh. Ifinductive storage capacitor 100 is defective, this test fails, thereby to identify a failed device. Therefore,inductive storage capacitor 100 has built in error checking of the type not available in prior art storage capacitors. - If
inductive storage capacitor 100 is to be charged after the read process, then theinput terminal 24 is disconnected from the voltage supply 31 (FIG. 5) as shown bysegment 321 d, because a charge has been already stored as described above in reference to FIG. 22. Because the dielectrics are not perfect, some leakage ofstorage capacitor 100 occurs slowly over time (depending on the dielectric leakage) as shown bysegment 321 d. This slow decay occurs after time t3, and is insufficient to cause a significant inductive field to be formed (field sufficiently significant to discharge the charge C2 to zero coulombs over the life of the device, e.g. 1 year). - If
inductive storage capacitor 100 happens to contain a stored charge prior to the read process (as illustrated bysegment 333 a in FIG. 23), then during time period t0-t1, voltage Vs (seesegment 334 a) at the output trace 198 (FIG. 9) ofsense capacitor 55 follows the voltage Vi (seesegment 321 a) presented atinput terminal 24. In this case, output voltage Vs exceeds the threshold voltage Vthresh at a time t0 a, prior to time t1. Time t0 a being smaller than time t1 indicates tosensor 56 thatinductive storage capacitor 100 contained a stored charge prior to the read process. In all other respects,inductive storage capacitor 100 operates in the same manner as described above in reference to FIG. 22, including operation ofsense capacitor 48 at time t2 to verify that a charge has been stored. - To store a discharged state in
inductive storage capacitor 100, the input terminal of thestorage capacitor 29 is grounded (seesegment 341 c in FIG. 24).Storage capacitor 29 is discharged and opposite polarity inductive field (shown negative in FIG. 24) is generated (seesegment 342 c). Whenstorage capacitor 29 has completely discharged (seesegment 341 d) and is at or below ground reference (see time period t3-t4) then the inductive field 23 (seesegment 342 d) collapses to reach zero at time t4. During time period t2-t3, the opposite polarity inductive field starts to empty the stored charge in trap material 5 (as shown bysegment 343 c). Between times t3 and t4, the collapse ofinductive field 23 forces the electrons intrap material 5 to be attracted to surface 44 (FIG. 4) andtrap material 5 becomes empty (seesegment 343 d) at time t4. During time period t2-t3, the charge insense capacitor 55 also decays (seesegment 344 c) in response to the loss of charge intrap material 5, and when thestorage capacitor 29 has discharged (at time t4) thesense capacitor 55 will have also discharged (seesegment 344 d). During this storage process as well,sense capacitor 48 may verify that a discharge occurred, e.g. if the voltage atoutput trace 198 ofsense capacitor 55 falls to a negative threshold Vn at time t4 (e.g. a −3 volt spike). - In one embodiment,
input terminal 24 ofstorage capacitor 29 is grounded (seesegment 351 c in FIG. 25), andinductive storage capacitor 100 operates as discussed above in reference to FIG. 24, except for a shorter duration than t2-t4. Specifically, the duration is selected to implement one or more partially charged states forinductive storage capacitor 100. For example, to implement two states in addition to the charged and discharged states,input terminal 24 is decoupled from the ground reference (e.g. allowed to float) after the respective durations Tx and Ty, as illustrated by segments 71-72, and thereforestorage capacitor 29 remains partially charged as illustrated by segments 73-74. The partially stored charge ininductive storage capacitor 100 is read at durations Tx and Ty that are identical to the corresponding durations used in storing the partial charge, because the device charges and discharges at the same rate due to the resonant frequency. Such multiple states ofinductive storage capacitor 100 are used to store multiple bits of data. - In another embodiment (FIG. 26A) the
inductive storage capacitor 360 is constructed on top of a semicondutor wafer instead of inside a via hole. In this exampleinductive storage capacitor 360 has been created upside down in the same manner as that described above in reference to FIGS. 13-20 except for the following differences. The processing steps are reversed with construction of theinductive storage capacitor 360 starting with aconductive layer 197 that is used to form sense capacitor 48 (FIG. 4). Specifically,conductive layer 197 is deposited using either a metal or polysilicon. Next, adielectric layer 196 is deposited onconductive layer 197 using a CVD process. Thereafter, plug 195 (e.g. metal) is deposited followed by fourth layer 194 (e.g. silicon nitride (Si3N4)). The third layer 193 (e.g. silicon dioxide) and second layer 192 (e.g. silicon) are then added. Then first layer 191 (e.g. metal that forms a sleeve or cup) is deposited and connected to the circuit to forminductive storage capacitor 360. - Note that several of the just-described acts can be performed after a thick dielectric is deposited and then a via hole created, e.g. layers192-195 are deposited in the via hole. Also, a transistor 363 (FIG. 26B) can be built first, followed by formation of
inductive storage capacitor 360 as described above. Specifically, drain 367,source 368 andbase 369 are initially implanted into asubstrate 399, followed by formation ofinterconnects substrate 399. Next, agate oxide 362 is deposited and agate junction 365 is also deposited, followed bymore oxide 362. Thereafter, via 198 is formed in contact withgate junction 365, followed by formation of layers 197-191 as described above. - In another embodiment (FIG. 27) the
inductive storage capacitor 360 is formed upside down over a transistor (as described above in reference to FIG. 26A), but the transistor'scontrol gate 365 and via 198 are eliminated. The function ofgate 365 is performed byconductive layer 197 ofsense capacitor 55. In yet another embodiment (FIG. 28) the inductive storage capacitor is formed as described above in reference to FIG. 27, butconductive layer 197 ofsense capacitor 55 is eliminated. The function of gate 365 (FIG. 26) is performed byplug 195. In still another embodiment, a roof 290 (FIG. 28) is eliminated (e.g. etched away or not deposited) thereby to form asleeve 191 instead of a cup (FIG. 29). - In yet another embodiment, a plug195 (of any inductive storage capacitor as described herein) is made hollow, e.g. has a hole 401 (FIG. 30) at the center, and a
material 402 may be deposited in such ahole 401.Material 402 can be formed in an amorphous (and vitreous, meaning that the atomic structure is ordered only over short distances) form to create free or dangling electron bonds, same astrap material 5. Therefore,material 402 forms an additional storage tunnel (of the type described above in reference to trap material 5). The two storage tunnels in such an inductive storage capacitor act in concert to work better than a single storage tunnel. When two storage tunnels are used, a sense capacitor may be eliminated to prevent a charge in the storage tunnel in the plug from generating a false signal in the sense capacitor. - Note that the just-described additional storage tunnel can replace the storage tunnel at interface214 (FIG. 12), for example if
trap material 5 is not present betweensleeve 3 and plug 4 (FIG. 1). In such a case,trap material 5 is replaced with any dielectric material. - In alternative embodiments,
material 402 can be any material that is responsive to aninductive field 23. In one implementation,material 402 is a ferroelectric material that has a perovskite crystal structure described by the general chemical formula ABO3, where A and B are large and small cations respectively. Therefore, any material that has paraelectric, pyroelectric, piezoelectric, or ferroelectric property can be embedded inplug 195. Examples of ferroelectric material that can be embedded inplug 195 include Pb,Zr,TiO3 (PZT); Pb,La,TiO3 (PLT); Pb,La,Zr,TiO3 (PLZT); BaTiO3; Pb,Mg,NbO3 (PMN); Pb,Mg,NbO3—PbTiO3 (PMNPT); SrTiO3 to name a few. - A
plug 195 that has embedded therein a piezoelectric material may also be used with an inductive storage capacitor that is devoid oftrap material 5. In such a case, use of a piezoelectric material inplug 195 has the advantage of being able to control the direction and/or modulation of a beam of light or electrons or electromagnetic energy. Therefore, such a device can be used with a source of light (such as an LED or TFT) built into a semiconductor substrate, e.g. instead of a transistor as described above in reference to FIGS. 26-29. - In one embodiment, an inductive storage capacitor of the type described herein is used as a storage element50 (FIG. 31) in a
memory cell 501 that may include aswitch 505 coupled tostorage element 50 by aconductive trace 25.Switch 505, when operated by a control signal on aline 506, couples a trace 500 (that carries a signal of voltage Vmax) to an input terminal of storage element 50 (via trace 25).Memory cell 501 may be operated by a read/write switch 502 that provides the control signal online 506.Memory cell 501 is coupled by anoutput trace 507 to a sensor 56 (as described above in reference to FIG. 5). - In one implementation,
switch 505 is implemented by an NMOS transistor 605 (FIG. 32) having a gate connected to trace 506 (that is connected to read/write switch 502 as discussed above), andstorage element 50 is implemented byinductive storage capacitor 100.Transistor 605 is turned on during the read cycle, and the output of theinductive storage capacitor 100 is read by the sensor 56 (that is implemented by a CMOS transistor 604). - In one embodiment, the following signals (wherein 1 represents a charged state and 0 represents a discharged state) are present at the input/output terminals of
memory cell 501.Input line Read/Write Memory Cell Memory Cell 500 line 506state output 507 Read 0 1 1 Discharged 0 Read 1 1 1 Charged 1 Write 0 0 1 Discharged −1 Write 1 float 0 Charged 0 - Specifically, in a read operation,
input line 500 and read/write line 506 both carry a high signal, and a stored charge (either 0 or 1) is supplied onoutput line 507. Note that at the end of each read operation,memory cell 501 has been charged. In an operation to write a 0,input line 500 carries 0 and read/write line 506 carries a high signal, andmemory cell 501 is discharged to a voltage of zero. In an operation to write a 1,input line 500 floats and read/write line 506 carries a low signal, andmemory cell 501 stays charged. - In one embodiment, a memory array340 (FIG. 33) uses a number of inductive storage capacitors (of the type described herein), each coupled to receive a signal of voltage Vmax from a respective transistor, thereby to form a two-dimensional array of
memory cells 100 a-100 z. An address bus 341 (e.g. coupled to a CPU) provides input signals for anaddress decoder 342. In response to the input signals,address decoder 342 selects one of severalselect lines 343 a through 343 n to access arow 350 a ofmemory cells 100 a through 100 g located in the array. An active signal onselect line 343 a fromdecoder 342, causesvoltage source 344 to provide signals totiming control circuit 354 that in turn supplies a signal totransistor 345 a. -
Transistor 345 a passes the signal from timingcontrol circuit 354, through aline 350 a, to each ofmemory cells 100 a-100 g. Transistors 346 a-346 g in therespective memory cells 100 a-100 g have their gates coupled via their respective transistors 348 a-348 g to adata decoder 353.Data decoder 353 receives a control signal (e.g. from timing control circuit 354) to turn on transistors 346 a-346 g during a read operation. When turned on, transistors 346 a-346 g pass the signal of voltage Vmax fromvoltage source 344 to their respective inductive storage capacitors (not labeled). In response, inductive storage capacitors provide their stored charges to output lines 373 a-373 g that are coupled to the respective sensors 349 a-349 g. Sensors 349 a-349 g are coupled to alatch 356, that in turn provides the latched signals to anoutput data bus 357. - During a write operation,
address decoder 342 operates in the same manner as that discussed above for the read operation. The data to be stored is received on aninput data bus 352, and is decoded indata decoder 353.Data decoder 353 operates transistors 348 a-348 g to drive appropriate signals to the respective inductive storage capacitors, to write a zero (or discharged state) or one (or charged state). When a zero (or 1) is set then the column transistor 348 a-348 g is turned on (or off) to allow thevoltage source 344 to discharge (or stay charged) memory cellslOOa-100 g. - To generate signals for transistors348 a-348 g,
data decoder 353 inverts the data received ondata input bus 352, because a previous read operation has leftmemory cells 100 a-100 g in a charged state, anddata decoder 353 must determine which cells must be discharged (to reflect the data received on bus 352). As a read operation always precedes a write operation,decoder 353 must invert the data signal. - Furthermore, as a read operation results in charged state of the
memory cells 100 a-100 g, all data stored in these cells is no longer left therein, thereby resulting in a destructive read. Therefore, latch 356 may be coupled to transistors 346 a-346 g which pass the signal of voltage Vmax fromvoltage source 344 to their respective inductive storage capacitors (not labeled), so that the just-read data is rewritten (at the end of a read operation) intomemory cells 100 a-100 g. Note that any addressing circuitry that operates with destructive read memory cells can be used, e.g. see U.S. Pat. No. 4,153,934 that is incorporated by reference herein in its entirety. - Numerous modifications and adaptations of the embodiments, implementations and examples described herein will be apparent to the skilled artisan in view of the disclosure. For example, an inductive capacitor of the type described herein, but devoid of the trap material, is used in one embodiment of a radio-frequency circuit (such as an RF detector) as an LC filter. Such an LC filter has the advantage of eliminating the need for an external filter, and takes less real estate on the die than a conventional LC filter in which the inductor is formed separate and distinct from the capacitor. Furthermore, although in some embodiments, certain surfaces are flat, or cylindrical, or parallel, or coaxial to one another, in other embodiments, other surfaces may just approximate such surfaces to within 10% variation in a measure of the respective properties (such as two surfaces with 10% variation in distance therebetween are considered approximately parallel, and a surface is considered approximately cylindrical if it fits within two concentric cylinders with the smaller cylinder having 90% of the volume of the larger cylinder), depending on manufacturing constraints.
- Numerous such modifications and adaptations are encompassed by the attached claims.
Claims (51)
1. A device comprising:
a first element;
a second element at least partially surrounding the first element and physically separated from the first element; and
a material having a plurality of dangling bonds, said material being located between said first element and said second element.
2. The device of claim 1 further comprising:
a semiconductor substrate;
wherein each of the first element, the second element and the material are supported by the semiconductor substrate, and the material includes a semiconductor material.
3. The device of claim 1 wherein the second element surrounds a majority of a surface of the first element.
4. The device of claim 1 wherein the first element includes an electrical conductive material.
5. The device of claim 1 wherein the second element includes an electrical conductive material.
6. The device of claim 1 wherein the first element is at least approximately cylindrical in shape.
7. The device of claim 1 further comprising:
a third element physically separated from each of the first element and the second element, the third element being located transverse to each of a first axis of the first element and a second axis of the second element.
8. The device of claim 7 wherein the first element and the third element form a capacitor.
9. The device of claim 7 wherein the first element has a first end facing the third element, the first end being at least approximately flat.
10. The device of claim 9 wherein the third element has a surface at least approximately parallel to the first end.
11. The device of claim 7 wherein each of the second element and the third element include a common electrical conductive material.
12. The device of claim 7 wherein the second element includes one electrical conductive material and the third element includes another electrical conductive material.
13. The device of claim 7 wherein an electrical charge can be sensed in the third element.
14. The device of claim 1 wherein the first element includes a trap material surrounded by an electrically conductive material.
15. The device of claim 1 wherein the first element and the second element form a capacitor.
16. The device of claim 1 wherein the first element and the second element form a first capacitor and the first element and the third element form a sense capacitor, wherein the first capacitor and the sense capacitor are coupled in series.
17. The device of claim 1 wherein the first element and the second element form an inductor, with the first element acting as a core and the second element acting as a coil.
18. The device of claim 1 wherein the first element generates an electrical charge in response to applying power to the second element.
19. The device of claim 1 wherein:
the first element is cylindrical in shape with at least one flat end;
the first element and the second element are conductive;
a material between the first element and the second element is at least substantially dielectric;
the third element is at least substantially parallel to the flat end of the first element; and
another material between the first element and the third element is at least substantially dielectric.
20. A device comprising:
an annular element located in a via hole of a semiconductor material;
a plug located in the via hole and surrounded at least partially by but isolated from the annular element; and
another element facing one end of the plug.
21. The device of claim 20 wherein the plug is at least approximately cylindrical in shape.
22. The device of claim 21 wherein an axis of the annular element is at least approximately coaxial with an axis of the plug.
23. The device of claim 20 wherein said another element is connected to the annular element and is isolated from the plug, and the device further includes yet another element facing another end of the plug.
24. The device of claim 23 wherein the only connection of said another element to a voltage source is through the annular element.
25. The device of claim 20 wherein:
said another element is at least approximately planar and is hereinafter referred to as “end element”; and
said end element is isolated from each of the plug and the annular element.
26. The device of claim 25 further including yet another element located transverse to and connected to the annular element, wherein said elements at least partially enclose the plug.
27. A device comprising:
an element located in a via hole of a semiconductor material; and
a core located in the via hole and separated from but at least partially surrounded by the element.
28. The device of claim 27 wherein when viewed in a direction perpendicular to the core:
a portion of the element overlaps at least a region of the core, and
another portion of the element surrounds the core.
29. The device of claim 27 wherein the element is hereinafter “first element” and the device further comprises:
a second element separated from the core and overlapping at least a region of the core when viewed in a direction perpendicular to the core.
30. The device of claim 29 wherein the first element is connected to a first conductor for carrying a first voltage, the second element is connected to a second conductor for carrying a second voltage, and the core is not connected to any conductor.
31. A multilayered structure comprising:
a cup-shaped element defining an interior volume; and
a core located in the interior volume and separated from but surrounded by a first wall of the cup-shaped element, one end of the core facing a second wall of the cup-shaped element;
wherein said second wall is transverse to and connected to said first wall.
32. The device of claim 31 further comprising:
an electrode separated from each of the core and the cup-shaped element, the electrode facing another end of the core.
33. The device of claim 32 wherein:
the electrode and the cup-shaped element substantially enclose the core.
34. The device of claim 32 further comprising:
a dielectric element formed of a semiconductor material and located between the core and the electrode.
35. The device of claim 31 further comprising:
a dielectric element formed of a semiconductor material and located between the cup-shaped element and the core.
36. A circuit comprising:
a capacitor;
an inductor coupled in parallel to said capacitor; and
a dielectric material located inside said capacitor, said dielectric material having a plurality of traps.
37. The circuit of claim 36 wherein:
the inductor is in contact with the dielectric material.
38. The circuit of claim 36 wherein:
the inductor is adjacent to the dielectric material.
39. The circuit of claim 36 wherein:
during operation of said circuit said inductor generates a field passing through said dielectric material.
40. The circuit of claim 36 further comprising:
a sensor coupled to said capacitor.
41. The circuit of claim 40 wherein:
said capacitor and said inductor are coupled to a common terminal;
said sensor is coupled to said common terminal; and
a voltage source is coupled to said common terminal.
42. The circuit of claim 36 wherein said capacitor is hereinafter “first capacitor,” and the circuit further comprises:
a second capacitor in series with said first capacitor.
43. The circuit of claim 42 wherein:
said dielectric material is not present inside said second capacitor.
44. The circuit of claim 42 further comprising:
a sensor coupled to said second capacitor.
45. The circuit of claim 44 wherein:
a voltage source is coupled to a terminal of said first capacitor; and
said sensor is coupled to a terminal of said second capacitor.
46. A method comprising:
forming a via hole in a semiconductor material;
forming a first layer of conductive material inside the via hole;
forming a second layer of insulative material over the first layer, the second layer defining an interior volume;
forming a third layer of trap material in said interior volume;
forming a fourth layer of insulative material outside said via hole; and
forming a fifth layer of conductive material over the fourth layer.
47. The method of claim 46 wherein:
the third layer fills the interior volume;
the third layer contacts the second layer; and
the third layer contacts the fourth layer.
48. A method comprising:
forming a first layer of conductive material in the shape of a column, over a semiconductor material;
forming a second layer of insulative material over the first layer;
forming a fourth layer of insulative material over the second layer while simultaneously forming a third layer of trap material at an interface between the second layer and the fourth layer; and
forming a fifth layer of conductive material over the fourth layer.
49. A computer comprising:
a monitor displaying a symbol, the symbol including:
two parallel line segments; and
a spiral wrapped around the two parallel line segments; and
a memory encoded with software that simulates a capacitor and inductor combination represented by the symbol.
50. A method of forming a circuit diagram, the method comprising:
drawing two parallel line segments and a spiral wrapped around the two parallel line segments to form a symbol;
fc drawing a symbol of a circuit element selected from a group consisting of a transistor and a resistor; and
drawing a line connecting the circuit element and the symbol.
51. The method of claim 50 further comprising:
drawing a rectangle between the two parallel line segments.
Priority Applications (1)
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US10/413,795 US20030178639A1 (en) | 2001-02-02 | 2003-04-14 | Inductive storage capacitor |
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US09/776,003 US6642552B2 (en) | 2001-02-02 | 2001-02-02 | Inductive storage capacitor |
US10/413,795 US20030178639A1 (en) | 2001-02-02 | 2003-04-14 | Inductive storage capacitor |
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US09/776,003 Division US6642552B2 (en) | 2001-02-02 | 2001-02-02 | Inductive storage capacitor |
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US20030178639A1 true US20030178639A1 (en) | 2003-09-25 |
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US09/776,003 Expired - Lifetime US6642552B2 (en) | 2001-02-02 | 2001-02-02 | Inductive storage capacitor |
US10/413,795 Abandoned US20030178639A1 (en) | 2001-02-02 | 2003-04-14 | Inductive storage capacitor |
US10/694,661 Abandoned US20040084751A1 (en) | 2001-02-02 | 2003-10-27 | Inductive storage capacitor |
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US09/776,003 Expired - Lifetime US6642552B2 (en) | 2001-02-02 | 2001-02-02 | Inductive storage capacitor |
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US10/694,661 Abandoned US20040084751A1 (en) | 2001-02-02 | 2003-10-27 | Inductive storage capacitor |
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WO (1) | WO2002075818A2 (en) |
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US20020145904A1 (en) | 2002-10-10 |
US6642552B2 (en) | 2003-11-04 |
WO2002075818A3 (en) | 2002-11-07 |
US20040084751A1 (en) | 2004-05-06 |
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