US20030034491A1 - Structure and method for fabricating semiconductor structures and devices for detecting an object - Google Patents
Structure and method for fabricating semiconductor structures and devices for detecting an object Download PDFInfo
- Publication number
- US20030034491A1 US20030034491A1 US09/928,356 US92835601A US2003034491A1 US 20030034491 A1 US20030034491 A1 US 20030034491A1 US 92835601 A US92835601 A US 92835601A US 2003034491 A1 US2003034491 A1 US 2003034491A1
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- layer
- monocrystalline
- forming
- compound semiconductor
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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Abstract
High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. A high quality layer of compound semiconductor material is used to form a source component and a receiver component that are interconnected with an antenna and each other within a semiconductor structure that can detect a parameter, such as the speed, of an object.
Description
- This invention relates generally to semiconductor structures and devices and to a method for their fabrication, and more specifically to semiconductor structures and devices and to the fabrication and use of semiconductor structures, devices, and integrated circuits that include a monocrystalline material layer comprised of semiconductor material, compound semiconductor material, and/or other types of material such as metals and non-metals for detecting an object.
- Semiconductor devices often include multiple layers of conductive, insulating, and semiconductive layers. Often, the desirable properties of such layers improve with the crystallinity of the layer. For example, the electron mobility and band gap of semiconductive layers improves as the crystallinity of the layer increases. Similarly, the free electron concentration of conductive layers and the electron charge displacement and electron energy recoverability of insulative or dielectric films improves as the crystallinity of these layers increases.
- For many years, attempts have been made to grow various monolithic thin films on a foreign substrate such as silicon (Si). To achieve optimal characteristics of the various monolithic layers, however, a monocrystalline film of high crystalline quality is desired. Attempts have been made, for example, to grow various monocrystalline layers on a substrate such as germanium, silicon, and various insulators. These attempts have generally been unsuccessful because lattice mismatches between the host crystal and the grown crystal have caused the resulting layer of monocrystalline material to be of low crystalline quality.
- If a large area thin film of high quality monocrystalline material was available at low cost, a variety of semiconductor devices could advantageously be fabricated in or using that film at a low cost compared to the cost of fabricating such devices beginning with a bulk wafer of semiconductor material or in an epitaxial film of such material on a bulk wafer of semiconductor material. In addition, if a thin film of high quality monocrystalline material could be realized beginning with a bulk wafer such as a silicon wafer, an integrated device structure could be achieved that took advantage of the best properties of both the silicon and the high quality monocrystalline material.
- Accordingly, a need exists for a semiconductor structure that provides a high quality monocrystalline film or layer over another monocrystalline material and for a process for making such a structure. In other words, there is a need for providing the formation of a monocrystalline substrate that is compliant with a high quality monocrystalline material layer so that true two-dimensional growth can be achieved for the formation of quality semiconductor structures, devices and integrated circuits having grown monocrystalline film having the same crystal orientation as an underlying substrate. This monocrystalline material layer may be comprised of a semiconductor material, a compound semiconductor material, and other types of material such as metals and non-metals.
- Furthermore, a need exists for a semiconductor structure that provides a high quality monocrystalline film or layer over another monocrystalline material and a process for making such a structure to detect an object. A detection device such as a radar or a lidar may use transmitted and reflected radio waves or laser light for detecting an object. The detection device may further determine the range (i.e., distance or height) between the device itself and the object, and also the speed of the object as it either approaches or moves away from the device. Typically, detection devices require multiple components to detect an object. In particular, a detection device requires a source component and a receiver component. To reduce size, cost, and power consumption, it is desirable to integrate all components on a single semiconductor structure. However, semiconductor structures have not been available to do so.
- The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements, and in which:
- FIGS. 1, 2, and3 illustrate schematically, in cross section, device structures in accordance with various embodiments of the invention;
- FIG. 4 illustrates graphically the relationship between maximum attainable film thickness and lattice mismatch between a host crystal and a grown crystalline overlayer;
- FIG. 5 illustrates a high resolution Transmission Electron Micrograph of a structure including a monocrystalline accommodating buffer layer;
- FIG. 6 illustrates an x-ray diffraction spectrum of a structure including a monocrystalline accommodating buffer layer;
- FIG. 7 illustrates a high resolution Transmission Electron Micrograph of a structure including an amorphous oxide layer;
- FIG. 8 illustrates an x-ray diffraction spectrum of a structure including an amorphous oxide layer;
- FIGS.9-12 illustrate schematically, in cross-section, the formation of a device structure in accordance with another embodiment of the invention;
- FIGS.13-16 illustrate a probable molecular bonding structure of the device structures illustrated in FIGS. 9-12;
- FIGS.17-20 illustrate schematically, in cross-section, the formation of a device structure in accordance with still another embodiment of the invention;
- FIGS.21-23 illustrate schematically, in cross-section, the formation of yet another embodiment of a device structure in accordance with the invention;
- FIGS. 24, 25 illustrate schematically, in cross section, device structures that can be used in accordance with various embodiments of the invention;
- FIGS.26-30 include illustrations of cross-sectional views of a portion of an integrated circuit that includes a compound semiconductor portion, a bipolar portion, and an MOS portion in accordance with what is shown herein;
- FIGS.31-37 include illustrations of cross-sectional views of a portion of another integrated circuit that includes a semiconductor laser and a MOS transistor in accordance with what is shown herein;
- FIG. 38 illustrates schematically a semiconductor structure for detecting an object in accordance with what is shown herein; and
- FIG. 39 illustrates a flow diagram of a method for detecting an object in accordance with what is shown herein.
- Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.
- FIG. 1 illustrates schematically, in cross section, a portion of a
semiconductor structure 20 in accordance with an embodiment of the invention.Semiconductor structure 20 includes amonocrystalline substrate 22,accommodating buffer layer 24 comprising a monocrystalline material, and amonocrystalline material layer 26. In this context, the term “monocrystalline” shall have the meaning commonly used within the semiconductor industry. The term shall refer to materials that are a single crystal or that are substantially a single crystal and shall include those materials having a relatively small number of defects such as dislocations and the like as are commonly found in substrates of silicon or germanium or mixtures of silicon and germanium and epitaxial layers of such materials commonly found in the semiconductor industry. - In accordance with one embodiment of the invention,
structure 20 also includes an amorphousintermediate layer 28 positioned betweensubstrate 22 and accommodatingbuffer layer 24.Structure 20 may also include atemplate layer 30 between the accommodating buffer layer andmonocrystalline material layer 26. As will be explained more fully below, the template layer helps to initiate the growth of the monocrystalline material layer on the accommodating buffer layer. The amorphous intermediate layer helps to relieve the strain in the accommodating buffer layer and by doing so, aids in the growth of a high crystalline quality accommodating buffer layer. -
Substrate 22, in accordance with an embodiment of the invention, is a monocrystalline semiconductor or compound semiconductor wafer, preferably of large diameter. The wafer can be of, for example, a material from Group IV of the periodic table, e.g., carbon, silicon, etc. Examples of Group IV semiconductor materials include silicon, germanium, mixed silicon and germanium, mixed silicon and carbon, mixed silicon, germanium and carbon, and the like. Preferablysubstrate 22 is a wafer containing silicon or germanium, and most preferably is a high quality monocrystalline silicon wafer as used in the semiconductor industry. Accommodatingbuffer layer 24 is preferably a monocrystalline oxide or nitride material epitaxially grown on the underlying substrate. In accordance with one embodiment of the invention, amorphousintermediate layer 28 is grown onsubstrate 22 at the interface betweensubstrate 22 and the growing accommodating buffer layer by the oxidation ofsubstrate 22 during the growth oflayer 24. The amorphous intermediate layer serves to relieve strain that might otherwise occur in the monocrystalline accommodating buffer layer as a result of differences in the lattice constants of the substrate and the buffer layer. As used herein, lattice constant refers to the distance between atoms of a cell measured in the plane of the surface. If such strain is not relieved by the amorphous intermediate layer, the strain may cause defects in the crystalline structure of the accommodating buffer layer. Defects in the crystalline structure of the accommodating buffer layer, in turn, would make it difficult to achieve a high quality crystalline structure inmonocrystalline material layer 26 which may comprise a semiconductor material, a compound semiconductor material, or another type of material such as a metal or a non-metal. - Accommodating
buffer layer 24 is preferably a monocrystalline oxide or nitride material selected for its crystalline compatibility with the underlying substrate and with the overlying material layer. For example, the material could be an oxide or nitride having a lattice structure closely matched to the substrate and to the subsequently applied monocrystalline material layer. Materials that are suitable for the accommodating buffer layer include metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates, alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide. Additionally, various nitrides such as gallium nitride, aluminum nitride, and boron nitride may also be used for the accommodating buffer layer. Most of these materials are insulators, although strontium ruthenate, for example, is a conductor. Generally, these materials are metal oxides or metal nitrides, and more particularly, these metal oxide or nitrides typically include at least two different metallic elements. In some specific applications, the metal oxides or nitrides may include three or more different metallic elements. -
Amorphous interface layer 28 is preferably an oxide formed by the oxidation of the surface ofsubstrate 22, and more preferably is composed of a silicon oxide. The thickness oflayer 28 is sufficient to relieve strain attributed to mismatches between the lattice constants ofsubstrate 22 andaccommodating buffer layer 24. Typically,layer 28 has a thickness in the range of approximately 0.5-5 nm. - The material for
monocrystalline material layer 26 can be selected, as desired, for a particular structure or application. For example, the monocrystalline material oflayer 26 may comprise a compound semiconductor which can be selected, as needed for a particular semiconductor structure, from any of the Group IIIA and VA elements (IIIV semiconductor compounds), mixed III-V compounds, Group II (A or B) and VIA elements (II-VI semiconductor compounds), and mixed II-VI compounds. Examples include gallium arsenide (GaAs), gallium indium arsenide (GaInAs), gallium aluminum arsenide (GaAlAs), indium phosphide (InP), cadmium sulfide (CdS), cadmium mercury telluride (CdHgTe), zinc selenide (ZnSe), zinc sulfur selenide (ZnSSe), and the like. However,monocrystalline material layer 26 may also comprise other semiconductor materials, metals, or non-metal materials which are used in the formation of semiconductor structures, devices and/or integrated circuits. - Appropriate materials for
template 30 are discussed below. Suitable template materials chemically bond to the surface of theaccommodating buffer layer 24 at selected sites and provide sites for the nucleation of the epitaxial growth ofmonocrystalline material layer 26. When used,template layer 30 has a thickness ranging from about 1 to about 10 monolayers. - FIG. 2 illustrates, in cross section, a portion of a
semiconductor structure 40 in accordance with a further embodiment of the invention.Structure 40 is similar to the previously describedsemiconductor structure 20, except that anadditional buffer layer 32 is positioned betweenaccommodating buffer layer 24 andmonocrystalline material layer 26. Specifically, the additional buffer layer is positioned betweentemplate layer 30 and the overlying layer of monocrystalline material. The additional buffer layer, formed of a semiconductor or compound semiconductor material when themonocrystalline material layer 26 comprises a semiconductor or compound semiconductor material, serves to provide a lattice compensation when the lattice constant of the accommodating buffer layer cannot be adequately matched to the overlying monocrystalline semiconductor or compound semiconductor material layer. - FIG. 3 schematically illustrates, in cross section, a portion of a
semiconductor structure 34 in accordance with another exemplary embodiment of the invention.Structure 34 is similar tostructure 20, except thatstructure 34 includes anamorphous layer 36, rather than accommodatingbuffer layer 24 andamorphous interface layer 28, and an additionalmonocrystalline layer 38. - As explained in greater detail below,
amorphous layer 36 may be formed by first forming an accommodating buffer layer and an amorphous interface layer in a similar manner to that described above.Monocrystalline layer 38 is then formed (by epitaxial growth) overlying the monocrystalline accommodating buffer layer. The accommodating buffer layer is then exposed to an anneal process to convert the monocrystalline accommodating buffer layer to an amorphous layer.Amorphous layer 36 formed in this manner comprises materials from both the accommodating buffer and interface layers, which amorphous layers may or may not amalgamate. Thus,layer 36 may comprise one or two amorphous layers. Formation ofamorphous layer 36 betweensubstrate 22 and additional monocrystalline layer 26 (subsequent to layer 38 formation) relieves stresses betweenlayers monocrystalline material layer 26 formation. - The processes previously described above in connection with FIGS. 1 and 2 are adequate for growing monocrystalline material layers over a monocrystalline substrate. However, the process described in connection with FIG. 3, which includes transforming a monocrystalline accommodating buffer layer to an amorphous oxide layer, may be better for growing monocrystalline material layers because it allows any strain in
layer 26 to relax. - Additional
monocrystalline layer 38 may include any of the materials described throughout this application in connection with either ofmonocrystalline material layer 26 oradditional buffer layer 32. For example, whenmonocrystalline material layer 26 comprises a semiconductor or compound semiconductor material,layer 38 may include monocrystalline Group IV or monocrystalline compound semiconductor materials. - In accordance with one embodiment of the present invention, additional
monocrystalline layer 38 serves as an anneal cap duringlayer 36 formation and as a template for subsequentmonocrystalline layer 26 formation. Accordingly,layer 38 is preferably thick enough to provide a suitable template forlayer 26 growth (at least one monolayer) and thin enough to allowlayer 38 to form as a substantially defect free monocrystalline material. - In accordance with another embodiment of the invention, additional
monocrystalline layer 38 comprises monocrystalline material (e.g., a material discussed above in connection with monocrystalline layer 26) that is thick enough to form devices withinlayer 38. In this case, a semiconductor structure in accordance with the present invention does not includemonocrystalline material layer 26. In other words, the semiconductor structure in accordance with this embodiment only includes one monocrystalline layer disposed aboveamorphous oxide layer 36. - The following non-limiting, illustrative examples illustrate various combinations of materials useful in
structures - In accordance with one embodiment of the invention,
monocrystalline substrate 22 is a silicon substrate oriented in the (100) direction. The silicon substrate can be, for example, a silicon substrate as is commonly used in making complementary metal oxide semiconductor (CMOS) integrated circuits having a diameter of about 200-300 mm. In accordance with this embodiment of the invention,accommodating buffer layer 24 is a monocrystalline layer of SrzBa1−zTiO3 where z ranges from 0 to 1 and the amorphous intermediate layer is a layer of silicon oxide (SiOx) formed at the interface between the silicon substrate and the accommodating buffer layer. The value of z is selected to obtain one or more lattice constants closely matched to corresponding lattice constants of the subsequently formedlayer 26. The accommodating buffer layer can have a thickness of about 2 to about 100 nanometers (nm) and preferably has a thickness of about 5 nm. In general, it is desired to have an accommodating buffer layer thick enough to isolate themonocrystalline material layer 26 from the substrate to obtain the desired electrical and optical properties. Layers thicker than 100 nm usually provide little additional benefit while increasing cost unnecessarily; however, thicker layers may be fabricated if needed. The amorphous intermediate layer of silicon oxide can have a thickness of about 0.5-5 nm, and preferably a thickness of about 1 to 2 nm. - In accordance with this embodiment of the invention,
monocrystalline material layer 26 is a compound semiconductor layer of gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs) having a thickness of about 1 nm to about 100 micrometers (μm) and preferably a thickness of about 0.5 μm to 10 μm. The thickness generally depends on the application for which the layer is being prepared. To facilitate the epitaxial growth of the gallium arsenide or aluminum gallium arsenide on the monocrystalline oxide, a template layer is formed by capping the oxide layer. The template layer is preferably 1-10 monolayers of Ti—As, Sr—O—As, Sr—Ga—O, or Sr—Al—O. By way of a preferred example, 1-2 monolayers of Ti—As or Sr—Ga—O have been illustrated to successfully grow GaAs layers. - In accordance with a further embodiment of the invention,
monocrystalline substrate 22 is a silicon substrate as described above. The accommodating buffer layer is a monocrystalline oxide of strontium or barium zirconate or hafnate in a cubic or orthorhombic phase with an amorphous intermediate layer of silicon oxide formed at the interface between the silicon substrate and the accommodating buffer layer. The accommodating buffer layer can have a thickness of about 2-100 nm and preferably has a thickness of at least 5 nm to ensure adequate crystalline and surface quality and is formed of a monocrystalline SrZrO3, BaZrO3, SrHfO3, BaSnO3 or BaHfO3. For example, a monocrystalline oxide layer of BaZrO3 can grow at a temperature of about 700 degrees C. The lattice structure of the resulting crystalline oxide exhibits a 45 degree rotation with respect to the substrate silicon lattice structure. - An accommodating buffer layer formed of these zirconate or hafnate materials is suitable for the growth of a monocrystalline material layer which comprises compound semiconductor materials in the indium phosphide (InP) system. In this system, the compound semiconductor material can be, for example, indium phosphide (InP), indium gallium arsenide (InGaAs), aluminum indium arsenide, (AlInAs), or aluminum gallium indium arsenic phosphide (AlGaInAsP), having a thickness of about 1.0 nm to 10 μm. A suitable template for this structure is 1-10 monolayers of zirconium-arsenic (Zr—As), zirconium-phosphorus (Zr—P), hafnium-arsenic (Hf—As), hafnium-phosphorus (Hf—P), strontium-oxygen-arsenic (Sr—O—As), strontium-oxygen-phosphorus (Sr—O—P), barium-oxygen-arsenic (Ba—O—As), indium-strontium-oxygen (In—Sr—O), or barium-oxygen-phosphorus (Ba—O—P), and preferably 1-2 monolayers of one of these materials. By way of an example, for a barium zirconate accommodating buffer layer, the surface is terminated with 1-2 monolayers of zirconium followed by deposition of 1-2 monolayers of arsenic to form a Zr—As template. A monocrystalline layer of the compound semiconductor material from the indium phosphide system is then grown on the template layer. The resulting lattice structure of the compound semiconductor material exhibits a 45 degree rotation with respect to the accommodating buffer layer lattice structure and a lattice mismatch to (100) InP of less than 2.5%, and preferably less than about 1.0%.
- In accordance with a further embodiment of the invention, a structure is provided that is suitable for the growth of an epitaxial film of a monocrystalline material comprising a II-VI material overlying a silicon substrate. The substrate is preferably a silicon wafer as described above. A suitable accommodating buffer layer material is SrxBa1−xTiO3, where x ranges from 0 to 1, having a thickness of about 2-100 nm and preferably a thickness of about 5-15 nm. Where the monocrystalline layer comprises a compound semiconductor material, the II-VI compound semiconductor material can be, for example, zinc selenide (ZnSe) or zinc sulfur selenide (ZnSSe). A suitable template for this material system includes 1-10 monolayers of zinc-oxygen (Zn—O) followed by 1-2 monolayers of an excess of zinc followed by the selenidation of zinc on the surface. Alternatively, a template can be, for example, 1-10 monolayers of strontium-sulfur (Sr—S) followed by the ZnSeS.
- This embodiment of the invention is an example of
structure 40 illustrated in FIG. 2.Substrate 22,accommodating buffer layer 24, andmonocrystalline material layer 26 can be similar to those described in example 1. In addition, anadditional buffer layer 32 serves to alleviate any strains that might result from a mismatch of the crystal lattice of the accommodating buffer layer and the lattice of the monocrystalline material.Buffer layer 32 can be a layer of germanium or a GaAs, an aluminum gallium arsenide (AlGaAs), an indium gallium phosphide (InGaP), an aluminum gallium phosphide (AlGaP), an indium gallium arsenide (InGaAs), an aluminum indium phosphide (AlInP), a gallium arsenide phosphide (GaAsP), or an indium gallium phosphide (InGaP) strain compensated superlattice. In accordance with one aspect of this embodiment,buffer layer 32 includes a GaAsxP1−x superlattice, wherein the value of x ranges from 0 to 1. In accordance with another aspect,buffer layer 32 includes an InyGal1−yP superlattice, wherein the value of y ranges from 0 to 1. By varying the value of x or y, as the case may be, the lattice constant is varied from bottom to top across the superlattice to create a match between lattice constants of the underlying oxide and the overlying monocrystalline material which in this example is a compound semiconductor material. The compositions of other compound semiconductor materials, such as those listed above, may also be similarly varied to manipulate the lattice constant oflayer 32 in a like manner. The superlattice can have a thickness of about 50-500 nm and preferably has a thickness of about 100-200 nm. The template for this structure can be the same of that described in example 1. Alternatively,buffer layer 32 can be a layer of monocrystalline germanium having a thickness of 1-50 nm and preferably having a thickness of about 2-20 nm. In using a germanium buffer layer, a template layer of either germanium-strontium (Ge—Sr) or germanium-titanium (Ge—Ti) having a thickness of about one monolayer can be used as a nucleating site for the subsequent growth of the monocrystalline material layer which in this example is a compound semiconductor material. The formation of the oxide layer is capped with either a monolayer of strontium or a monolayer of titanium to act as a nucleating site for the subsequent deposition of the monocrystalline germanium. The monolayer of strontium or titanium provides a nucleating site to which the first monolayer of germanium can bond. - This example also illustrates materials useful in a
structure 40 as illustrated in FIG. 2.Substrate material 22,accommodating buffer layer 24,monocrystalline material layer 26 andtemplate layer 30 can be the same as those described above in example 2. In addition,additional buffer layer 32 is inserted between the accommodating buffer layer and the overlying monocrystalline material layer. Theadditional buffer layer 32, a further monocrystalline material which in this instance comprises a semiconductor material, can be, for example, a graded layer of indium gallium arsenide (InGaAs) or indium aluminum arsenide (InAlAs). In accordance with one aspect of this embodiment,additional buffer layer 32 includes InGaAs, in which the indium composition varies from 0 to about 50%. Theadditional buffer layer 32 preferably has a thickness of about 10-30 nm. Varying the composition of the buffer layer from GaAs to InGaAs serves to provide a lattice match between the underlying monocrystalline oxide material and the overlying layer of monocrystalline material which in this example is a compound semiconductor material. Such a buffer layer is especially advantageous if there is a lattice mismatch betweenaccommodating buffer layer 24 andmonocrystalline material layer 26. - This example provides exemplary materials useful in
structure 34, as illustrated in FIG. 3.Substrate material 22,template layer 30, andmonocrystalline material layer 26 may be the same as those described above in connection with example 1. -
Amorphous layer 36 is an amorphous oxide layer which is suitably formed of a combination of amorphous intermediate layer materials (e.g.,layer 28 materials as described above) and accommodating buffer layer materials (e.g.,layer 24 materials as described above). For example,amorphous layer 36 may include a combination of SiOx and SrzBa1−z TiO3 (where z ranges from 0 to 1), which combine or mix, at least partially, during an anneal process to formamorphous oxide layer 36. - The thickness of
amorphous layer 36 may vary from application to application and may depend on such factors as desired insulating properties oflayer 36, type of monocrystallinematerial comprising layer 26, and the like. In accordance with one exemplary aspect of the present embodiment,layer 36 thickness is about 2 nm to about 100 nm, preferably about 2-10 nm, and more preferably about 5-6 nm. -
Layer 38 comprises a monocrystalline material that can be grown epitaxially over a monocrystalline oxide material such as material used to formaccommodating buffer layer 24. In accordance with one embodiment of the invention,layer 38 includes the same materials as those comprisinglayer 26. For example, iflayer 26 includes GaAs,layer 38 also includes GaAs. However, in accordance with other embodiments of the present invention,layer 38 may include materials different from those used to formlayer 26. In accordance with one exemplary embodiment of the invention,layer 38 is about 1 monolayer to about 100 nm thick. - Referring again to FIGS.1-3,
substrate 22 is a monocrystalline substrate such as a monocrystalline silicon or gallium arsenide substrate. The crystalline structure of the monocrystalline substrate is characterized by a lattice constant and by a lattice orientation. In similar manner,accommodating buffer layer 24 is also a monocrystalline material and the lattice of that monocrystalline material is characterized by a lattice constant and a crystal orientation. The lattice constants of the accommodating buffer layer and the monocrystalline substrate must be closely matched or, alternatively, must be such that upon rotation of one crystal orientation with respect to the other crystal orientation, a substantial match in lattice constants is achieved. In this context the terms “substantially equal” and “substantially matched” mean that there is sufficient similarity between the lattice constants to permit the growth of a high quality crystalline layer on the underlying layer. - FIG. 4 illustrates graphically the relationship of the achievable thickness of a grown crystal layer of high crystalline quality as a function of the mismatch between the lattice constants of the host crystal and the grown crystal.
Curve 42 illustrates the boundary of high crystalline quality material. The area to the right ofcurve 42 represents layers that have a large number of defects. With no lattice mismatch, it is theoretically possible to grow an infinitely thick, high quality epitaxial layer on the host crystal. As the mismatch in lattice constants increases, the thickness of achievable, high quality crystalline layer decreases rapidly. As a reference point, for example, if the lattice constants between the host crystal and the grown layer are mismatched by more than about 2%, monocrystalline epitaxial layers in excess of about 20 nm cannot be achieved. - In accordance with one embodiment of the invention,
substrate 22 is a (100) or (1111) oriented monocrystalline silicon wafer andaccommodating buffer layer 24 is a layer of strontium barium titanate. Substantial matching of lattice constants between these two materials is achieved by rotating the crystal orientation of the titanate material by 45° with respect to the crystal orientation of the silicon substrate wafer. The inclusion in the structure ofamorphous interface layer 28, a silicon oxide layer in this example, if it is of sufficient thickness, serves to reduce strain in the titanate monocrystalline layer that might result from any mismatch in the lattice constants of the host silicon wafer and the grown titanate layer. As a result, in accordance with an embodiment of the invention, a high quality, thick, monocrystalline titanate layer is achievable. - Still referring to FIGS.1-3,
layer 26 is a layer of epitaxially grown monocrystalline material and that crystalline material is also characterized by a crystal lattice constant and a crystal orientation. In accordance with one embodiment of the invention, the lattice constant oflayer 26 differs from the lattice constant ofsubstrate 22. To achieve high crystalline quality in this epitaxially grown monocrystalline layer, the accommodating buffer layer must be of high crystalline quality. In addition, in order to achieve high crystalline quality inlayer 26, substantial matching between the crystal lattice constant of the host crystal, in this case, the monocrystalline accommodating buffer layer, and the grown crystal is desired. With properly selected materials this substantial matching of lattice constants is achieved as a result of rotation of the crystal orientation of the grown crystal with respect to the orientation of the host crystal. For example, if the grown crystal is gallium arsenide, aluminum gallium arsenide, zinc selenide, or zinc sulfur selenide and the accommodating buffer layer is monocrystalline SrxBa1−xTiO3, substantial matching of crystal lattice constants of the two materials is achieved, wherein the crystal orientation of the grown layer is rotated by 45° with respect to the orientation of the host monocrystalline oxide. Similarly, if the host material is a strontium or barium zirconate or a strontium or barium hafnate or barium tin oxide and the compound semiconductor layer is indium phosphide or gallium indium arsenide or aluminum indium arsenide, substantial matching of crystal lattice constants can be achieved by rotating the orientation of the grown crystal layer by 45° with respect to the host oxide crystal. In some instances, a crystalline semiconductor buffer layer between the host oxide and the grown monocrystalline material layer can be used to reduce strain in the grown monocrystalline material layer that might result from small differences in lattice constants. Better crystalline quality in the grown monocrystalline material layer can thereby be achieved. - The following example illustrates a process, in accordance with one embodiment of the invention, for fabricating a semiconductor structure such as the structures depicted in FIGS.1-3. The process starts by providing a monocrystalline semiconductor substrate comprising silicon or germanium. In accordance with a preferred embodiment of the invention, the semiconductor substrate is a silicon wafer having a (100) orientation. The substrate is preferably oriented on axis or, at most, about 4° off axis. At least a portion of the semiconductor substrate has a bare surface, although other portions of the substrate, as described below, may encompass other structures. The term “bare” in this context means that the surface in the portion of the substrate has been cleaned to remove any oxides, contaminants, or other foreign material. As is well known, bare silicon is highly reactive and readily forms a native oxide. The term “bare” is intended to encompass such a native oxide. A thin silicon oxide may also be intentionally grown on the semiconductor substrate, although such a grown oxide is not essential to the process in accordance with the invention. In order to epitaxially grow a monocrystalline oxide layer overlying the monocrystalline substrate, the native oxide layer must first be removed to expose the crystalline structure of the underlying substrate. The following process is preferably carried out by molecular beam epitaxy (MBE), although other epitaxial processes may also be used in accordance with the present invention. The native oxide can be removed by first thermally depositing a thin layer of strontium, barium, a combination of strontium and barium, or other alkaline earth metals or combinations of alkaline earth metals in an MBE apparatus. In the case where strontium is used, the substrate is then heated to a temperature of about 750° C. to cause the strontium to react with the native silicon oxide layer. The strontium serves to reduce the silicon oxide to leave a silicon oxide-free surface. The resultant surface, which exhibits an ordered 2×1 structure, includes strontium, oxygen, and silicon. The ordered 2×1 structure forms a template for the ordered growth of an overlying layer of a monocrystalline oxide. The template provides the necessary chemical and physical properties to nucleate the crystalline growth of an overlying layer.
- In accordance with an alternate embodiment of the invention, the native silicon oxide can be converted and the substrate surface can be prepared for the growth of a monocrystalline oxide layer by depositing an alkaline earth metal oxide, such as strontium oxide, strontium barium oxide, or barium oxide, onto the substrate surface by MBE at a low temperature and by subsequently heating the structure to a temperature of about 750° C. At this temperature a solid state reaction takes place between the strontium oxide and the native silicon oxide causing the reduction of the native silicon oxide and leaving an ordered 2×1 structure with strontium, oxygen, and silicon remaining on the substrate surface. Again, this forms a template for the subsequent growth of an ordered monocrystalline oxide layer.
- Following the removal of the silicon oxide from the surface of the substrate, in accordance with one embodiment of the invention, the substrate is cooled to a temperature in the range of about 200-800° C. and a layer of strontium titanate is grown on the template layer by molecular beam epitaxy. The MBE process is initiated by opening shutters in the MBE apparatus to expose strontium, titanium and oxygen sources. The ratio of strontium and titanium is approximately 1:1. The partial pressure of oxygen is initially set at a minimum value to grow stoichiometric strontium titanate at a growth rate of about 0.3-0.5 nm per minute. After initiating growth of the strontium titanate, the partial pressure of oxygen is increased above the initial minimum value. The overpressure of oxygen causes the growth of an amorphous silicon oxide layer at the interface between the underlying substrate and the growing strontium titanate layer. The growth of the silicon oxide layer results from the diffusion of oxygen through the growing strontium titanate layer to the interface where the oxygen reacts with silicon at the surface of the underlying substrate. The strontium titanate grows as an ordered (100) monocrystal with the (100) crystalline orientation rotated by 45° with respect to the underlying substrate. Strain that otherwise might exist in the strontium titanate layer because of the small mismatch in lattice constant between the silicon substrate and the growing crystal is relieved in the amorphous silicon oxide intermediate layer.
- After the strontium titanate layer has been grown to the desired thickness, the monocrystalline strontium titanate is capped by a template layer that is conducive to the subsequent growth of an epitaxial layer of a desired monocrystalline material. For example, for the subsequent growth of a monocrystalline compound semiconductor material layer of gallium arsenide, the MBE growth of the strontium titanate monocrystalline layer can be capped by terminating the growth with1-2 monolayers of titanium, 1-2 monolayers of titanium-oxygen or with 1-2 monolayers of strontiumoxygen. Following the formation of this capping layer, arsenic is deposited to form a Ti—As bond, a Ti—O—As bond or a Sr—O—As. Any of these form an appropriate template for deposition and formation of a gallium arsenide monocrystalline layer. Following the formation of the template, gallium is subsequently introduced to the reaction with the arsenic and gallium arsenide forms. Alternatively, gallium can be deposited on the capping layer to form a Sr—O—Ga bond, and arsenic is subsequently introduced with the gallium to form the GaAs.
- FIG. 5 is a high resolution Transmission Electron Micrograph (TEM) of semiconductor material manufactured in accordance with one embodiment of the present invention. Single crystal SrTiO3
accommodating buffer layer 24 was grown epitaxially onsilicon substrate 22. During this growth process, amorphousinterfacial layer 28 is formed which relieves strain due to lattice mismatch. GaAscompound semiconductor layer 26 was then grown epitaxially usingtemplate layer 30. - FIG. 6 illustrates an x-ray diffraction spectrum taken on a structure including a GaAs
monocrystalline layer 26 comprising GaAs grown onsilicon substrate 22 usingaccommodating buffer layer 24. The peaks in the spectrum indicate that both theaccommodating buffer layer 24 and GaAscompound semiconductor layer 26 are single crystal and (100) orientated. - The structure illustrated in FIG. 2 can be formed by the process discussed above with the addition of an additional buffer layer deposition step. The
additional buffer layer 32 is formed overlying the template layer before the deposition of the monocrystalline material layer. If the buffer layer is a monocrystalline material comprising a compound semiconductor superlattice, such a superlattice can be deposited, by MBE for example, on the template described above. If instead the buffer layer is a monocrystalline material layer comprising a layer of germanium, the process above is modified to cap the strontium titanate monocrystalline layer with a final layer of either strontium or titanium and then by depositing germanium to react with the strontium or titanium. The germanium buffer layer can then be deposited directly on this template. -
Structure 34, illustrated in FIG. 3, may be formed by growing an accommodating buffer layer, forming an amorphous oxide layer oversubstrate 22, and growingsemiconductor layer 38 over the accommodating buffer layer, as described above. The accommodating buffer layer and the amorphous oxide layer are then exposed to an anneal process sufficient to change the crystalline structure of the accommodating buffer layer from monocrystalline to amorphous, thereby forming an amorphous layer such that the combination of the amorphous oxide layer and the now amorphous accommodating buffer layer form a singleamorphous oxide layer 36.Layer 26 is then subsequently grown overlayer 38. Alternatively, the anneal process may be carried out subsequent to growth oflayer 26. - In accordance with one aspect of this embodiment,
layer 36 is formed by exposingsubstrate 22, the accommodating buffer layer, the amorphous oxide layer, andmonocrystalline layer 38 to a rapid thermal anneal process with a peak temperature of about 700° C. to about 1000° C. and a process time of about 5 seconds to about 10 minutes. However, other suitable anneal processes may be employed to convert the accommodating buffer layer to an amorphous layer in accordance with the present invention. For example, laser annealing, electron beam annealing, or “conventional” thermal annealing processes (in the proper environment) may be used to formlayer 36. When conventional thermal annealing is employed to formlayer 36, an overpressure of one or more constituents oflayer 30 may be required to prevent degradation oflayer 38 during the anneal process. For example, whenlayer 38 includes GaAs, the anneal environment preferably includes an overpressure of arsenic to mitigate degradation oflayer 38. - As noted above,
layer 38 ofstructure 34 may include any materials suitable for either oflayers layer layer 38. - FIG. 7 is a high resolution TEM of semiconductor material manufactured in accordance with the embodiment of the invention illustrated in FIG. 3. In accordance with this embodiment, a single crystal SrTiO3 accommodating buffer layer was grown epitaxially on
silicon substrate 22. During this growth process, an amorphous interfacial layer forms as described above. Next, additionalmonocrystalline layer 38 comprising a compound semiconductor layer of GaAs is formed above the accommodating buffer layer and the accommodating buffer layer is exposed to an anneal process to formamorphous oxide layer 36. - FIG. 8 illustrates an x-ray diffraction spectrum taken on a structure including additional
monocrystalline layer 38 comprising a GaAs compound semiconductor layer andamorphous oxide layer 36 formed onsilicon substrate 22. The peaks in the spectrum indicate that GaAscompound semiconductor layer 38 is single crystal and (100) orientated and the lack of peaks around 40 to 50 degrees indicates thatlayer 36 is amorphous. - The process described above illustrates a process for forming a semiconductor structure including a silicon substrate, an overlying oxide layer, and a monocrystalline material layer comprising a gallium arsenide compound semiconductor layer by the process of molecular beam epitaxy. The process can also be carried out by the process of chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), migration enhanced epitaxy (MEE), atomic layer epitaxy (ALE), physical vapor deposition (PVD), chemical solution deposition (CSD), pulsed laser deposition (PLD), or the like. Further, by a similar process, other monocrystalline accommodating buffer layers such as alkaline earth metal titanates, zirconates, hafnates, tantalates, vanadates, ruthenates, and niobates, alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide can also be grown. Further, by a similar process such as MBE, other monocrystalline material layers comprising other III-V and II-VI monocrystalline compound semiconductors, semiconductors, metals and non-metals can be deposited overlying the monocrystalline oxide accommodating buffer layer.
- Each of the variations of monocrystalline material layer and monocrystalline oxide accommodating buffer layer uses an appropriate template for initiating the growth of the monocrystalline material layer. For example, if the accommodating buffer layer is an alkaline earth metal zirconate, the oxide can be capped by a thin layer of zirconium. The deposition of zirconium can be followed by the deposition of arsenic or phosphorus to react with the zirconium as a precursor to depositing indium gallium arsenide, indium aluminum arsenide, or indium phosphide respectively. Similarly, if the monocrystalline oxide accommodating buffer layer is an alkaline earth metal hafnate, the oxide layer can be capped by a thin layer of hafnium. The deposition of hafnium is followed by the deposition of arsenic or phosphorous to react with the hafnium as a precursor to the growth of an indium gallium arsenide, indium aluminum arsenide, or indium phosphide layer, respectively. In a similar manner, strontium titanate can be capped with a layer of strontium or strontium and oxygen and barium titanate can be capped with a layer of barium or barium and oxygen. Each of these depositions can be followed by the deposition of arsenic or phosphorus to react with the capping material to form a template for the deposition of a monocrystalline material layer comprising compound semiconductors such as indium gallium arsenide, indium aluminum arsenide, or indium phosphide.
- The formation of a device structure in accordance with another embodiment of the invention is illustrated schematically in cross-section in FIGS.9-12. Like the previously described embodiments referred to in FIGS. 1-3, this embodiment of the invention involves the process of forming a compliant substrate utilizing the epitaxial growth of single crystal oxides, such as the formation of
accommodating buffer layer 24 previously described with reference to FIGS. 1 and 2 andamorphous layer 36 previously described with reference to FIG. 3, and the formation of atemplate layer 30. However, the embodiment illustrated in FIGS. 9-12 utilizes a template that includes a surfactant to facilitate layer-by-layer monocrystalline material growth. - Turning now to FIG. 9, an amorphous
intermediate layer 58 is grown onsubstrate 52 at the interface betweensubstrate 52 and a growingaccommodating buffer layer 54, which is preferably a monocrystalline crystal oxide layer, by the oxidation ofsubstrate 52 during the growth oflayer 54.Layer 54 is preferably a monocrystalline oxide material such as a monocrystalline layer of SrzBa1−zTiO3 where z ranges from 0 to 1. However,layer 54 may also comprise any of those compounds previously described withreference layer 24 in FIGS. 1-2 and any of those compounds previously described with reference tolayer 36 in FIG. 3 which is formed fromlayers -
Layer 54 is grown with a strontium (Sr) terminated surface represented in FIG. 9 by hatchedline 55 which is followed by the addition of atemplate layer 60 which includes asurfactant layer 61 andcapping layer 63 as illustrated in FIGS. 10 and 11.Surfactant layer 61 may comprise, but is not limited to, elements such as Al, In and Ga, but will be dependent upon the composition oflayer 54 and the overlying layer of monocrystalline material for optimal results. In one exemplary embodiment, aluminum (Al) is used forsurfactant layer 61 and functions to modify the surface and surface energy oflayer 54. Preferably,surfactant layer 61 is epitaxially grown, to a thickness of one to two monolayers, overlayer 54 as illustrated in FIG. 10 by way of molecular beam epitaxy (MBE), although other epitaxial processes may also be performed including chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), migration enhanced epitaxy (MEE), atomic layer epitaxy (ALE), physical vapor deposition (PVD), chemical solution deposition (CSD), pulsed laser deposition (PLD), or the like. -
Surfactant layer 61 is then exposed to a Group V element such as arsenic, for example, to form cappinglayer 63 as illustrated in FIG. 11.Surfactant layer 61 may be exposed to a number of materials to create cappinglayer 63 such as elements which include, but are not limited to, As, P, Sb andN. Surfactant layer 61 andcapping layer 63 combine to formtemplate layer 60. -
Monocrystalline material layer 66, which in this example is a compound semiconductor such as GaAs, is then deposited via MBE, CVD, MOCVD, MEE, ALE, PVD, CSD, PLD, and the like to form the final structure illustrated in FIG. 12. - FIGS.13-16 illustrate possible molecular bond structures for a specific example of a compound semiconductor structure formed in accordance with the embodiment of the invention illustrated in FIGS. 9-12. More specifically, FIGS. 13-16 illustrate the growth of GaAs (layer 66) on the strontium terminated surface of a strontium titanate monocrystalline oxide (layer 54) using a surfactant containing template (layer 60).
- The growth of a
monocrystalline material layer 66 such as GaAs on anaccommodating buffer layer 54 such as a strontium titanium oxide overamorphous interface layer 58 andsubstrate layer 52, both of which may comprise materials previously described with reference tolayers - δSTO>(δINTδGaAS
- where the surface energy of the
monocrystalline oxide layer 54 must be greater than the surface energy of theamorphous interface layer 58 added to the surface energy of theGaAs layer 66. Since it is impracticable to satisfy this equation, a surfactant containing template was used, as described above with reference to FIGS. 10-12, to increase the surface energy of themonocrystalline oxide layer 54 and also to shift the crystalline structure of the template to a diamond-like structure that is in compliance with the original GaAs layer. - FIG. 13 illustrates the molecular bond structure of a strontium terminated surface of a strontium titanate monocrystalline oxide layer. An aluminum surfactant layer is deposited on top of the strontium terminated surface and bonds with that surface as illustrated in FIG. 14, which reacts to form a capping layer comprising a monolayer of Al2Sr having the molecular bond structure illustrated in FIG. 14 which forms a diamond-like structure with an sp3 hybrid terminated surface that is compliant with compound semiconductors such as GaAs. The structure is then exposed to As to form a layer of AlAs as shown in FIG. 15. GaAs is then deposited to complete the molecular bond structure illustrated in FIG. 16 which has been obtained by 2D growth. The GaAs can be grown to any thickness for forming other semiconductor structures, devices, or integrated circuits. Alkaline earth metals such as those in Group IIA are those elements preferably used to form the capping surface of the
monocrystalline oxide layer 54 because they are capable of forming a desired molecular structure with aluminum. - In this embodiment, a surfactant containing template layer aids in the formation of a compliant substrate for the monolithic integration of various material layers including those comprised of Group III-V compounds to form high quality semiconductor structures, devices and integrated circuits. For example, a surfactant containing template may be used for the monolithic integration of a monocrystalline material layer such as a layer comprising Germanium (Ge), for example, to form high efficiency photocells.
- Turning now to FIGS.17-20, the formation of a device structure in accordance with still another embodiment of the invention is illustrated in cross-section. This embodiment utilizes the formation of a compliant substrate which relies on the epitaxial growth of single crystal oxides on silicon followed by the epitaxial growth of single crystal silicon onto the oxide.
- An
accommodating buffer layer 74 such as a monocrystalline oxide layer is first grown on asubstrate layer 72, such as silicon, with anamorphous interface layer 78 as illustrated in FIG. 17.Monocrystalline oxide layer 74 may be comprised of any of those materials previously discussed with reference tolayer 24 in FIGS. 1 and 2, whileamorphous interface layer 78 is preferably comprised of any of those materials previously described with reference to thelayer 28 illustrated in FIGS. 1 and 2.Substrate 72, although preferably silicon, may also comprise any of those materials previously described with reference tosubstrate 22 in FIGS. 1-3. - Next, a
silicon layer 81 is deposited overmonocrystalline oxide layer 74 via MBE, CVD, MOCVD, MEE, ALE, PVD, CSD, PLD, and the like as illustrated in FIG. 18 with a thickness of a few hundred Angstroms but preferably with a thickness of about 50 Angstroms.Monocrystalline oxide layer 74 preferably has a thickness of about 20 to 100 Angstroms. - Rapid thermal annealing is then conducted in the presence of a carbon source such as acetylene or methane, for example at a temperature within a range of about 800° C. to 1000° C. to form capping
layer 82 and silicateamorphous layer 86. However, other suitable carbon sources may be used as long as the rapid thermal annealing step functions to amorphize themonocrystalline oxide layer 74 into a silicateamorphous layer 86 and carbonize thetop silicon layer 81 to form cappinglayer 82 which in this example would be a silicon carbide (SiC) layer as illustrated in FIG. 19. The formation ofamorphous layer 86 is similar to the formation oflayer 36 illustrated in FIG. 3 and may comprise any of those materials described with reference tolayer 36 in FIG. 3 but the preferable material will be dependent upon thecapping layer 82 used forsilicon layer 81. - Finally, a
compound semiconductor layer 96, such as gallium nitride (GaN) is grown over the SiC surface by way of MBE, CVD, MOCVD, MEE, ALE, PVD, CSD, PLD, or the like to form a high quality compound semiconductor material for device formation. More specifically, the deposition of GaN and GaN based systems such as GaInN and AlGaN will result in the formation of dislocation nets confined at the silicon/amorphous region. The resulting nitride containing compound semiconductor material may comprise elements from groups III, IV and V of the periodic table and is defect free. - Although GaN has been grown on SiC substrate in the past, this embodiment of the invention possesses a one step formation of the compliant substrate containing a SiC top surface and an amorphous layer on a Si surface. More specifically, this embodiment of the invention uses an intermediate single crystal oxide layer that is amorphosized to form a silicate layer which adsorbs the strain between the layers. Moreover, unlike past use of a SiC substrate, this embodiment of the invention is not limited by wafer size which is usually less than 50 mm in diameter for prior art SiC substrates.
- The monolithic integration of nitride containing semiconductor compounds containing group III-V nitrides and silicon devices can be used for high temperature RF applications and optoelectronics. GaN systems have particular use in the photonic industry for the blue/green and UV light sources and detection. High brightness light emitting diodes (LEDs) and lasers may also be formed within the GaN system.
- FIGS.21-23 schematically illustrate, in cross-section, the formation of another embodiment of a device structure in accordance with the invention. This embodiment includes a compliant layer that functions as a transition layer that uses clathrate or Zintl type bonding. More specifically, this embodiment utilizes an intermetallic template layer to reduce the surface energy of the interface between material layers thereby allowing for two dimensional layer by layer growth.
- The structure illustrated in FIG. 21 includes a
monocrystalline substrate 102, anamorphous interface layer 108 and anaccommodating buffer layer 104.Amorphous interface layer 108 is formed onsubstrate 102 at the interface betweensubstrate 102 andaccommodating buffer layer 104 as previously described with reference to FIGS. 1 and 2.Amorphous interface layer 108 may comprise any of those materials previously described with reference toamorphous interface layer 28 in FIGS. 1 and 2.Substrate 102 is preferably silicon but may also comprise any of those materials previously described with reference tosubstrate 22 in FIGS. 1-3. - A
template layer 130 is deposited overaccommodating buffer layer 104 as illustrated in FIG. 22 and preferably comprises a thin layer of Zintl type phase material composed of metals and metalloids having a great deal of ionic character. As in previously described embodiments,template layer 130 is deposited by way of MBE, CVD, MOCVD, MEE, ALE, PVD, CSD, PLD, or the like to achieve a thickness of one monolayer.Template layer 130 functions as a “soft” layer with non-directional bonding but high crystallinity which absorbs stress build up between layers having lattice mismatch. Materials fortemplate 130 may include, but are not limited to, materials containing Si, Ga, In, and Sb such as, for example, AlSr2, (MgCaYb)Ga2, (Ca,Sr,Eu,Yb)In2, BaGe2As, and SrSn2As2 Amonocrystalline material layer 126 is epitaxially grown overtemplate layer 130 to achieve the final structure illustrated in FIG. 23. As a specific example, an SrAl2 layer may be used astemplate layer 130 and an appropriatemonocrystalline material layer 126 such as a compound semiconductor material GaAs is grown over the SrAl2. The Al—Ti (from the accommodating buffer layer of layer of SrzBa1−zTiO3 where z ranges from 0 to 1) bond is mostly metallic while the Al—As (from the GaAs layer) bond is weakly covalent. The Sr participates in two distinct types of bonding with part of its electric charge going to the oxygen atoms in the loweraccommodating buffer layer 104 comprising SrzBa1−zTiO3 to participate in ionic bonding and the other part of its valence charge being donated to Al in a way that is typically carried out with Zintl phase materials. The amount of the charge transfer depends on the relative electronegativity of elements comprising thetemplate layer 130 as well as on the interatomic distance. In this example, Al assumes an sp3 hybridization and can readily form bonds withmonocrystalline material layer 126, which in this example, comprises compound semiconductor material GaAs. - The compliant substrate produced by use of the Zintl type template layer used in this embodiment can absorb a large strain without a significant energy cost. In the above example, the bond strength of the Al is adjusted by changing the volume of the SrAl2 layer thereby making the device tunable for specific applications which include the monolithic integration of III-V and Si devices and the monolithic integration of high-k dielectric materials for CMOS technology.
- Clearly, those embodiments specifically describing structures having compound semiconductor portions and Group IV semiconductor portions, are meant to illustrate embodiments of the present invention and not limit the present invention. There are a multiplicity of other combinations and other embodiments of the present invention. For example, the present invention includes structures and methods for fabricating material layers which form semiconductor structures, devices and integrated circuits including other layers such as metal and non-metal layers. More specifically, the invention includes structures and methods for forming a compliant substrate which is used in the fabrication of semiconductor structures, devices and integrated circuits and the material layers suitable for fabricating those structures, devices, and integrated circuits. By using embodiments of the present invention, it is now simpler to integrate devices that include monocrystalline layers comprising semiconductor and compound semiconductor materials as well as other material layers that are used to form those devices with other components that work better or are easily and/or inexpensively formed within semiconductor or compound semiconductor materials. This allows a device to be shrunk, the manufacturing costs to decrease, and yield and reliability to increase.
- In accordance with one embodiment of this invention, a monocrystalline semiconductor or compound semiconductor wafer can be used in forming monocrystalline material layers over the wafer. In this manner, the wafer is essentially a “handle” wafer used during the fabrication of semiconductor electrical components within a monocrystalline layer overlying the wafer. Therefore, electrical components can be formed within semiconductor materials over a wafer of at least approximately 200 millimeters in diameter and possibly at least approximately 300 millimeters.
- By the use of this type of substrate, a relatively inexpensive “handle” wafer overcomes the fragile nature of compound semiconductor or other monocrystalline material wafers by placing them over a relatively more durable and easy to fabricate base material. Therefore, an integrated circuit can be formed such that all electrical components, and particularly all active electronic devices, can be formed within or using the monocrystalline material layer even though the substrate itself may include a monocrystalline semiconductor material. Fabrication costs for compound semiconductor devices and other devices employing non-silicon monocrystalline materials should decrease because larger substrates can be processed more economically and more readily compared to the relatively smaller and more fragile substrates (e.g. conventional compound semiconductor wafers).
- FIG. 24 illustrates schematically, in cross section, a
device structure 50 in accordance with a further embodiment.Device structure 50 includes amonocrystalline semiconductor substrate 52, preferably a monocrystalline silicon wafer.Monocrystalline semiconductor substrate 52 includes two regions, 53 and 57. An electrical semiconductor component generally indicated by the dashedline 56 is formed, at least partially, in region 53.Electrical component 56 can be a resistor, a capacitor, an active semiconductor component such as a diode or a transistor or an integrated circuit such as a CMOS integrated circuit. For example,electrical semiconductor component 56 can be a CMOS integrated circuit configured to perform digital signal processing or another function for which silicon integrated circuits are well suited. The electrical semiconductor component in region 53 can be formed by conventional semiconductor processing as well known and widely practiced in the semiconductor industry. A layer of insulatingmaterial 59 such as a layer of silicon dioxide or the like may overlieelectrical semiconductor component 56. - Insulating
material 59 and any other layers that may have been formed or deposited during the processing ofsemiconductor component 56 in region 53 are removed from the surface of region 57 to provide a bare silicon surface in that region. As is well known, bare silicon surfaces are highly reactive and a native silicon oxide layer can quickly form on the bare surface. A layer of barium or barium and oxygen is deposited onto the native oxide layer on the surface of region 57 and is reacted with the oxidized surface to form a first template layer (not shown). In accordance with one embodiment, a monocrystalline oxide layer is formed overlying the template layer by a process of molecular beam epitaxy. Reactants including barium, titanium and oxygen are deposited onto the template layer to form the monocrystalline oxide layer. Initially during the deposition the partial pressure of oxygen is kept near the minimum necessary to fully react with the barium and titanium to form monocrystalline barium titanate layer. The partial pressure of oxygen is then increased to provide an overpressure of oxygen and to allow oxygen to diffuse through the growing monocrystalline oxide layer. The oxygen diffusing through the barium titanate reacts with silicon at the surface of region 57 to form an amorphous layer ofsilicon oxide 62 on second region 57 and at the interface betweensilicon substrate 52 and themonocrystalline oxide layer 65.Layers - In accordance with an embodiment, the step of depositing the
monocrystalline oxide layer 65 is terminated by depositing asecond template layer 64, which can be 1-10 monolayers of titanium, barium, barium and oxygen, or titanium and oxygen. Alayer 66 of a monocrystalline compound semiconductor material is then deposited overlyingsecond template layer 64 by a process of molecular beam epitaxy. The deposition oflayer 66 is initiated by depositing a layer of arsenic ontotemplate 64. This initial step is followed by depositing gallium and arsenic to formmonocrystalline gallium arsenide 66. Alternatively, strontium can be substituted for barium in the above example. - In accordance with a further embodiment, a semiconductor component, generally indicated by a dashed
line 68 is formed incompound semiconductor layer 66.Semiconductor component 68 can be formed by processing steps conventionally used in the fabrication of gallium arsenide or other III-V compound semiconductor material devices.Semiconductor component 68 can be any active or passive component, and preferably is a semiconductor laser, light emitting diode, photodetector, heterojunction bipolar transistor (HBT), high frequency MESFET, or other component that utilizes and takes advantage of the physical properties of compound semiconductor materials. A metallic conductor schematically indicated by theline 70 can be formed toelectrically couple device 68 anddevice 56, thus implementing an integrated device that includes at least one component formed insilicon substrate 52 and one device formed in monocrystalline compoundsemiconductor material layer 66. Althoughillustrative structure 50 has been described as a structure formed on asilicon substrate 52 and having a barium (or strontium)titanate layer 65 and agallium arsenide layer 66, similar devices can be fabricated using other substrates, monocrystalline oxide layers and other compound semiconductor layers as described elsewhere in this disclosure. - FIG. 25 illustrates a
semiconductor structure 71 in accordance with a further embodiment.Structure 71 includes amonocrystalline semiconductor substrate 73 such as a monocrystalline silicon wafer that includes a region 75 and aregion 76. An electrical component schematically illustrated by the dashedline 79 is formed in region 75 using conventional silicon device processing techniques commonly used in the semiconductor industry. Using process steps similar to those described above, amonocrystalline oxide layer 80 and an intermediate amorphoussilicon oxide layer 83 are formedoverlying region 76 ofsubstrate 73. Atemplate layer 84 and subsequently amonocrystalline semiconductor layer 87 are formed overlyingmonocrystalline oxide layer 80. In accordance with a further embodiment, an additionalmonocrystalline oxide layer 88 is formedoverlying layer 87 by process steps similar to those used to formlayer 80, and an additionalmonocrystalline semiconductor layer 90 is formed overlyingmonocrystalline oxide layer 88 by process steps similar to those used to formlayer 87. In accordance with one embodiment, at least one oflayers Layers - A semiconductor component generally indicated by a dashed
line 92 is formed at least partially inmonocrystalline semiconductor layer 87. In accordance with one embodiment,semiconductor component 92 may include a field effect transistor having a gate dielectric formed, in part, bymonocrystalline oxide layer 88. In addition,monocrystalline semiconductor layer 90 can be used to implement the gate electrode of that field effect transistor. In accordance with one embodiment,monocrystalline semiconductor layer 87 is formed from a group III-V compound andsemiconductor component 92 is a radio frequency amplifier that takes advantage of the high mobility characteristic of group III-V component materials. In accordance with yet a further embodiment, an electrical interconnection schematically illustrated by theline 94electrically interconnects component 79 andcomponent 92.Structure 71 thus integrates components that take advantage of the unique properties of the two monocrystalline semiconductor materials. - Attention is now directed to a method for forming exemplary portions of illustrative composite semiconductor structures or composite integrated circuits like50 or 71. In particular, the illustrative composite semiconductor structure or
integrated circuit 103 shown in FIGS. 26-30 includes acompound semiconductor portion 1022, abipolar portion 1024, and aMOS portion 1026. In FIG. 26, a p-type doped,monocrystalline silicon substrate 110 is provided having acompound semiconductor portion 1022, abipolar portion 1024, and anMOS portion 1026. Withinbipolar portion 1024, themonocrystalline silicon substrate 110 is doped to form an N+ buriedregion 1102. A lightly p-type doped epitaxialmonocrystalline silicon layer 1104 is then formed over the buriedregion 1102 and thesubstrate 110. A doping step is then performed to create a lightly n-type dopeddrift region 1117 above the N+ buriedregion 1102. The doping step converts the dopant type of the lightly p-type epitaxial layer within a section of thebipolar region 1024 to a lightly n-type monocrystalline silicon region. Afield isolation region 1106 is then formed between and around thebipolar portion 1024 and theMOS portion 1026. Agate dielectric layer 1110 is formed over a portion of theepitaxial layer 1104 withinMOS portion 1026, and thegate electrode 1112 is then formed over thegate dielectric layer 1110.Sidewall spacers 1115 are formed along vertical sides of thegate electrode 1112 andgate dielectric layer 1110. - A p-type dopant is introduced into the
drift region 1117 to form an active orintrinsic base region 1114. An n-type,deep collector region 1108 is then formed within thebipolar portion 1024 to allow electrical connection to the buriedregion 1102. Selective n-type doping is performed to form N+ dopedregions 1116 and theemitter region 1120. N+ dopedregions 1116 are formed withinlayer 1104 along adjacent sides of thegate electrode 1112 and are source, drain, or source/drain regions for the MOS transistor. The N+ dopedregions 1116 andemitter region 1120 have a doping concentration of at least 1E19 atoms per cubic centimeter to allow ohmic contacts to be formed. A p-type doped region is formed to create the inactive orextrinsic base region 1118 which is a P+ doped region (doping concentration of at least 1E19 atoms per cubic centimeter). - In the embodiment described, several processing steps have been performed but are not illustrated or further described, such as the formation of well regions, threshold adjusting implants, channel punchthrough prevention implants, field punchthrough prevention implants, as well as a variety of masking layers. The formation of the device up to this point in the process is performed using conventional steps. As illustrated, a standard N-channel MOS transistor has been formed within the
MOS region 1026, and a vertical NPN bipolar transistor has been formed within thebipolar portion 1024. Although illustrated with a NPN bipolar transistor and a N-channel MOS transistor, device structures and circuits in accordance with various embodiments may additionally or alternatively include other electronic devices formed using the silicon substrate. As of this point, no circuitry has been formed within thecompound semiconductor portion 1022. - After the silicon devices are formed in
regions protective layer 1122 is formed overlying devices inregions regions region 1022.Layer 1122 may be formed of, for example, an insulating material such as silicon oxide or silicon nitride. - All of the layers that have been formed during the processing of the bipolar and MOS portions of the integrated circuit, except for
epitaxial layer 1104 but includingprotective layer 1122, are now removed from the surface ofcompound semiconductor portion 1022. A bare silicon surface is thus provided for the subsequent processing of this portion, for example in the manner set forth above. - An
accommodating buffer layer 124 is then formed over thesubstrate 110 as illustrated in FIG. 27. The accommodating buffer layer will form as a monocrystalline layer over the properly prepared (i.e., having the appropriate template layer) bare silicon surface inportion 1022. The portion oflayer 124 that forms overportions accommodating buffer layer 124 typically is a monocrystalline metal oxide or nitride layer and typically has a thickness in a range of approximately 2-100 nanometers. In one particular embodiment, the accommodating buffer layer is approximately 5-15 nm thick. During the formation of the accommodating buffer layer, an amorphousintermediate layer 122 is formed along the uppermost silicon surfaces of theintegrated circuit 103. This amorphousintermediate layer 122 typically includes an oxide of silicon and has a thickness and range of approximately 1-5 nm. In one particular embodiment, the thickness is approximately 2 nm. Following the formation of theaccommodating buffer layer 124 and the amorphousintermediate layer 122, atemplate layer 125 is then formed and has a thickness in a range of approximately one to ten monolayers of a material. In one particular embodiment, the material includes titanium-arsenic, strontium-oxygen-arsenic, or other similar materials as previously described with respect to FIGS. 1-5. - A monocrystalline
compound semiconductor layer 132 is then epitaxially grown overlying the monocrystalline portion of accommodating buffer layer 124 (as shown in FIG. 28. The portion oflayer 132 that is grown over portions oflayer 124 that are not monocrystalline may be polycrystalline or amorphous. The compound semiconductor layer can be formed by a number of methods and typically includes a material such as gallium arsenide, aluminum gallium arsenide, indium phosphide, or other compound semiconductor materials as previously mentioned. The thickness of the layer is in a range of approximately 1-5,000 nm, and more preferably 100-2000 nm. Furthermore, additional monocrystalline layers may be formed abovelayer 132, as discussed in more detail below in connection with FIGS. 31-32. - In this particular embodiment, each of the elements within the template layer are also present in the
accommodating buffer layer 124, the monocrystallinecompound semiconductor material 132, or both. Therefore, the delineation between thetemplate layer 125 and its two immediately adjacent layers disappears during processing. Therefore, when a transmission electron microscopy (TEM) photograph is taken, an interface between theaccommodating buffer layer 124 and the monocrystallinecompound semiconductor layer 132 is seen. - After at least a portion of
layer 132 is formed inregion 1022, layers 122 and 124 may be subject to an annealing process as described above in connection with FIG. 3 to form a single amorphous accommodating layer. If only a portion oflayer 132 is formed prior to the anneal process, the remaining portion may be deposited ontostructure 103 prior to further processing. - At this point in time, sections of the
compound semiconductor layer 132 and the accommodating buffer layer 124 (or of the amorphous accommodating layer if the annealing process described above has been carried out) are removed from portions overlying thebipolar portion 1024 and theMOS portion 1026 as shown in FIG. 29. After the section of the compound semiconductor layer and theaccommodating buffer layer 124 are removed, an insulatinglayer 142 is formed overprotective layer 1122. The insulatinglayer 142 can include a number of materials such as oxides, nitrides, oxynitrides, low-k dielectrics, or the like. As used herein, low-k is a material having a dielectric constant no higher than approximately 3.5. After the insulatinglayer 142 has been deposited, it is then polished or etched to remove portions of the insulatinglayer 142 that overlie monocrystallinecompound semiconductor layer 132. - A
transistor 144 is then formed within the monocrystallinecompound semiconductor portion 1022. Agate electrode 148 is then formed on the monocrystallinecompound semiconductor layer 132.Doped regions 146 are then formed within the monocrystallinecompound semiconductor layer 132. In this embodiment, thetransistor 144 is a metal-semiconductor field-effect transistor (MESFET). If the MESFET is an n-type MESFET, the dopedregions 146 and at least a portion of monocrystallinecompound semiconductor layer 132 are also n-type doped. If a p-type MESFET were to be formed, then thedoped regions 146 and at least a portion of monocrystallinecompound semiconductor layer 132 would have just the opposite doping type. The heavier doped (N+)regions 146 allow ohmic contacts to be made to the monocrystallinecompound semiconductor layer 132. At this point in time, the active devices within the integrated circuit have been formed. Although not illustrated in the drawing figures, additional processing steps such as formation of well regions, threshold adjusting implants, channel punchthrough prevention implants, field punchthrough prevention implants, and the like may be performed in accordance with the present invention. This particular embodiment includes an n-type MESFET, a vertical NPN bipolar transistor, and a planar n-channel MOS transistor. Many other types of transistors, including P-channel MOS transistors, p-type vertical bipolar transistors, p-type MESFETs, and combinations of vertical and planar transistors, can be used. Also, other electrical components, such as resistors, capacitors, diodes, and the like, may be formed in one or more of theportions - Processing continues to form a substantially completed
integrated circuit 103 as illustrated in FIG. 30. An insulatinglayer 152 is formed over thesubstrate 110. The insulatinglayer 152 may include an etch-stop or polish-stop region that is not illustrated in FIG. 30. A second insulatinglayer 154 is then formed over the first insulatinglayer 152. Portions oflayers layer 154 to provide the lateral connections between the contacts. As illustrated in FIG. 30,interconnect 1562 connects a source or drain region of the n-type MESFET withinportion 1022 to thedeep collector region 1108 of the NPN transistor within thebipolar portion 1024. Theemitter region 1120 of the NPN transistor is connected to one of the dopedregions 1116 of the n-channel MOS transistor within theMOS portion 1026. The otherdoped region 1116 is electrically connected to other portions of the integrated circuit that are not shown. Similar electrical connections are also formed to coupleregions - A
passivation layer 156 is formed over theinterconnects layer 154. Other electrical connections are made to the transistors as illustrated as well as to other electrical or electronic components within theintegrated circuit 103 but are not illustrated in the FIGS. Further, additional insulating layers and interconnects may be formed as necessary to form the proper interconnections between the various components within theintegrated circuit 103. - As can be seen from the previous embodiment, active devices for both compound semiconductor and Group IV semiconductor materials can be integrated into a single integrated circuit. Because there is some difficulty in incorporating both bipolar transistors and MOS transistors within a same integrated circuit, it may be possible to move some of the components within
bipolar portion 1024 into thecompound semiconductor portion 1022 or theMOS portion 1026. Therefore, the requirement of special fabricating steps solely used for making a bipolar transistor can be eliminated. Therefore, there would only be a compound semiconductor portion and a MOS portion to the integrated circuit. - In still another embodiment, an integrated circuit can be formed such that it includes an optical laser in a compound semiconductor portion and an optical interconnect (waveguide) to a MOS transistor within a Group IV semiconductor region of the same integrated circuit. FIGS.31-37 include illustrations of one embodiment.
- FIG. 31 includes an illustration of a cross-section view of a portion of an
integrated circuit 160 that includes amonocrystalline silicon wafer 161. An amorphousintermediate layer 162 and anaccommodating buffer layer 164, similar to those previously described, have been formed overwafer 161.Layers lower mirror layer 166 includes alternating layers of compound semiconductor materials. For example, the first, third, and fifth films within the optical laser may include a material such as gallium arsenide, and the second, fourth, and sixth films within thelower mirror layer 166 may include aluminum gallium arsenide or vice versa.Layer 168 includes the active region that will be used for photon generation.Upper mirror layer 170 is formed in a similar manner to thelower mirror layer 166 and includes alternating films of compound semiconductor materials. In one particular embodiment, theupper mirror layer 170 may be p-type doped compound semiconductor materials, and thelower mirror layer 166 may be n-type doped compound semiconductor materials. - Another
accommodating buffer layer 172, similar to theaccommodating buffer layer 164, is formed over theupper mirror layer 170. In an alternative embodiment, the accommodating buffer layers 164 and 172 may include different materials. However, their function is essentially the same in that each is used for making a transition between a compound semiconductor layer and a monocrystalline Group IV semiconductor layer.Layer 172 may be subject to an annealing process as described above in connection with FIG. 3 to form an amorphous accommodating layer. A monocrystalline GroupIV semiconductor layer 174 is formed over theaccommodating buffer layer 172. In one particular embodiment, the monocrystalline GroupIV semiconductor layer 174 includes germanium, silicon germanium, silicon germanium carbide, or the like. - In FIG. 32, the MOS portion is processed to form electrical components within this upper monocrystalline Group
IV semiconductor layer 174. As illustrated in FIG. 32, afield isolation region 171 is formed from a portion oflayer 174. Agate dielectric layer 173 is formed over thelayer 174, and agate electrode 175 is formed over thegate dielectric layer 173.Doped regions 177 are source, drain, or source/drain regions for thetransistor 181, as shown.Sidewall spacers 179 are formed adjacent to the vertical sides of thegate electrode 175. Other components can be made within at least a part oflayer 174. These other components include other transistors (n-channel or p-channel), capacitors, transistors, diodes, and the like. - A monocrystalline Group IV semiconductor layer is epitaxially grown over one of the doped
regions 177. Anupper portion 184 is P+ doped, and alower portion 182 remains substantially intrinsic (undoped) as illustrated in FIG. 32. The layer can be formed using a selective epitaxial process. In one embodiment, an insulating layer (not shown) is formed over thetransistor 181 and thefield isolation region 171. The insulating layer is patterned to define an opening that exposes one of the dopedregions 177. At least initially, the selective epitaxial layer is formed without dopants. The entire selective epitaxial layer may be intrinsic, or a p-type dopant can be added near the end of the formation of the selective epitaxial layer. If the selective epitaxial layer is intrinsic, as formed, a doping step may be formed by implantation or by furnace doping. Regardless how the P+upper portion 184 is formed, the insulating layer is then removed to form the resulting structure shown in FIG. 32. - The next set of steps is performed to define the
optical laser 180 as illustrated in FIG. 33. Thefield isolation region 171 and theaccommodating buffer layer 172 are removed over the compound semiconductor portion of the integrated circuit. Additional steps are performed to define theupper mirror layer 170 andactive layer 168 of theoptical laser 180. The sides of theupper mirror layer 170 andactive layer 168 are substantially coterminous. -
Contacts upper mirror layer 170 and thelower mirror layer 166, respectively, as shown in FIG. 33. Contact 186 has an annular shape to allow light (photons) to pass out of theupper mirror layer 170 into a subsequently formed optical waveguide. - An insulating
layer 190 is then formed and patterned to define optical openings extending to thecontact layer 186 and one of the dopedregions 177 as shown in FIG. 34. The insulating material can be any number of different materials, including an oxide, nitride, oxynitride, low-k dielectric, or any combination thereof. After defining theopenings 192, a higherrefractive index material 202 is then formed within the openings to fill them and to deposit the layer over the insulatinglayer 190 as illustrated in FIG. 35. With respect to the higherrefractive index material 202, “higher” is in relation to the material of the insulating layer 190 (i.e.,material 202 has a higher refractive index compared to the insulating layer 190). Optionally, a relatively thin lower refractive index film (not shown) could be formed before forming the higherrefractive index material 202. Ahard mask layer 204 is then formed over the highrefractive index layer 202. Portions of thehard mask layer 204, and highrefractive index layer 202 are removed from portions overlying the opening and to areas closer to the sides of FIG. 35. - The balance of the formation of the optical waveguide, which is an optical interconnect, is completed as illustrated in FIG. 36. A deposition procedure (possibly a dep-etch process) is performed to effectively create
sidewalls sections 212. In this embodiment, thesidewall sections 212 are made of the same material asmaterial 202. Thehard mask layer 204 is then removed, and a low refractive index layer 214 (low relative tomaterial 202 and layer 212) is formed over the higherrefractive index material layer 190. The dash lines in FIG. 36 illustrate the border between the highrefractive index materials - Processing is continued to form a substantially completed integrated circuit as illustrated in FIG. 37. A
passivation layer 220 is then formed over theoptical laser 180 andMOSFET transistor 181. Although not shown, other electrical or optical connections are made to the components within the integrated circuit but are not illustrated in FIG. 37. These interconnects can include other optical waveguides or may include metallic interconnects. - In other embodiments, other types of lasers can be formed. For example, another type of laser can emit light (photons) horizontally instead of vertically. If light is emitted horizontally, the MOSFET transistor could be formed within the
substrate 161, and the optical waveguide would be reconfigured, so that the laser is properly coupled (optically connected) to the transistor. In one specific embodiment, the optical waveguide can include at least a portion of the accommodating buffer layer. Other configurations are possible. - Clearly, these embodiments of integrated circuits having compound semiconductor portions and Group IV semiconductor portions, are meant to illustrate what can be done and are not intended to be exhaustive of all possibilities or to limit what can be done. There is a multiplicity of other possible combinations and embodiments. For example, the compound semiconductor portion may include light emitting diodes, photodetectors, diodes, or the like, and the Group IV semiconductor can include digital logic, memory arrays, and most structures that can be formed in conventional MOS integrated circuits. By using what is shown and described herein, it is now simpler to integrate devices that work better in compound semiconductor materials with other components that work better in Group IV semiconductor materials. This allows a device to be shrunk, the manufacturing costs to decrease, and yield and reliability to increase.
- Although not illustrated, a monocrystalline Group IV wafer can be used in forming only compound semiconductor electrical components over the wafer. In this manner, the wafer is essentially a “handle” wafer used during the fabrication of the compound semiconductor electrical components within a monocrystalline compound semiconductor layer overlying the wafer. Therefore, electrical components can be formed within III-V or II-VI semiconductor materials over a wafer of at least approximately 200 millimeters in diameter and possibly at least approximately 300 millimeters.
- By the use of this type of substrate, a relatively inexpensive “handle” wafer overcomes the fragile nature of the compound semiconductor wafers by placing them over a relatively more durable and easy to fabricate base material. Therefore, an integrated circuit can be formed such that all electrical components, and particularly all active electronic devices, can be formed within the compound semiconductor material even though the substrate itself may include a Group IV semiconductor material. Fabrication costs for compound semiconductor devices should decrease because larger substrates can be processed more economically and more readily, compared to the relatively smaller and more fragile, conventional compound semiconductor wafers.
- A composite integrated circuit may include components that provide electrical isolation when electrical signals are applied to the composite integrated circuit. The composite integrated circuit may include a pair of optical components, such as an optical source component and an optical detector component. An optical source component may be a light generating semiconductor device, such as an optical laser (e.g., the optical laser illustrated in FIG. 33), a photo emitter, a diode, etc. An optical detector component may be a light-sensitive semiconductor junction device, such as a photodetector, a photodiode, a bipolarjunction, a transistor, etc.
- A composite integrated circuit may include components to detect an object such as a person, a car, a plane, etc. The composite integrated circuit generally includes a source component, a receiver component, and an interconnect. The source component such as, but not limited to, a radio frequency (RF) transmitter (e.g., an RF voltage controlled oscillator) and an optical source component, generates an electromagnetic energy transmission. The electromagnetic energy transmission may be, but is not limited to, an electromagnetic energy transmission in one of the radio, microwave, infrared, visible light and ultraviolet spectrums. The interconnect guides the electromagnetic energy transmission from the source component to an antenna coupled with the interconnect. In addition, the interconnect may guide a portion of the electromagnetic energy transmission from the source component to the receiver component as a reference signal, which is further described below. The interconnect may be, but is not limited to, a dielectric material (i.e., an optical waveguide) and a metallic material. Furthermore, the interconnect may comprise a single interconnect (e.g., a single optical waveguide) or a plurality of interconnects. The antenna transmits the electromagnetic energy transmission. If there is an object then the antenna may receive a reflection of the electromagnetic energy transmission off of the object. Accordingly, the interconnect guides the reflection of the electromagnetic energy transmission from the antenna to the receiver component, which may be, but is not limited to, an optical detector component and an RF receiver (e.g., a mixer and a frequency modulated (FM) detector as one of ordinary skill will readily recognize). The receiver component may generate a detection signal in response to receipt at the antenna of the reflection of the electromagnetic energy transmission. As a result, a parameter associated with the object such as range (e.g., distance between the composite integrated circuit and the object) and speed may be determined by a processor based on the reference signal and the detection signal. The processor may also be integrated into the composite integrated circuit.
- Referring to FIG. 38, for example, a
semiconductor structure 3800 for detecting an object generally includes anoptical source component 3810, anoptical detector component 3820, a firstoptical waveguide 3830, a secondoptical waveguide 3835, and anantenna 3840. The pair ofoptical components optical source component 3810 may be, but is not limited to, a vertical cavity surface emitting laser (VCSEL), a semiconductor laser (e.g., a gallium arsenide (GaAs) laser, an aluminum gallium arsenide (AlGaAs) laser, a gallium nitride (GaN) laser, an indium phosphide (InP) laser, and an indium gallium arsenide (InGasAs) laser), and a light emitting diode (LED). Theoptical detector component 3820 may be, but is not limited to, a photodetector (e.g., a photodiode and a heterojunction bipolar transistor (HBT)) and a photoelectric detector (e.g., gallium arsenide (GaAs) detector, an aluminum gallium arsenide (AlGaAs) detector, a gallium nitride (GaN) detector, an indium phosphide (InP) detector, and an indium gallium arsenide (InGaAs) detector). The pair ofoptical components integrated circuit 3850 having a single monocrystalline silicon substrate. For example, asemiconductor device 3800 for detecting an object includes a VCSEL and a photodetector that are formed within a monocrystalline compound semiconductor material on a common monocrystalline silicon substrate. Although thesemiconductor structure 3800 for detecting an object has been described as a structure formed on a silicon substrate, other substrates, monocrystalline oxide layers and other compound semiconductor layers as described elsewhere in this disclosure may be used to fabricate theoptical source component 3810 and theoptical detector component 3820. - The pair of
optical waveguides integrated circuit 3850. As illustrated in FIG. 38, the firstoptical waveguide 3830 is coupled between theoptical source component 3810 and theantenna 3840, and the secondoptical waveguide 3835 is coupled with theoptical detector component 3820. Furthermore, the secondoptical waveguide 3835 may be disposed to overlie the firstoptical waveguide 3830. The pair ofoptical waveguides optical waveguides optical waveguides reflective components electromagnetic energy transmission 3880 and areflection 3885 of the electromagnetic energy transmission off of anobject 3870, respectively. In particular, thereflective component 3860 is preferably integrated with the firstoptical waveguide 3830 to guide theelectromagnetic energy transmission 3880 generated from theoptical source component 3810 to theantenna 3840, and thereflective component 3865 is preferably integrated with the secondoptical waveguide 3835 to guide thereflection 3885 of the electromagnetic energy transmission off of theobject 3870 from theantenna 3840 to theoptical detector component 3820. In a dielectric waveguide, for example, the dielectric constant may be higher in the inside of the waveguide than that of the outside of the waveguide (e.g., air). Accordingly, thereflective components electromagnetic energy transmission 3880 and itsreflection 3885, respectively. Theantenna 3840 is coupled with the pair ofoptical waveguides antenna 3850 may be, but is not limited to, a horn antenna. - In an alternate embodiment, the interconnect mentioned above may be adapted to detect an object via radio frequency and microwave. In particular, the interconnect may be a metallic waveguide. A probe (e.g., vertical rod) may be integrated with the metallic waveguide to guide an electromagnetic energy transmission from a source component to an antenna and a reflection of the electromagnetic energy transmission from the antenna to a receiver component. The probe may be insulated from the metallic waveguide and coupled to the source component. Further, the probe may be formed, for example, within a fraction of a wavelength from a back wall of the metallic waveguide as one of ordinary skill in art will readily recognize.
- A basic flow for detecting an object3870 (e.g., a person, a car, a plane, etc.) that may be applied with the preferred embodiment of the present invention shown in FIG. 38 starts with the
optical source component 3810 generating anelectromagnetic energy transmission 3880. Theelectromagnetic energy transmission 3880 may be, but is not limited to, an electromagnetic energy transmission in one of the radio, microwave, infrared, visible light and ultraviolet spectrums. The firstoptical waveguide 3830 guides theelectromagnetic energy transmission 3880 via thereflective component 3860 to theantenna 3840. Aportion 3888 of theelectromagnetic energy transmission 3885 generated from theoptical source component 3810 is guided to theoptical detector component 3820 as a reference signal, which is further described below. Theantenna 3840 transmits theelectromagnetic energy transmission 3880. When there is noobject 3870 then theelectromagnetic energy transmission 3880, e.g., a visible light ray, is not reflected off of theobject 3870 back to theantenna 3840. However, when there is anobject 3870 then theantenna 3840 can receive areflection 3885 of the electromagnetic energy transmission off of theobject 3870. The secondoptical waveguide 3835 guides thereflection 3885 of the electromagnetic energy transmission via thereflective component 3865 to theoptical detector component 3820, which in turn generates a detection signal to indicate a presence of an object. Furthermore, aprocessor 3890, which is preferably integrated into the singleintegrated circuit 3850, executes a program or a set of instructions such that theprocessor 3890 is operable to determine a parameter associated with theobject 3870 based on the reference signal and the detection signal as one of ordinary skill in the art will readily recognize. The parameter associated with theobject 3870 may be, for example, a direction, a distance, a height and a speed. For example, theprocessor 3890 may execute a program to determine the distance between thesemiconductor structure 3800 and theobject 3870 based on the reference signal and the detection signal, and a speed of theobject 3870 based on the rate of change of the distance. - In an alternate embodiment, the
semiconductor structure 3800 includes a plurality of receiver components and antennas as described in detail above to detect an object and to determine a direction of the object that is relative to thesemiconductor structure 3800. A source component may generate a plurality of electromagnetic energy transmissions. The plurality of receiver components and antennas receives a plurality of reflections of the plurality of electromagnetic energy transmissions off of an object. Accordingly, theprocessor 3890 determines the direction of the object by using an amplitude and/or a phase difference-based angle of arrival estimation as one of ordinary skill in the art will readily recognize based on the plurality of reflections. - Referring to FIG. 39, a
method 3900 for detecting an object is illustrated.Method 3900 begins atstep 3910, where a monocrystalline silicon substrate is provided. Atstep 3920, a monocrystalline perovskite oxide film is deposited to overlie the monocrystalline silicon substrate. The monocrystalline perovskite oxide film includes a thickness less than the material that would result in strain-induced defects. Atstep 3930, an amorphous oxide interface layer is formed at an interface between the monocrystalline perovskite oxide film and the monocrystalline silicon substrate. The amorphous oxide interface layer contains at least silicon and oxygen. Atstep 3940, a monocrystalline compound semiconductor layer is epitaxially formed to overlie the monocrystalline perovskite oxide film. Atstep 3950, a source component is formed to overlie the monocrystalline compound semiconductor layer. The source component, for example an optical source or radio tranmistter, generates an electromagnetic energy transmission. Atstep 3960, an antenna is provided to transmit the electromagnetic energy transmission generated by the source component. The antenna may receive a reflection of the electromagnetic energy transmission off of an object. Atstep 3970, an interconnect is formed to couple between the antenna and the source component. The interconnect may comprise a single interconnect (e.g., a single optical waveguide) or a plurality of interconnects to guide the electromagnetic energy transmission from the source component to the antenna. Further, the interconnect may guide a portion of the electromagnetic energy transmission from the source component to a receiver component, such as an optical detector or radio receiver, as a reference signal. Atstep 3980, the receiver component is formed to overlie the monocrystalline compound semiconductor layer. The interconnect guides the reflection of the electromagnetic energy transmission off of the object to the receiver component, which may be an optical detector component. Accordingly, the receiver component generates a detection signal in response to receipt at the antenna of the reflection of the electromagnetic energy transmission off of the object. The detection signal indicates a presence of the object. Furthermore, the reference signal and the detection signal may be used to determine a parameter associated with the object. - Devices constructed in accordance with the foregoing described preferred embodiments of the invention may be used for detecting an object. For example, a source component generates an electromagnetic energy transmission. An interconnect guides the electromagnetic energy transmission to an antenna, which in turn, transmits the electromagnetic energy transmission. The interconnect may guide a portion of the electromagnetic energy transmission from the source component to a receiver component as a reference signal. The antenna receives a reflection of the electromagnetic energy transmission off of an object. In response to receipt at the antenna of the reflection of the electromagnetic energy transmission off of the object, the receiver component generates a detection signal that indicates a presence of the object. The reference signal and the detection signal may be used to determine a parameter associated with the object such as a direction, a distance, a height and a speed of the object.
- A composite integrated circuit such as the
semiconductor structure 3800 may include processing circuitry that is formed at least partly in the Group IV semiconductor portion of the composite integrated circuit but may be formed using one of the formation techniques and materials herein described. The processing circuitry is configured to communicate with circuitry external to the composite integrated circuit. The processing circuitry may be electronic circuitry, such as a microprocessor, RAM, logic device, decoder, etc. - For the processing circuitry to communicate with external electronic circuitry, the composite integrated circuit may be provided with electrical signal connections with the external electronic circuitry. The composite integrated circuit such as the
semiconductor structure 3800 may have internal optical communications connections for connecting the processing circuitry in the composite integrated circuit to the electrical connections with the external circuitry. Optical components in the composite integrated circuit may provide the optical communications connections which may electrically isolate the electrical signals in the communications connections from the processing circuitry. Together, the electrical and optical communications connections may be for communicating information, such as data, control, timing, etc. - A pair of optical components (an optical source component and an optical detector component) in the composite integrated circuit may be configured to pass information. Information that is received or transmitted between the optical pair may be from or for the electrical communications connection between the external circuitry and the composite integrated circuit. The optical components and the electrical communications connection may form a communications connection between the processing circuitry and the external circuitry while providing electrical isolation for the processing circuitry. If desired, a plurality of optical component pairs may be included in the composite integrated circuit for providing a plurality of communications connections and for providing isolation. For example, a composite integrated circuit receiving a plurality of data bits may include a pair of optical components for communication of each data bit.
- In operation, for example, an optical source component in a pair of components may be configured to generate light (e.g., photons) based on receiving electrical signals from an electrical signal connection with the external circuitry. An optical detector component in the pair of components may be optically connected to the source component to generate electrical signals based on detecting light generated by the optical source component. Information that is communicated between the source and detector components may be digital or analog.
- If desired the reverse of this configuration may be used. An optical source component that is responsive to the on-board processing circuitry may be coupled to an optical detector component to have the optical source component generate an electrical signal for use in communications with external circuitry. A plurality of such optical component pair structures may be used for providing two-way connections. In some applications where synchronization is desired, a first pair of optical components may be coupled to provide data communications and a second pair may be coupled for communicating synchronization information.
- For clarity and brevity, optical detector components that are discussed below are discussed primarily in the context of optical detector components that have been formed in a compound semiconductor portion of a composite integrated circuit. In application, the optical detector component may be formed in many suitable ways (e.g., formed from silicon, etc.).
- A composite integrated circuit will typically have an electric connection for a power supply and a ground connection. The power and ground connections are in addition to the communications connections that are discussed above. Processing circuitry in a composite integrated circuit may include electrically isolated communications connections and include electrical connections for power and ground. In most known applications, power supply and ground connections are usually well-protected by circuitry to prevent harmful external signals from reaching the composite integrated circuit. A communications ground may be isolated from the ground signal in communications connections that use a ground communications signal.
- In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention. Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a nonexclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Claims (40)
1. A semiconductor structure comprising:
a monocrystalline silicon substrate;
an amorphous oxide material overlying the monocrystalline silicon substrate;
a monocrystalline perovskite oxide material overlying the amorphous oxide material;
a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material;
an antenna, the antenna being operable to transmit an electromagnetic energy transmission;
a source component overlying the monocrystalline compound semiconductor material, the source component being operable to generate the electromagnetic energy transmission;
an interconnect coupled between the antenna and the source component, the interconnect being operable to guide the electromagnetic energy transmission from the source component to the antenna; and
a receiver component overlying the monocrystalline compound semiconductor material, the receiver component being operable to generate a detection signal in response to receipt at the antenna of a reflection of the electromagnetic energy transmission off of the object;
wherein the interconnect is operable to guide a portion of the electromagnetic energy transmission from the source component to the receiver component, the portion being operable as a reference signal.
2. The semiconductor structure of claim 1 , wherein the source component is one of a radio frequency (RF) transmitter and an optical source component.
3. The semiconductor structure of claim 1 , wherein the optical source component is one of a vertical cavity surface emitting laser (VCSEL), a group III-V compound semiconductor laser, and a light emitting diode (LED).
4. The semiconductor structure of claim 3 , wherein the group III-V compound semiconductor laser is one of a gallium arsenide (GaAs) laser, an aluminum gallium arsenide (AlGaAs) laser, a gallium nitride (GaN) laser, an indium phosphide (InP) laser, and an indium gallium arsenide (InGasAs) laser.
5. The semiconductor structure of claim 1 , wherein the receiver component is one of a radio frequency (RF) receiver and an optical detector component.
6. The semiconductor structure of claim 5 , wherein the optical detector component is one of a photodetector and a photoelectric detector.
7. The semiconductor structure of claim 6 , wherein the photodetector is one of a photodiode and a phototransistor.
8. The semiconductor structure of claim 7 , wherein the photoelectric detector is a group III-V compound semiconductor detector.
9. The semiconductor structure of claim 8 , wherein the group III-V compound semiconductor detector is one of a gallium arsenide (GaAs) detector, an aluminum gallium arsenide (AlGaAs) detector, a gallium nitride (GaN) detector, an indium phosphide (InP) detector, and an indium gallium arsenide (InGaAs) detector.
10. The semiconductor structure of claim 1 , wherein the interconnect is one of an optical waveguide and a metallic waveguide.
11. The semiconductor structure of claim 10 , wherein the optical waveguide is formed from one of an organic material, an inorganic material, and a gas medium.
12. The semiconductor structure of claim 11 , wherein the organic material is one of an epoxy, a polycarbonate, a polystyrene, a polymethyl methacrylate, a polysulfone, a polyimide, and a polyurethane material.
13. The semiconductor structure of claim 11 , wherein the organic material is one of a glass and a ceramic material.
14. The semiconductor structure of claim 13 , wherein the ceramic material is one of a silica, a lithium niobate, a lead lanthamum, a zirconate titanate and a barium titanate (BTO) material.
15. The semiconductor structure of claim 1 , wherein the interconnect is a first interconnect, and wherein the semiconductor structure further comprises a second interconnect, the second interconnect being operable to guide the reflection of the electromagnetic energy transmission off of the object from the antenna to the receiver component.
16. The semiconductor structure of claim 1 , wherein the interconnect comprises a reflective component, the reflective component being operable to guide the electromagnetic energy transmission.
17. The semiconductor structure of claim 1 , wherein the antenna is a horn antenna.
18. The semiconductor structure of claim 1 further comprising a processor overlying the monocrystalline compound semiconductor material, the processor is operable to determine a parameter associated with the object based on the reference signal and the detection signal, wherein the parameter is one a direction, a distance, a height, and a speed.
19. The semiconductor structure of claim 1 , wherein the electromagnetic energy transmission is an electromagnetic energy transmission in one of the radio, microwave, infrared, visible light and ultraviolet spectrums.
20. A process for fabricating a semiconductor structure for detecting an object comprising:
providing a monocrystalline silicon substrate;
depositing a monocrystalline perovskite oxide film overlying the monocrystalline silicon substrate, the film having a thickness less than a thickness of the material that would result in strain-induced defects;
forming an amorphous oxide interface layer containing at least silicon and oxygen at an interface between the monocrystalline perovskite oxide film and the monocrystalline silicon substrate;
epitaxially forming a monocrystalline compound semiconductor layer overlying the monocrystalline perovskite oxide film;
forming a source component overlying the monocrystalline compound semiconductor layer, the source component being operable to generate an electromagnetic energy transmission;
providing an antenna, the antenna being operable to transmit the electromagnetic energy transmission;
forming an interconnect coupled between the antenna and the source component, the interconnect being operable to guide the electromagnetic energy transmission from the source component; and
forming a receiver component overlying the monocrystalline compound semiconductor layer, the receiver component being operable to generate a detection signal in response to receipt at the antenna of a reflection of the electromagnetic energy transmission off of an object;
wherein the interconnect is operable to guide a portion of the electromagnetic energy transmission from the source component to the receiver component, the portion being operable as a reference signal.
21. The process of claim 20 , the step of forming an source component comprising forming one of a radio frequency (RF) transmitter and an optical source component overlying the monocrystalline semiconductor layer.
22. The process of claim 21 , the step of forming an optical source component comprising forming one of a vertical cavity surface emitting laser (VCSEL), a group III-V compound semiconductor laser, and a light emitting diode (LED) overlying the monocrystalline compound semiconductor layer.
23. The process of claim 22 , wherein the group III-V compound semiconductor laser is one of a gallium arsenide (GaAs) laser, an aluminum gallium arsenide (AlGaAs) laser, a gallium nitride (GaN) laser, an indium phosphide (InP) laser, and an indium gallium arsenide (InGasAs) laser overlying the monocrystalline compound semiconductor layer.
24. The process of claim 20 , the step of forming a receiver component comprising forming one of a radio frequency (RF) receiver and an optical detector component overlying the monocrystalline compound semiconductor layer.
25. The process of claim 24 , the step of forming an optical detector component comprising forming one of a photodetector and a photoelectric detector overlying on the monocrystalline compound semiconductor layer.
26. The process of claim 25 , the step of forming a photodetector comprising forming one of a photodiode and a phototransistor overlying on the monocrystalline compound semiconductor layer.
27. The process of claim 25 , the step of forming a photoelectric detector comprising forming a group III-V compound semiconductor detector overlying on the monocrystalline compound semiconductor layer.
28. The process of claim 27 , the step of forming a photoelectric detector comprising forming one of a gallium arsenide (GaAs) detector, an aluminum gallium arsenide (AlGaAs) detector, a gallium nitride (GaN) detector, an indium phosphide (InP) detector, and an indium gallium arsenide (InGaAs) detector overlying the monocrystalline compound semiconductor layer.
29. The process of claim 20 , the step of forming an interconnect comprising forming one of an optical waveguide and a metallic waveguide coupled between the antenna and the source component.
30. The process of claim 29 , the step of forming an optical waveguide comprising forming an optical waveguide from one of an organic material, an inorganic material, and a gas medium.
31. The process of claim 30 , the step of forming an optical waveguide from an organic material comprising forming an optical waveguide from one of an epoxy, a polycarbonate, a polystyrene, a polymethyl methacrylate, a polysulfone, a polyimide, and a polyurethane material.
32. The process of claim 30 , step of forming an optical waveguide from an inorganic material comprising forming an optical waveguide from one of a glass and a ceramic material.
33. The process of claim 32 , the step of forming an optical waveguide from a ceramic material comprising forming an optical waveguide from one of a silica, a lithium niobate, a lead lanthamum, a zirconate titanate and a barium titanate (BTO) material.
34. The process of claim 20 , wherein the interconnect is a first interconnect, and wherein the process further comprises forming a second interconnect coupled with the first interconnect, the second interconnect being operable to guide the reflection of the electromagnetic energy transmission off of the object from the antenna to the receiver component.
35. The process of claim 20 , the step of forming an interconnect comprising forming an interconnect having a reflective component, the reflective component being operable to guide the electromagnetic energy transmission.
36. The process of claim 20 , the step of forming an antenna comprising forming a horn antenna.
37. The process of claim 20 further comprising forming a processor to overlie the monocrystalline compound semiconductor layer, the processor being operable to determine a parameter associated with the object based on the reference signal and the detection signal, wherein the parameter is one of a direction, a distance, a height, and a speed.
38. The process of claim 20 , wherein the electromagnetic energy transmission is an electromagnetic energy transmission in one of the radio, microwave, infrared, visible light and ultraviolet spectrums.
39. A method for detecting an object comprising:
providing a monocrystalline silicon substrate;
depositing a monocrystalline perovskite oxide film overlying the monocrystalline silicon substrate, the film having a thickness less than a thickness of the material that would result in strain-induced defects;
forming an amorphous oxide interface layer containing at least silicon and oxygen at an interface between the monocrystalline perovskite oxide film and the monocrystalline silicon substrate;
epitaxially forming a monocrystalline compound semiconductor layer overlying the monocrystalline perovskite oxide film;
transmitting an electromagnetic energy signal using active devices formed in the monocrystalline compound semiconductor layer; and
generating a detection signal in response to receipt of a reflection of the electromagnetic energy signal off of an object, wherein a portion of the electromagnetic energy signal is operable as a reference signal.
40. The method of claim 39 further comprising determining a parameter associated with the object based on the reference signal and the detection signal, wherein the parameter is one of a direction, a distance, a height and a speed.
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