US20010046778A1 - Dual damascene process using sacrificial spin-on materials - Google Patents

Dual damascene process using sacrificial spin-on materials Download PDF

Info

Publication number
US20010046778A1
US20010046778A1 US09/532,731 US53273100A US2001046778A1 US 20010046778 A1 US20010046778 A1 US 20010046778A1 US 53273100 A US53273100 A US 53273100A US 2001046778 A1 US2001046778 A1 US 2001046778A1
Authority
US
United States
Prior art keywords
coating material
reflective coating
oxide layer
layer
contact hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/532,731
Other versions
US6424039B2 (en
Inventor
Fei Wang
Bhanwar Singh
James Kai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lone Star Silicon Innovations LLC
Original Assignee
Fei Wang
Bhanwar Singh
Kai James K.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fei Wang, Bhanwar Singh, Kai James K. filed Critical Fei Wang
Priority to US09/532,731 priority Critical patent/US6424039B2/en
Publication of US20010046778A1 publication Critical patent/US20010046778A1/en
Application granted granted Critical
Publication of US6424039B2 publication Critical patent/US6424039B2/en
Assigned to LONE STAR SILICON INNOVATIONS LLC reassignment LONE STAR SILICON INNOVATIONS LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ADVANCED MICRO DEVICES INC.
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material

Definitions

  • the invention relates generally to a dual damascene process for forming a contact hole for an integrated circuit (IC) and more particularly to a dual damascene process that uses a sacrificial layer of spin-on material for protecting the contact hole profile during the damascene etch process.
  • FIGS. 1 A- 1 F illustrate the steps of the conventional dual damascene process.
  • FIG. 1A illustrates an oxide layer 20 disposed on top of a semiconductor substrate 10 .
  • a layer of photoresist 30 is spin coated on top of the oxide layer 20 , exposed through a mask (not shown) containing a contact hole pattern, and developed. An etch opening 31 is thus formed. Using the remaining photoresist as an etch mask, the oxide layer 20 is then etched to form a contact hole 32 and the remaining photoresist is then removed producing the structure shown in FIG. 1B.
  • a layer of photoresist 33 is applied a second time (FIG. 1C).
  • the photoresist 33 is then exposed through a mask (not shown) and developed to form an etch opening 34 (FIG. 1D).
  • the oxide layer 20 is etched to form a wiring trough 35 as shown in FIG. 1E.
  • This etch step is known as a damascene etch step.
  • the remaining photoresist is removed and the contact hole 32 and the wiring trough 35 are filled with metal 36 .
  • the reflectivity from the topography substrate makes the width of the etch opening 34 in the photoresist 33 difficult to control.
  • the aspect ratio (height/width) of the contact hole 32 has increased. At high aspect ratios, it is difficult for the photoresist 33 to completely flow into and fill the contact hole 32 . If the contact hole is not completely filled, there is a possibility that the photoresist 33 disposed within the contact hole 32 may partially or even completely develop away and provide little or no protection for the contact hole profile during the subsequent damascene etch step.
  • the thickness of the photoresist 33 over the topography substrate varies signficantly, and so the exposure depth of the photoresist 33 is difficult to control. This is likely to cause an over-development of the photoresist 33 disposed within the contact hole 32 and possibly erode the contact hole profile during the subsequent damascene etch step.
  • An object of this invention is to provide a dual damascene process that produces more consistent results by employing an improved process control.
  • Another object of this invention is to provide a dual damascene process for forming a semiconductor structure with improved damascene etch profiles.
  • Still another object of this invention is to provide for use in a dual damascene process a semiconductor structure having a sacrificial layer of anti-reflective coating material.
  • a dual damascene process including the steps of forming a contact hole in an oxide layer disposed above a semiconductor substrate, disposing a layer of anti-reflective coating material on top of the oxide layer and in the contact hole, and partially etching the layer of anti-reflective coating material and the oxide layer to form the wiring trough.
  • the partial etching step includes the steps of spin coating photoresist on top of the anti-reflective coating material, exposing the photoresist through a mask containing a pattern of the wiring trough, developing the photoresist to expose portions of the anti-reflective coating material, dry etching the exposed portions of the anti-reflective coating material to expose portions of the oxide layer, and wet etching the exposed portions of the oxide layer to form the wiring trough.
  • the anti-reflective coating material can be non-photosensitive, and is termed a “sacrificial layer” because it is added and then “sacrificed” (i.e., removed) for the purpose of performing an interim function in the dual damascene process.
  • the dual damascene process according to the invention employs a semiconductor structure including a substrate, an oxide layer disposed above the substrate, and a layer of anti-reflective coating material disposed on top of the oxide layer.
  • the oxide layer has a contact hole which is filled by the anti-reflective coating material when the anti-reflective coating material is disposed on top of the oxide layer.
  • a photoresist formed to have a wiring trough pattern is disposed on top of the layer of the anti-reflective coating material.
  • the wiring trough pattern defines an opening which is aligned with the contact hole and which has a width larger than that of the contact hole.
  • the photoresist is used as a mask during the damascene etching step that forms the wiring trough in the oxide layer in alignment with the contact hole.
  • FIG. 1A- 1 F illustrate a conventional dual damascene process
  • FIG. 2A- 2 H illustrate a dual damascene process according to a first embodiment of the invention.
  • FIG. 3A- 3 H illustrate a dual damascene process according to a second embodiment of the invention.
  • FIG. 2A- 2 H illustrate a dual damascene process according to a first embodiment of the invention.
  • FIG. 2A illustrates an oxide layer 20 disposed on top of a semiconductor substrate 10 .
  • a layer of photoresist 30 is spin coated on top of the oxide layer 20 , exposed through a mask (not shown) containing a contact hole pattern, and developed in a weak alkaline medium to remove the exposed photoresist.
  • An etch opening 31 is thus formed.
  • the oxide layer 20 is then wet etched to form a contact hole 32 and the remaining photoresist is removed (FIG. 2B).
  • the wet etch may be either a buffered-oxide etch (BOE) dip or a hydrofluoric (HF) dip.
  • BOE buffered-oxide etch
  • HF hydrofluoric
  • a sacrificial layer 40 of spin-on material is applied on top of the oxide layer 20 (FIG. 2C).
  • the spin-on material is an anti-reflective coating material and can be any of the following: CD 11 , BARLi, or low dielectric constant materials such as BCB, HSQ, SOG, and Flare.
  • CD 11 is preferred when employing deep ultraviolet wavelength photolithography and BARLi is preferred when employing i-line wavelength photolithography.
  • a layer of photoresist 50 is then spin coated on top of the sacrificial layer 40 , exposed through a mask (not shown) containing a wiring trough pattern, and developed in a weak alkaline medium to remove the exposed photoresist. An etch opening 51 is thus formed.
  • the sacrificial layer 40 is anisotropically etched to form an opening 52 (FIG. 2E).
  • the anisotropic etch process may be carried out as a dry etch, preferably a plasma etch.
  • the oxide layer 20 is etched in BOE or HF solution to form a wiring trough 53 as shown in FIG. 2F.
  • the sacrificial layer etch step and the oxide etch step can be carried out at the same time using a dry etch, preferably a plasma etch.
  • the remaining photoresist and the remaining sacrificial layer are then removed (FIG. 2G).
  • HSQ or SOG
  • BOE or HF solution can be used to remove the HSQ (or SOG) layer after the photoresist 50 is stripped because the HSQ (or SOG) etch rate in BOE or HF solution is much faster than that of oxide.
  • Metal 36 is deposited on top of the oxide layer 20 to fill the contact hole 32 and the wiring trough 53 , and polished to obtain the structure shown in FIG. 2H.
  • the metal 36 may be tungsten, copper, aluminum, or any alloy thereof.
  • FIG. 3A- 3 H illustrate a dual damascene process according to a second embodiment of the invention.
  • FIG. 3A illustrates a first oxide layer 20 disposed on top of a first nitride layer 13 , a second oxide layer 12 , a second nitride layer 11 , and a semiconductor substrate 10 .
  • a layer of photoresist 30 is spin coated on top of the oxide layer 20 , exposed through a mask (not shown) containing a contact hole pattern, and developed in a weak alkaline medium to remove the exposed photoresist. An etch opening 31 is thus formed.
  • the oxide layer 20 , the first nitride layer 13 , and the second oxide layer 12 are then plasma etched to form a contact hole 32 .
  • the remaining photoresist is then removed (FIG. 3B).
  • a sacrificial layer 40 of spin-on material is applied on top of the oxide layer 20 (FIG. 3C).
  • the spin-on material is an anti-reflective coating material and can be any of the following: CD 11 , BARLi, or low dielectric constant materials such as BCB, HSQ, SOG, and Flare.
  • CD 11 is preferred when employing deep ultraviolet wavelength photolithography and BARLi is preferred when employing i-line wavelength photolithography.
  • a layer of photoresist 50 is then spin coated on top of the sacrificial layer 40 , exposed through a mask (not shown) containing a wiring trough pattern, and developed in a weak alkaline medium to remove the exposed photoresist. An etch opening 51 is thus formed.
  • the sacrificial layer 40 is anisotropically etched to form an opening 52 (FIG. 3E).
  • the anisotropic etch process may be carried out as a dry etch, preferably plasma etch.
  • the oxide layer 20 is plasma etched to form a wiring trough 53 as shown in FIG. 3F.
  • the nitride layer 13 functions well as an etch stop for this etching step.
  • HSQ or SOG
  • the sacrificial layer etch step and the oxide etch step can be carried out at the same time using a dry etch, preferably a plasma etch.
  • the remaining photoresist and the remaining sacrificial layer are then removed in oxygen plasma (FIG. 3G).
  • oxygen plasma FOG. 3G
  • BOE or HF solution can be used to remove the HSQ (or SOG) layer after the photoresist 50 is stripped because the HSQ (or SOG) etch rate in BOE or HF solution is much faster than that of either nitride or oxide.
  • Metal 36 is deposited on top of the oxide layer 20 to fill the contact hole 32 and the wiring trough 35 , and polished to obtain the structure shown in FIG. 3H.
  • the metal 36 may be tungsten, copper, aluminum, or any alloy thereof.

Abstract

A dual damascene process includes the steps of forming a contact hole in an oxide layer disposed above a semiconductor substrate, disposing a layer of anti-reflective coating material on top of the oxide layer and in the contact hole, and partially etching the layer of anti-reflective coating material and the oxide layer to form the wiring trough. The partial etching step includes the steps of spin coating photoresist on top of the anti-reflective coating material, exposing the photoresist through a mask containing a pattern of the wiring trough, developing the photoresist to expose portions of the anti-reflective coating material, dry etching the exposed portions of the anti-reflective coating material to expose portions of the oxide layer, and wet etching the exposed portions of the oxide layer to form the wiring trough.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The invention relates generally to a dual damascene process for forming a contact hole for an integrated circuit (IC) and more particularly to a dual damascene process that uses a sacrificial layer of spin-on material for protecting the contact hole profile during the damascene etch process. [0002]
  • 2. Description of the Related Art [0003]
  • A conventional dual damascene process is described in Licata et al., “Dual Damascene Al Wiring for 256M DRAM,” Proceedings of the 12th International VLSI Multilevel Interconection Conference, edited by T. E. Wade (VMIC, Tampa), pp. 596-602 (1995). FIGS. [0004] 1A-1F illustrate the steps of the conventional dual damascene process.
  • FIG. 1A illustrates an [0005] oxide layer 20 disposed on top of a semiconductor substrate 10. A layer of photoresist 30 is spin coated on top of the oxide layer 20, exposed through a mask (not shown) containing a contact hole pattern, and developed. An etch opening 31 is thus formed. Using the remaining photoresist as an etch mask, the oxide layer 20 is then etched to form a contact hole 32 and the remaining photoresist is then removed producing the structure shown in FIG. 1B.
  • Next, a layer of [0006] photoresist 33 is applied a second time (FIG. 1C). The photoresist 33 is then exposed through a mask (not shown) and developed to form an etch opening 34 (FIG. 1D). Using the remaining photoresist as an etch mask, the oxide layer 20 is etched to form a wiring trough 35 as shown in FIG. 1E. This etch step is known as a damascene etch step. The remaining photoresist is removed and the contact hole 32 and the wiring trough 35 are filled with metal 36.
  • The above-described process is difficult to control for three reasons. [0007]
  • First, the reflectivity from the topography substrate makes the width of the etch opening [0008] 34 in the photoresist 33 difficult to control.
  • Second, as feature sizes have become smaller, the aspect ratio (height/width) of the [0009] contact hole 32 has increased. At high aspect ratios, it is difficult for the photoresist 33 to completely flow into and fill the contact hole 32. If the contact hole is not completely filled, there is a possibility that the photoresist 33 disposed within the contact hole 32 may partially or even completely develop away and provide little or no protection for the contact hole profile during the subsequent damascene etch step.
  • Third, the thickness of the [0010] photoresist 33 over the topography substrate varies signficantly, and so the exposure depth of the photoresist 33 is difficult to control. This is likely to cause an over-development of the photoresist 33 disposed within the contact hole 32 and possibly erode the contact hole profile during the subsequent damascene etch step.
    • SUMMARY OF THE INVENTION
  • An object of this invention is to provide a dual damascene process that produces more consistent results by employing an improved process control. [0011]
  • Another object of this invention is to provide a dual damascene process for forming a semiconductor structure with improved damascene etch profiles. [0012]
  • Still another object of this invention is to provide for use in a dual damascene process a semiconductor structure having a sacrificial layer of anti-reflective coating material. [0013]
  • The above and other objects of the invention are accomplished by a dual damascene process including the steps of forming a contact hole in an oxide layer disposed above a semiconductor substrate, disposing a layer of anti-reflective coating material on top of the oxide layer and in the contact hole, and partially etching the layer of anti-reflective coating material and the oxide layer to form the wiring trough. [0014]
  • The partial etching step includes the steps of spin coating photoresist on top of the anti-reflective coating material, exposing the photoresist through a mask containing a pattern of the wiring trough, developing the photoresist to expose portions of the anti-reflective coating material, dry etching the exposed portions of the anti-reflective coating material to expose portions of the oxide layer, and wet etching the exposed portions of the oxide layer to form the wiring trough. The anti-reflective coating material can be non-photosensitive, and is termed a “sacrificial layer” because it is added and then “sacrificed” (i.e., removed) for the purpose of performing an interim function in the dual damascene process. [0015]
  • The dual damascene process according to the invention employs a semiconductor structure including a substrate, an oxide layer disposed above the substrate, and a layer of anti-reflective coating material disposed on top of the oxide layer. The oxide layer has a contact hole which is filled by the anti-reflective coating material when the anti-reflective coating material is disposed on top of the oxide layer. A photoresist formed to have a wiring trough pattern is disposed on top of the layer of the anti-reflective coating material. The wiring trough pattern defines an opening which is aligned with the contact hole and which has a width larger than that of the contact hole. The photoresist is used as a mask during the damascene etching step that forms the wiring trough in the oxide layer in alignment with the contact hole. [0016]
  • Additional objects, features and advantages of the invention will be set forth in the description of preferred embodiments which follows.[0017]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The invention is described in detail herein with reference to the drawings in which: [0018]
  • FIG. 1A-[0019] 1F illustrate a conventional dual damascene process; and
  • FIG. 2A-[0020] 2H illustrate a dual damascene process according to a first embodiment of the invention.
  • FIG. 3A-[0021] 3H illustrate a dual damascene process according to a second embodiment of the invention.
  • The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred exemplary embodiments of the invention, and, together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention. [0022]
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • FIG. 2A-[0023] 2H illustrate a dual damascene process according to a first embodiment of the invention. FIG. 2A illustrates an oxide layer 20 disposed on top of a semiconductor substrate 10. A layer of photoresist 30 is spin coated on top of the oxide layer 20, exposed through a mask (not shown) containing a contact hole pattern, and developed in a weak alkaline medium to remove the exposed photoresist. An etch opening 31 is thus formed. Using the remaining photoresist as an etch mask, the oxide layer 20 is then wet etched to form a contact hole 32 and the remaining photoresist is removed (FIG. 2B). The wet etch may be either a buffered-oxide etch (BOE) dip or a hydrofluoric (HF) dip.
  • Next, a [0024] sacrificial layer 40 of spin-on material is applied on top of the oxide layer 20 (FIG. 2C). The spin-on material is an anti-reflective coating material and can be any of the following: CD11, BARLi, or low dielectric constant materials such as BCB, HSQ, SOG, and Flare. CD11 is preferred when employing deep ultraviolet wavelength photolithography and BARLi is preferred when employing i-line wavelength photolithography. A layer of photoresist 50 is then spin coated on top of the sacrificial layer 40, exposed through a mask (not shown) containing a wiring trough pattern, and developed in a weak alkaline medium to remove the exposed photoresist. An etch opening 51 is thus formed.
  • Afterwards, using the remaining photoresist as an etch mask, the [0025] sacrificial layer 40 is anisotropically etched to form an opening 52 (FIG. 2E). The anisotropic etch process may be carried out as a dry etch, preferably a plasma etch. Then, using the remaining photoresist and the remaining sacrificial layer as an etch mask, the oxide layer 20 is etched in BOE or HF solution to form a wiring trough 53 as shown in FIG. 2F. When HSQ or SOG is used as the sacrificial layer 40, the sacrificial layer etch step and the oxide etch step can be carried out at the same time using a dry etch, preferably a plasma etch.
  • The remaining photoresist and the remaining sacrificial layer are then removed (FIG. 2G). When HSQ (or SOG) is used as the [0026] sacrificial layer 40, BOE or HF solution can be used to remove the HSQ (or SOG) layer after the photoresist 50 is stripped because the HSQ (or SOG) etch rate in BOE or HF solution is much faster than that of oxide. Metal 36 is deposited on top of the oxide layer 20 to fill the contact hole 32 and the wiring trough 53, and polished to obtain the structure shown in FIG. 2H. The metal 36 may be tungsten, copper, aluminum, or any alloy thereof.
  • FIG. 3A-[0027] 3H illustrate a dual damascene process according to a second embodiment of the invention. FIG. 3A illustrates a first oxide layer 20 disposed on top of a first nitride layer 13, a second oxide layer 12, a second nitride layer 11, and a semiconductor substrate 10. A layer of photoresist 30 is spin coated on top of the oxide layer 20, exposed through a mask (not shown) containing a contact hole pattern, and developed in a weak alkaline medium to remove the exposed photoresist. An etch opening 31 is thus formed. Using the remaining photoresist as an etch mask, the oxide layer 20, the first nitride layer 13, and the second oxide layer 12 are then plasma etched to form a contact hole 32. The remaining photoresist is then removed (FIG. 3B).
  • Next, a [0028] sacrificial layer 40 of spin-on material is applied on top of the oxide layer 20 (FIG. 3C). The spin-on material is an anti-reflective coating material and can be any of the following: CD11, BARLi, or low dielectric constant materials such as BCB, HSQ, SOG, and Flare. CD11 is preferred when employing deep ultraviolet wavelength photolithography and BARLi is preferred when employing i-line wavelength photolithography. A layer of photoresist 50 is then spin coated on top of the sacrificial layer 40, exposed through a mask (not shown) containing a wiring trough pattern, and developed in a weak alkaline medium to remove the exposed photoresist. An etch opening 51 is thus formed.
  • Afterwards, using the remaining photoresist as an etch mask, the [0029] sacrificial layer 40 is anisotropically etched to form an opening 52 (FIG. 3E). The anisotropic etch process may be carried out as a dry etch, preferably plasma etch. Then, using the remaining photoresist and the remaining sacrificial layer- as an etch mask, the oxide layer 20 is plasma etched to form a wiring trough 53 as shown in FIG. 3F. The nitride layer 13 functions well as an etch stop for this etching step. When HSQ (or SOG) is used as the sacrificial layer 40, the sacrificial layer etch step and the oxide etch step can be carried out at the same time using a dry etch, preferably a plasma etch.
  • The remaining photoresist and the remaining sacrificial layer are then removed in oxygen plasma (FIG. 3G). When HSQ (or SOG) is used as the [0030] sacrificial layer 40, BOE or HF solution can be used to remove the HSQ (or SOG) layer after the photoresist 50 is stripped because the HSQ (or SOG) etch rate in BOE or HF solution is much faster than that of either nitride or oxide. Metal 36 is deposited on top of the oxide layer 20 to fill the contact hole 32 and the wiring trough 35, and polished to obtain the structure shown in FIG. 3H. The metal 36 may be tungsten, copper, aluminum, or any alloy thereof.
  • While particular embodiments according to the invention have been illustrated and described above, it will be clear that the invention can take a variety of forms and embodiments within the scope of the appended claims. [0031]

Claims (22)

We claim:
1. A dual damascene process comprising the steps of:
forming a contact hole in an oxide layer;
disposing a layer of anti-reflective coating material on top of the oxide layer and filling the contact hole with the anti-reflective coating material;
etching the anti-reflective coating material to expose portions of the oxide layer;
etching the exposed portions of the oxide layer to form a wiring trough;
removing the anti-reflective coating material; and
filling the contact hole and the wiring trough with a metal.
2. The process as recited in
claim 1
, wherein the step of etching the anti-reflective coating material includes the steps of:
depositing photoresist on top of the anti-reflective coating material;
exposing the photoresist through a mask containing a pattern of the wiring trough;
developing the photoresist to expose portions of the anti-reflective coating material; and
etching the exposed portions of the anti-reflective coating material.
3. The process as recited in
claim 1
, wherein the step of disposing the layer of anti-reflective coating material includes the step of spin coating the layer of anti-reflective coating material.
4. The process as recited in
claim 3
, wherein the step of spin coating the layer of anti-reflective coating material includes the step of selecting an anti-reflective coating material that is non-photosensitive.
5. A dual damascene process for forming a semiconductor structure having a wiring trough and a contact hole defined contiguously therein, said process comprising the steps of:
forming the contact hole in an oxide layer;
disposing a layer of anti-reflective coating material on top of the oxide layer and in the contact hole; and
etching the layer of anti-reflective coating material and the oxide layer to form the wiring trough.
6. The process as recited in
claim 5
, wherein the step of etching to form the wiring trough includes the steps of:
depositing photoresist on top of the anti-reflective coating material;
exposing the photoresist through a mask containing a pattern of the wiring trough;
developing the photoresist to expose portions of the anti-reflective coating material;
etching the exposed portions of the anti-reflective coating material to expose portions of the oxide layer; and
etching the exposed portions of the oxide layer to form the wiring trough.
7. The process as recited in
claim 6
, wherein the step of etching the exposed portions of the anti-reflective coating material includes the step of anisotropic etching.
8. The process as recited in
claim 6
, wherein the step of etching the exposed portions of the oxide layer includes the step of buffered-oxide etching.
9. The process as recited in
claim 5
, wherein the step of disposing the layer of anti-reflective coating material includes the step of spin coating the layer of anti-reflective coating material.
10. The process as recited in
claim 9
, wherein the step of spin coating the layer of anti-reflective coating material includes the step of selecting an anti-reflective coating material that is non-photosensitive.
11. A semiconductor structure comprising:
a substrate;
an oxide layer disposed above the substrate, the oxide layer having a contact hole formed therein; and
a layer of anti-reflective coating material disposed on top of the oxide layer, the anti-reflective coating material filling the contact hole.
12. The semiconductor structure as recited in
claim 11
, further comprising a photoresist disposed on top of the layer of anti-reflective coating material, the photoresist having a wiring trough pattern.
13. The semiconductor structure as recited in
claim 12
, wherein the wiring trough pattern defines an opening aligned with the contact hole.
14. The semiconductor structure as recited in
claim 13
, wherein the width of the opening is larger than the width of the contact hole.
15. The semiconductor structure as recited in
claim 11
, wherein the anti-reflective coating material includes a non-photosensitive material.
16. The semiconductor structure as recited in
claim 11
, further comprising:
a first nitride layer disposed on top of the substrate;
a second oxide layer disposed on top of the first nitride layer; and
a second nitride layer disposed on top of the second oxide layer,
wherein the first oxide layer is disposed on top of the second nitride layer.
17. The semiconductor structure as recited in
claim 16
, wherein the contact hole extends through the first oxide layer, the second nitride layer, and the second nitride layer.
18. The semiconductor structure as recited in
claim 17
, wherein the anti-reflective coating material disposed on top of the oxide layer defines an opening aligned with the contact hole.
19. The semiconductor structure as recited in
claim 18
, wherein the oxide layer further defines a wiring trough aligned with the contact hole.
20. The semiconductor structure as recited in
claim 19
, wherein the widths of the opening and the wiring trough are substantially equal to each other and larger than the width of the contact hole.
21. A semiconductor structure made using the process of
claim 1
.
22. A semiconductor structure made using the process of
claim 5
.
US09/532,731 1997-12-17 2000-03-22 Dual damascene process using sacrificial spin-on materials Expired - Lifetime US6424039B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/532,731 US6424039B2 (en) 1997-12-17 2000-03-22 Dual damascene process using sacrificial spin-on materials

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/992,537 US6057239A (en) 1997-12-17 1997-12-17 Dual damascene process using sacrificial spin-on materials
US09/532,731 US6424039B2 (en) 1997-12-17 2000-03-22 Dual damascene process using sacrificial spin-on materials

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US08/992,537 Division US6057239A (en) 1997-12-17 1997-12-17 Dual damascene process using sacrificial spin-on materials

Publications (2)

Publication Number Publication Date
US20010046778A1 true US20010046778A1 (en) 2001-11-29
US6424039B2 US6424039B2 (en) 2002-07-23

Family

ID=25538437

Family Applications (2)

Application Number Title Priority Date Filing Date
US08/992,537 Expired - Lifetime US6057239A (en) 1997-12-17 1997-12-17 Dual damascene process using sacrificial spin-on materials
US09/532,731 Expired - Lifetime US6424039B2 (en) 1997-12-17 2000-03-22 Dual damascene process using sacrificial spin-on materials

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US08/992,537 Expired - Lifetime US6057239A (en) 1997-12-17 1997-12-17 Dual damascene process using sacrificial spin-on materials

Country Status (1)

Country Link
US (2) US6057239A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040018721A1 (en) * 2002-07-24 2004-01-29 Samsung Electronics Co., Ltd. Method for forming a dual damascene wiring pattern in a semiconductor device
US20040132291A1 (en) * 2002-02-22 2004-07-08 Samsung Electronics Co., Ltd. Method of fabricating dual damascene interconnections of microelectronic device using hybrid low k-dielectric and carbon-free inorganic filler
US6828229B2 (en) 2001-05-10 2004-12-07 Samsung Electronics Co., Ltd. Method of manufacturing interconnection line in semiconductor device
US20050029229A1 (en) * 2003-08-08 2005-02-10 Applied Materials, Inc. Selective etch process of a sacrificial light absorbing material (SLAM) over a dielectric material
US20180138077A1 (en) * 2015-12-30 2018-05-17 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming interconnection structure

Families Citing this family (79)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW383463B (en) 1998-06-01 2000-03-01 United Microelectronics Corp Manufacturing method for dual damascene structure
US6680248B2 (en) 1998-06-01 2004-01-20 United Microelectronics Corporation Method of forming dual damascene structure
US6319813B1 (en) * 1998-07-06 2001-11-20 Micron Technology, Inc. Semiconductor processing methods of forming integrated circuitry and integrated circuitry constructions
US6649515B2 (en) * 1998-09-30 2003-11-18 Intel Corporation Photoimageable material patterning techniques useful in fabricating conductive lines in circuit structures
US6406995B1 (en) * 1998-09-30 2002-06-18 Intel Corporation Pattern-sensitive deposition for damascene processing
TW413896B (en) * 1999-01-06 2000-12-01 United Microelectronics Corp Manufacturing method for dual damascene structure
EP1190277B1 (en) * 1999-06-10 2009-10-07 AlliedSignal Inc. Semiconductor having spin-on-glass anti-reflective coatings for photolithography
US6268457B1 (en) 1999-06-10 2001-07-31 Allied Signal, Inc. Spin-on glass anti-reflective coatings for photolithography
US6329118B1 (en) * 1999-06-21 2001-12-11 Intel Corporation Method for patterning dual damascene interconnects using a sacrificial light absorbing material
WO2001001480A1 (en) * 1999-06-30 2001-01-04 Intel Corporation Method of protecting an underlying wiring layer during dual damascene processing
US6872665B1 (en) * 1999-07-12 2005-03-29 Texas Instruments Incorporated Process flow for dual damescene interconnect structures
US6297149B1 (en) * 1999-10-05 2001-10-02 International Business Machines Corporation Methods for forming metal interconnects
JP2001135630A (en) * 1999-11-10 2001-05-18 Matsushita Electronics Industry Corp Method of manufacturing semiconductor device
JP3346475B2 (en) * 2000-01-18 2002-11-18 日本電気株式会社 Manufacturing method of semiconductor integrated circuit, semiconductor integrated circuit
JP2001230317A (en) * 2000-02-15 2001-08-24 Nec Corp Method for forming multilayer interconnection structure and multilayer interconnection structure for semiconductor device
US6521542B1 (en) * 2000-06-14 2003-02-18 International Business Machines Corp. Method for forming dual damascene structure
US6576550B1 (en) 2000-06-30 2003-06-10 Infineon, Ag ‘Via first’ dual damascene process for copper metallization
JP2004503089A (en) * 2000-06-30 2004-01-29 インフィネオン　テクノロジーズ　アクチエンゲゼルシャフト Via-first dual damascene method for copper metallization
JP4654544B2 (en) * 2000-07-12 2011-03-23 日産化学工業株式会社 Gap fill material forming composition for lithography
US6380073B1 (en) * 2000-08-29 2002-04-30 United Microelectronics Corp. Method for forming metal interconnection structure without corner faceted
US6455416B1 (en) * 2000-10-24 2002-09-24 Advanced Micro Devices, Inc. Developer soluble dyed BARC for dual damascene process
US6737222B2 (en) * 2000-11-21 2004-05-18 Advanced Micro Devices, Inc. Dual damascene process utilizing a bi-layer imaging layer
US6583047B2 (en) * 2000-12-26 2003-06-24 Honeywell International, Inc. Method for eliminating reaction between photoresist and OSG
US6514860B1 (en) * 2001-01-31 2003-02-04 Advanced Micro Devices, Inc. Integration of organic fill for dual damascene process
KR100366639B1 (en) * 2001-03-23 2003-01-06 삼성전자 주식회사 A method for formation of contact having low resistivity using porous oxide plug and methods for forming semiconductor devices using the same
US6506692B2 (en) 2001-05-30 2003-01-14 Intel Corporation Method of making a semiconductor device using a silicon carbide hard mask
US6821896B1 (en) * 2001-05-31 2004-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method to eliminate via poison effect
US6448185B1 (en) 2001-06-01 2002-09-10 Intel Corporation Method for making a semiconductor device that has a dual damascene interconnect
US6730561B2 (en) * 2001-06-06 2004-05-04 Applied Materials, Inc. Method of forming a cup capacitor
US6875699B1 (en) * 2001-06-21 2005-04-05 Lam Research Corporation Method for patterning multilevel interconnects
US6551915B2 (en) * 2001-07-03 2003-04-22 Taiwan Semiconductor Manufacturing Co., Ltd. Thermal annealing/hydrogen containing plasma method for forming structurally stable low contact resistance damascene conductor structure
US6616855B1 (en) 2001-09-27 2003-09-09 Taiwan Semiconductor Manufacturing Company Process to reduce surface roughness of low K damascene
US6680262B2 (en) * 2001-10-25 2004-01-20 Intel Corporation Method of making a semiconductor device by converting a hydrophobic surface of a dielectric layer to a hydrophilic surface
US6488509B1 (en) 2002-01-23 2002-12-03 Taiwan Semiconductor Manufacturing Company Plug filling for dual-damascene process
US7253112B2 (en) 2002-06-04 2007-08-07 Taiwan Semiconductor Manufacturing Co., Ltd. Dual damascene process
EP1385201B1 (en) * 2002-07-24 2012-09-05 Samsung Electronics Co., Ltd. Method of fabricating dual damascene interconnections of microelectronic device
TW544857B (en) * 2002-07-30 2003-08-01 Promos Technologies Inc Manufacturing method of dual damascene structure
US6864556B1 (en) * 2002-07-31 2005-03-08 Advanced Micro Devices, Inc. CVD organic polymer film for advanced gate patterning
KR100441685B1 (en) * 2002-09-19 2004-07-27 삼성전자주식회사 Dual damascene process
KR100457044B1 (en) * 2002-09-25 2004-11-10 삼성전자주식회사 Method for manufacturing semiconductor device
JP2004128074A (en) * 2002-09-30 2004-04-22 Sanyo Electric Co Ltd Manufacturing method of semiconductor device
US6569777B1 (en) * 2002-10-02 2003-05-27 Taiwan Semiconductor Manufacturing Co., Ltd Plasma etching method to form dual damascene with improved via profile
US6872666B2 (en) * 2002-11-06 2005-03-29 Intel Corporation Method for making a dual damascene interconnect using a dual hard mask
US6917109B2 (en) * 2002-11-15 2005-07-12 United Micorelectronics, Corp. Air gap structure and formation method for reducing undesired capacitive coupling between interconnects in an integrated circuit device
US7138329B2 (en) * 2002-11-15 2006-11-21 United Microelectronics Corporation Air gap for tungsten/aluminum plug applications
US7449407B2 (en) * 2002-11-15 2008-11-11 United Microelectronics Corporation Air gap for dual damascene applications
JP4210858B2 (en) * 2002-12-26 2009-01-21 日産化学工業株式会社 Gap fill material forming composition for alkali dissolution type lithography
WO2004074938A1 (en) 2003-02-21 2004-09-02 Nissan Chemical Industries, Ltd. Acrylic polymer-containing gap filler forming composition for lithography
US20040175934A1 (en) * 2003-03-04 2004-09-09 International Business Machines Corporation Method for improving etch selectivity effects in dual damascene processing
US6858528B2 (en) * 2003-03-20 2005-02-22 Intel Corporation Composite sacrificial material
KR101156200B1 (en) * 2003-05-23 2012-06-18 다우 코닝 코포레이션 Siloxane resin-based anti-reflective coating composition having high wet etch rate
JP2004356708A (en) * 2003-05-27 2004-12-16 Hosiden Corp Sound detection mechanism and manufacturing method thereof
US8053159B2 (en) 2003-11-18 2011-11-08 Honeywell International Inc. Antireflective coatings for via fill and photolithography applications and methods of preparation thereof
KR100534103B1 (en) * 2004-01-14 2005-12-06 삼성전자주식회사 Method of fabricating a microelectronic device using supercritical fluid
KR100593737B1 (en) * 2004-01-28 2006-06-28 삼성전자주식회사 Wiring Method and Wiring Structure of Semiconductor Device
US20050170638A1 (en) * 2004-01-30 2005-08-04 Bang-Ching Ho Method for forming dual damascene interconnect structure
KR100621541B1 (en) * 2004-02-06 2006-09-14 삼성전자주식회사 Method for fabricating dual damascene interconnection and etchant for stripping sacrificial fill material
US7241682B2 (en) * 2004-02-27 2007-07-10 Taiwan Seminconductor Manufacturing Co., Ltd. Method of forming a dual damascene structure
KR100593446B1 (en) * 2004-05-19 2006-06-28 삼성전자주식회사 Methods of manufacturing semiconductor devices using organic fluoride buffer solutions
KR100745986B1 (en) * 2004-12-08 2007-08-06 삼성전자주식회사 Fabrication method of dual damascene interconnections of microelectronics device using filler having porogen
EP1819844B1 (en) 2004-12-17 2008-07-09 Dow Corning Corporation Method for forming anti-reflective coating
KR101191098B1 (en) * 2004-12-17 2012-10-15 다우 코닝 코포레이션 Siloxane resin coating
US7645707B2 (en) * 2005-03-30 2010-01-12 Lam Research Corporation Etch profile control
US20070105362A1 (en) * 2005-11-09 2007-05-10 Kim Jae H Methods of forming contact structures in low-k materials using dual damascene processes
WO2007094848A2 (en) 2006-02-13 2007-08-23 Dow Corning Corporation Antireflective coating material
US8642246B2 (en) 2007-02-26 2014-02-04 Honeywell International Inc. Compositions, coatings and films for tri-layer patterning applications and methods of preparation thereof
US8334338B2 (en) 2007-05-23 2012-12-18 Jsr Corporation Composition for forming resist lower layer film
US8158524B2 (en) * 2007-09-27 2012-04-17 Lam Research Corporation Line width roughness control with arc layer open
KR101528947B1 (en) * 2007-09-27 2015-06-15 램 리써치 코포레이션 Profile control in dielectric etch
JP5587791B2 (en) 2008-01-08 2014-09-10 東レ・ダウコーニング株式会社 Silsesquioxane resin
WO2009091440A1 (en) * 2008-01-15 2009-07-23 Dow Corning Corporation Silsesquioxane resins
WO2009111122A2 (en) * 2008-03-04 2009-09-11 Dow Corning Corporation Silsesquioxane resins
JP5581224B2 (en) * 2008-03-05 2014-08-27 ダウ・コーニング・コーポレイション Silsesquioxane resin
EP2376584B1 (en) * 2008-12-10 2014-07-16 Dow Corning Corporation Wet-etchable antireflective coatings
US8809482B2 (en) 2008-12-10 2014-08-19 Dow Corning Corporation Silsesquioxane resins
US8557877B2 (en) 2009-06-10 2013-10-15 Honeywell International Inc. Anti-reflective coatings for optically transparent substrates
US8864898B2 (en) 2011-05-31 2014-10-21 Honeywell International Inc. Coating formulations for optical elements
US8803129B2 (en) 2011-10-11 2014-08-12 International Business Machines Corporation Patterning contacts in carbon nanotube devices
JP6803842B2 (en) 2015-04-13 2020-12-23 ハネウェル・インターナショナル・インコーポレーテッドＨｏｎｅｙｗｅｌｌ Ｉｎｔｅｒｎａｔｉｏｎａｌ Ｉｎｃ． Polysiloxane formulations and coatings for optoelectronic applications

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4775550A (en) * 1986-06-03 1988-10-04 Intel Corporation Surface planarization method for VLSI technology
US5110697A (en) * 1988-09-28 1992-05-05 Brewer Science Inc. Multifunctional photolithographic compositions
US5106786A (en) * 1989-10-23 1992-04-21 At&T Bell Laboratories Thin coatings for use in semiconductor integrated circuits and processes as antireflection coatings consisting of tungsten silicide
US5275972A (en) * 1990-02-19 1994-01-04 Matsushita Electric Industrial Co., Ltd. Method for fabricating a semiconductor integrated circuit device including the self-aligned formation of a contact window
US5100503A (en) * 1990-09-14 1992-03-31 Ncr Corporation Silica-based anti-reflective planarizing layer
US5401613A (en) * 1990-12-13 1995-03-28 Brewer Science Method of manufacturing microelectronic devices having multifunctional photolithographic layers
US5219788A (en) * 1991-02-25 1993-06-15 Ibm Corporation Bilayer metallization cap for photolithography
US5264076A (en) * 1992-12-17 1993-11-23 At&T Bell Laboratories Integrated circuit process using a "hard mask"
US5397684A (en) * 1993-04-27 1995-03-14 International Business Machines Corporation Antireflective polyimide dielectric for photolithography
KR0128828B1 (en) * 1993-12-23 1998-04-07 김주용 Forming method of contact hole in the semiconductor device
US5635423A (en) * 1994-10-11 1997-06-03 Advanced Micro Devices, Inc. Simplified dual damascene process for multi-level metallization and interconnection structure
US5705430A (en) * 1995-06-07 1998-01-06 Advanced Micro Devices, Inc. Dual damascene with a sacrificial via fill
US5759911A (en) * 1995-08-22 1998-06-02 International Business Machines Corporation Self-aligned metallurgy
US5741626A (en) * 1996-04-15 1998-04-21 Motorola, Inc. Method for forming a dielectric tantalum nitride layer as an anti-reflective coating (ARC)
US5910018A (en) * 1997-02-24 1999-06-08 Winbond Electronics Corporation Trench edge rounding method and structure for trench isolation
US6074959A (en) * 1997-09-19 2000-06-13 Applied Materials, Inc. Method manifesting a wide process window and using hexafluoropropane or other hydrofluoropropanes to selectively etch oxide

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6828229B2 (en) 2001-05-10 2004-12-07 Samsung Electronics Co., Ltd. Method of manufacturing interconnection line in semiconductor device
US20040132291A1 (en) * 2002-02-22 2004-07-08 Samsung Electronics Co., Ltd. Method of fabricating dual damascene interconnections of microelectronic device using hybrid low k-dielectric and carbon-free inorganic filler
US7183195B2 (en) 2002-02-22 2007-02-27 Samsung Electronics, Co., Ltd. Method of fabricating dual damascene interconnections of microelectronic device using hybrid low k-dielectric and carbon-free inorganic filler
US20040018721A1 (en) * 2002-07-24 2004-01-29 Samsung Electronics Co., Ltd. Method for forming a dual damascene wiring pattern in a semiconductor device
US6855629B2 (en) 2002-07-24 2005-02-15 Samsung Electronics Co., Ltd. Method for forming a dual damascene wiring pattern in a semiconductor device
US20050029229A1 (en) * 2003-08-08 2005-02-10 Applied Materials, Inc. Selective etch process of a sacrificial light absorbing material (SLAM) over a dielectric material
US20070020944A1 (en) * 2003-08-08 2007-01-25 Applied Materials, Inc. Selective etch process of a sacrificial light absorbing material (slam) over a dielectric material
US7300597B2 (en) * 2003-08-08 2007-11-27 Applied Materials, Inc. Selective etch process of a sacrificial light absorbing material (SLAM) over a dielectric material
US20180138077A1 (en) * 2015-12-30 2018-05-17 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming interconnection structure
US11075112B2 (en) * 2015-12-30 2021-07-27 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming interconnection structure

Also Published As

Publication number Publication date
US6057239A (en) 2000-05-02
US6424039B2 (en) 2002-07-23

Similar Documents

Publication Publication Date Title
US6424039B2 (en) Dual damascene process using sacrificial spin-on materials
US5882999A (en) Process for metallization of an insulation layer
US5895740A (en) Method of forming contact holes of reduced dimensions by using in-situ formed polymeric sidewall spacers
US6440640B1 (en) Thin resist with transition metal hard mask for via etch application
US6825562B2 (en) Damascene structure fabricated using a layer of silicon-based photoresist material
US6972259B2 (en) Method for forming openings in low dielectric constant material layer
US6140225A (en) Method of manufacturing semiconductor device having multilayer wiring
US7871934B2 (en) Method for an integrated circuit contact
US5882996A (en) Method of self-aligned dual damascene patterning using developer soluble arc interstitial layer
US6458705B1 (en) Method for forming via-first dual damascene interconnect structure
US6743711B2 (en) Method for forming dual damascene line structure
EP0905768A1 (en) A dual damascene process for metal layers and organic intermetal layers
US7749904B2 (en) Method of forming a dual damascene structure
US6426298B1 (en) Method of patterning a dual damascene
US5234864A (en) Method for interconnecting layers in a semiconductor device using two etching gases
US6521542B1 (en) Method for forming dual damascene structure
JP4108228B2 (en) Manufacturing method of semiconductor device
US6815335B2 (en) Method for forming a contact in a semiconductor process
US6930038B2 (en) Dual damascene partial gap fill polymer fabrication process
US6372614B2 (en) Dual damascene method for backened metallization using poly stop layers
US6406836B1 (en) Method of stripping photoresist using re-coating material
US6780778B2 (en) Method for fabricating semiconductor device
US6569760B1 (en) Method to prevent poison via
US20030124464A1 (en) Method for forming via and contact holes with deep UV photoresist
US6660645B1 (en) Process for etching an organic dielectric using a silyated photoresist mask

Legal Events

Date Code Title Description
STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: LONE STAR SILICON INNOVATIONS LLC, TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ADVANCED MICRO DEVICES INC.;REEL/FRAME:039597/0957

Effective date: 20160804