US20010020736A1 - Semiconductor package and manufacturing method thereof - Google Patents
Semiconductor package and manufacturing method thereof Download PDFInfo
- Publication number
- US20010020736A1 US20010020736A1 US09/850,265 US85026501A US2001020736A1 US 20010020736 A1 US20010020736 A1 US 20010020736A1 US 85026501 A US85026501 A US 85026501A US 2001020736 A1 US2001020736 A1 US 2001020736A1
- Authority
- US
- United States
- Prior art keywords
- face
- semiconductor element
- wiring substrate
- resin layer
- semiconductor package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
- B29C45/00—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
- B29C45/17—Component parts, details or accessories; Auxiliary operations
- B29C45/26—Moulds
- B29C45/34—Moulds having venting means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/29111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83909—Post-treatment of the layer connector or bonding area
- H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01068—Erbium [Er]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3512—Cracking
Definitions
- the present invention relates to semiconductor devices such as semiconductor packages, particularly relates to thin and highly reliable semiconductor packages.
- a means for mounting a semiconductor element on a wiring substrate can be generally divided into a face-up type bonding (wire bonding), and face-down type bonding (flip chip bonding).
- connecting electrodes of a semiconductor element and connecting electrodes of a wiring substrate are connected with bonding wires. Then, by molding the semiconductor element including the bonding wires on the wiring substrate, a semiconductor package is formed.
- connecting electrodes of a semiconductor element and connecting electrodes of a wiring substrate are connected with conductive bumps and the like.
- the semiconductor package of the flip chip type there are an over-coat type in which a semiconductor element is molded as a whole, and a bare chip type in which a semiconductor element is exposed. Even in the latter case, it is generally done to seal a gap between a semiconductor element and a wiring substrate with a resin and the like.
- Semiconductor packages of the flip chip type because they can be made thinner than those of the face-up type, are recently used much in CSP (Chip Size Package) and the like.
- the CSPs are used much in, for instance, computers, semiconductor packages of high frequency and integrated function used in communication instruments, or portable information instruments such as a PDA.
- FIG. 11 is a diagram showing a structure of a conventional semiconductor package.
- a semiconductor element (chip) 92 is mounted in a face-down manner on a wiring substrate 91 .
- Connecting terminals 92 a of the semiconductor element 92 and pads 93 disposed on the wiring substrate 91 are connected with conductive bumps 94 .
- the conductive bumps are composed of, for instance, solder, gold and the like.
- a gap between the wiring substrate 91 and the semiconductor element 92 is sealed with a resin layer 95 called an under-fill.
- a semiconductor package of a structure in which a rear surface of the semiconductor 92 is exposed is illustrated, however, if the semiconductor element 92 is covered with a molding resin as a whole, a semiconductor package of the over-coat structure can be obtained.
- connecting pads 96 connected to the bonding pads 93 are disposed, on the connecting pads 96 solder balls 97 are disposed. Those solder balls 97 and the conductive bumps 94 are connected electrically with interior wiring.
- the wiring substrate 91 glass fabric based epoxy resin is employed as an insulating layer.
- that of two-layered structure is employed here, however, that of multi-layered structure such as three-layered structure or more may be employed.
- a metallic cap or a heat-sink is disposed in some cases.
- solder balls are disposed as BGA (ball grid array) type terminals.
- the connecting terminals 96 to which the solder balls 97 are disposed and the bonding pads 93 of the wiring substrate are connected between layers with, for instance, through holes, conductive pillars consisting of conductive resin and the like.
- FIG. 12A, FIG. 12B and FIG. 12C are diagrams explaining a method forming a resin layer 95 (under-fill).
- a liquid resin 95 i such as epoxy resin or the like is supplied from a dispense nozzle 99 . Viscosity of the resin is selected and adjusted according to demands.
- the dispense nozzle 99 is attached to a syringe in which the resin 95 i is stocked.
- the resin 95 i permeates into a gap between the wiring substrate 91 and the semiconductor element 92 due to capillary action (FIG. 12A). That is, the resin 95 i supplied from the dispense nozzle 99 is dripped on the circumference of the wiring substrate 91 (FIG. 12B), then the dripped resin permeates into the gap between the wiring substrate 91 and the semiconductor element 92 (FIG. 12C), thus the under-fill is formed thereby.
- Thermal expansion coefficient of a semiconductor element and that of a wiring substrate differ approximately one digit in general.
- the thermal expansion coefficient of a semiconductor element (chip) consisting of silicon, for instance, is about 3-4 ppm/K
- the thermal expansion coefficient of a wiring substrate having an organic insulating layer such as FR-4, FR-5 or BT resin (Bis maleimide triazine) is about 12 to 20 ppm/K. Therefore, deformation due to thermal load is larger for the wiring substrate than that of the semiconductor chip. Therefore, stress pulling the semiconductor element 92 occurs, due to this stress, the semiconductor package suffers warp.
- FIG. 13A, FIG. 13B and FIG. 13C are diagrams explaining stress suffered by a semiconductor package.
- appearance of chip crack and resin crack observed in TCT (Thermal Cycle Test) which is a generally adopted environment test of semiconductor package is shown schematically.
- a resin layer 95 is filled in a gap formed between the wiring substrate 91 and the semiconductor element.
- that of an under-fill resin layer 95 is extremely thin.
- Displacement of warp of a semiconductor package after an under-fill is formed is desirable to be suppressed at 100 ⁇ m or less at most, preferable to be 80 ⁇ m or less. Further, the displacement of the warp of the semiconductor package is further desirable to be suppressed approximately 50 to 70 ⁇ m or less. That is implemented so that there does not occur any inconvenience when solder balls 97 or caps are attached after the under-fill is formed, or package coplanarity guaranty (ordinarily the maximum of 100 ⁇ m) is to be satisfied.
- modulus of elasticity of the semiconductor element 166 [GPa]
- thermal expansion coefficient of resin layer (under-fill) 26 [ppm/K]
- thermal expansion coefficient of the wiring substrate 14.6 [ppm/K]
- modulus of elasticity of the substrate 24 [GPa]
- radius of curvature ⁇ is calculated as follows.
- FIG. 15 is a diagram for explaining flexure of a multi-layer composite beam.
- t is a coordinate between t(i+1) and t(i) and corresponds to a displacement in the direction of the thickness of the semiconductor package.
- t3 a boundary between the semiconductor element and the resin layer of the under-fill
- t5 bottom surface of the wiring substrate.
- ⁇ i thermal expansion coefficient of the layer i
- ⁇ i coordinate of a neutral line
- ⁇ radius of curvature
- ⁇ i and ⁇ i can be expressed with the following equations.
- ⁇ i [ ⁇ E J ( t J+1 ⁇ t j )( ⁇ j ⁇ 1 ) ⁇ T]/ ⁇ E J ( t J+1 ⁇ t J )
- T ⁇ 4 ⁇ E j ⁇ j ( t j+1 ⁇ t J ) ⁇ E J ( t j+1 3 ⁇ t J 3 )+3 ⁇ E j ⁇ J (t j+1 2 ⁇ t j 2 ) ⁇ E j ( t j+1 2 ⁇ t J 2 ), and
- Another problem of the flip-chip type semiconductor package is in its difficulty of securing heat releasing path for a semiconductor element.
- a semiconductor element being mounted on a wiring substrate in a face-up way, a rear surface of the semiconductor element (the surface opposite to the surface where integrated circuit is formed) is connected onto die pads of the wiring substrate. Therefore, heat from the semiconductor element can be released to the wiring substrate side.
- an object of the present invention is to provide a semiconductor package which is thin, compact and highly reliable. Further, another object of the present invention is to provide a thin semiconductor package of high connection reliability. Still another object of the present invention is to provide a semiconductor package of a structure suitable for high density packaging.
- a semiconductor package of the present invention adopts such a configuration as described below.
- the first aspect of a semiconductor package of the present invention comprises, a wiring substrate having a first face and a second face, the first face having a first area and a second area surrounds the first area, and at least a first connecting pad arranged in the first area; a semiconductor element having a first face and a second face, the semiconductor element having at least a connecting terminal formed on the first face, and the semiconductor element being mounted on the first area of the wiring substrate in a face-down type; at least a conductive bump connecting the first connecting pad of the wiring substrate and the connecting terminal of the semiconductor element; and, a resin layer disposed on the first face of the wiring substrate, the resin layer disposed so that the second face of the semiconductor element being exposed, side faces of the semiconductor element being sealed, and a gap between the first face of the wiring substrate and the first face of the semiconductor element being filled.
- a wiring substrate which has a first face having a first area thereon a first connecting pads are disposed and a second area in the circumference of the first area and a second face; a semiconductor element which has a first face thereon connecting terminals are disposed and a second face, and is mounted in a face-down way on the first area of the first face of the wiring substrate; conductive bumps connecting the first connecting pads of the wiring substrate and connecting terminals of the semiconductor element; and a resin layer for sealing disposed such that the second face of the semiconductor element is exposed, and side surface of the semiconductor element is covered, and the resin layer fills a gap between the semiconductor element and the wiring substrate.
- the resin layer for sealing may have a first face substantially in parallel with the first face of the wiring substrate, in addition, may be disposed such that the first face of the resin layer for sealing and the second face of the semiconductor element are substantially in a same plane.
- the resin layer for sealing may be inclined in its side faces, and, at the same time, the first face of the wiring substrate can be made larger than the first face of the resin layer for sealing.
- the resin layer for sealing may be disposed so that it covers substantially the second area of the first face of the wiring substrate.
- the semiconductor package of the present invention may further comprise a conductive plate on the second face of the semiconductor element.
- a heat releasing path of the semiconductor element can be secured. Therefore, reliability of the semiconductor package can be improved.
- thermal load being put on the semiconductor package can be alleviated. Therefore, the stress generated due to discrepancy and the like of thermal expansion coefficients of the constituent elements such as a semiconductor element, a resin layer for sealing and a wiring substrate on the semiconductor package, can be alleviated. Therefore, a thin semiconductor package of high dimensional accuracy can be provided.
- the resin layer for sealing may be disposed such that it covers the side faces of the conductive plate. That is, with the resin layer for sealing, the conductive plate may be fixed. In this case, it is desirable from the view-point of securing heat releasing path to dispose the sealing resin layer with the conductive plate exposed.
- the second face of the semiconductor element may be disposed with not only the conductive plate but also a heat releasing plate with a heat-sink, for instance.
- the second aspect of a semiconductor package of the present invention comprises, a wiring substrate having a first face and a second face, the substrate having at least a first connecting pad formed on the first face; a semiconductor element having a first face and a second face, the semiconductor element having at least a connecting terminal formed on the first face, and the semiconductor element being mounted on the first area of the wiring substrate in a face-down type; at least a conductive bump connecting the first connecting pad of the wiring substrate and the connecting terminal of the semiconductor element; and, a resin layer disposed on the first face of the wiring substrate and the second face of the semiconductor element so that the semiconductor element being sealed; wherein, ( ⁇ r ⁇ Er ⁇ Hr)/( ⁇ s ⁇ Es ⁇ Hs) is approximately 0.6 or more, when ⁇ r is a thermal expansion coefficient of the resin layer, Er is a Young's modulus if the resin layer, Hr is a thickness of the resin layer, ⁇ s is a thermal expansion coefficient of the wiring substrates, Es is a Young's modulus of
- a wiring substrate having a first face thereon a first connecting pads are disposed and a second face; a semiconductor element which has a first face thereon connecting terminals are disposed and a second face, and is mounted in a face-down way on the first face of the wiring substrate; conductive bumps connecting the first connecting pads of the wiring substrate and the connecting terminals of the semiconductor element; and a resin layer disposed on the first face of the wiring substrate in such a manner that seals the semiconductor element; wherein, when thermal expansion coefficient, Young's modulus and thickness of the wiring substrate is ⁇ s, Es and Hs, respectively, and thermal expansion coefficient, Young's modulus and thickness of the resin layer is ⁇ r, Er and Hr, respectively, ( ⁇ r ⁇ Er ⁇ Hr)/( ⁇ s ⁇ Es ⁇ Hs) is approximately 0.6 or more.
- thermal expansion coefficient and Young's modulus of the semiconductor is ⁇ c, Ec, respectively, ( ⁇ c ⁇ Ec)/( ⁇ s ⁇ Es) may be designed to be approximately 1.5 or more.
- the present inventors found that, by adjusting thermal expansion coefficient ⁇ s, Young's modulus Es and thickness Hs of the wiring substrate, and, thermal expansion coefficient ⁇ r, Young's modulus Er and thickness Hr of the resin layer, the stress being put on the semiconductor package can be effectively alleviated.
- the present invention is based on such findings.
- the thickness of a resin layer (under-fill) filled in between a semiconductor element and a wiring substrate is ordinarily extremely thin (for instance, approximately 0.2 mm or less). Therefore, this part exerts very slight influence on the distortion of the whole semiconductor package. Therefore, the thickness Hr of the resin layer is set as a thickness of the resin layer disposed on the second face of the semiconductor element. Further, the resin layer disposed as the under-fill and the resin layer sealing the whole semiconductor element can be composed of different materials.
- the resin layer for sealing may be divided into a first portion filled in between the wiring substrate and the semiconductor element and a second portion covering the semiconductor element from above the second face of the semiconductor element, and the first portion may be constituted of a resin layer of smaller Young's modulus than that of the second portion.
- a soft resin can be disposed in the circumference of the conductive bumps, thereby deformation and rupture of the conductive bumps can be prevented from occurring. Therefore, a semiconductor package of high reliability and high productivity can be provided.
- the third aspect of a manufacturing method of a semiconductor package of the present invention comprises, a step of mounting a semiconductor element on a first face of a wiring substrate, a first face of the semiconductor having at least a connecting terminal, the first face of the wiring substrate having at least a first connecting pad, the connecting terminal of the semiconductor element being connected by a conductive bump; and a step of forming a resin layer on the first face of the wiring substrate so that the semiconductor element is sealed; wherein, ⁇ r, Er, Hr, ⁇ s, Es, Hs are arranged so that ( ⁇ r ⁇ Er ⁇ Hr)/( ⁇ s ⁇ Es ⁇ Hs) is approximately 0.6 or more, when ⁇ r is a thermal expansion coefficient of the resin layer, Er is a Young's modulus if the resin layer, Hr is a thickness of the resin layer, ⁇ s is a thermal expansion coefficient of the wiring substrates, Es is a Young's modulus of the wiring substrate and Hs is a thickness of the wiring substrates.
- the step of forming the resin layer can be carried out with transfer molding in which, after setting a wiring substrate mounted a semiconductor element thereon in a cavity, resin is supplied to be cured. Further, in this case, the resin layer may be supplied under pressure, and, at the same time, curing can be carried out thermally.
- the resin layer may be formed with transfer mold method.
- the semiconductor package of the present invention may be provided with a sealing resin body consisting of a first resin layer filling a gap between a first face thereon conductive bumps of a semiconductor element are formed and a main surface of a wiring substrate, and a second resin layer which contacts at least circumference of a semiconductor element, and is formed so as to surround the semiconductor element.
- a semiconductor package of the present invention comprises at least one semiconductor element having conductive bumps; a wiring substrate the main surface thereof is electrically connected to the semiconductor element through the conductive bumps; and a sealing resin formed on the main surface of the wiring substrate; wherein the sealing resin may be constituted of a first resin layer filling a gap between a first face thereon the conductive bumps of the semiconductor element are formed and the main surface of the wiring substrate, and a second resin layer contacting at least circumference of the semiconductor element and formed so as to surround the semiconductor element.
- a liquid resin is injected under pressure by a transfer method or an injection molding method, by curing this, the sealing resin is formed.
- the present invention can be applied to various kinds of semiconductor packages and semiconductor devices.
- the semiconductor package of the present invention also includes an MCM (multi-chip module).
- MCM multi-chip module
- a CPU central processing unit
- DSP digital signal processor
- various kinds of memory chips including a flash type non-volatile semiconductor memory, or a composite chip thereof can be cited.
- FIG. 1 is a diagram showing diagrammatically one example of a configuration of a semiconductor package of the present invention
- FIG. 2 is a diagram showing diagrammatically another example of a configuration of a semiconductor package of the present invention.
- FIG. 3 is a diagram showing diagrammatically another example of a configuration of a semiconductor package of the present invention.
- FIG. 4 is a diagram showing diagrammatically a plan configuration of the semiconductor package illustrated in FIG. 1;
- FIG. 5 is a diagram explaining a connection structure of a wiring substrate and a semiconductor element
- FIG. 6 is a diagram showing diagrammatically another example of a configuration of a semiconductor package of the present invention.
- FIG. 7 is a chart showing results of coplanarity of a semiconductor package evaluated by simulation
- FIG. 8 is a diagram explaining coplanarity of the most lowest surface of terminal
- FIG. 9A and FIG. 9B are cross-sectional views of a molding die used for resin sealing for formation of a mold layer 13 ;
- FIG. 10 is a diagram explaining dependence of relation between coplanality of the most lowest surface of the terminals of a semiconductor package and size of the mold layer on the thickness of the mold layer;
- FIG. 11 is a diagram diagrammatically showing a structure of a conventional semiconductor package
- FIG. 12A, FIG. 12B and FIG. 12C are diagrams explaining a method of forming a resin layer 95 (under-fill).
- FIG. 13A, FIG. 13B and FIG. 13C are diagrams explaining stress exerted on a semiconductor package.
- FIG. 14 is a diagram diagrammatically showing a structure of an electronic device having a mother wiring substrate the semiconductor package of the present invention being mounted;
- FIG. 15 is a diagram for explaining a warping of a multi-layered lamination.
- FIG. 16 and FIG. 17 are diagrams for explaining coplanarity of a semiconductor package of the present invention.
- FIG. 1 is a diagram showing an example of a configuration of a semiconductor package of the present invention.
- the semiconductor package 10 comprises a wiring substrate 11 having a wiring layer on a first face and another wiring layer on a second face, a semiconductor element 12 mounted on the first face of the wiring substrate 11 , and a mold layer 13 which is disposed on the first face, where the semiconductor element being mounted on.
- the mold layer is consisting of a resin. This mold layer 13 is disposed such that a rear surface of a semiconductor element 12 is exposed.
- the semiconductor element 12 is mounted in a face-down manner on a wiring substrate 11 . That is, between connecting terminals 14 of the semiconductor element 12 and connecting pads 15 disposed as a part of wiring pattern of the wiring substrate, the conductive bumps 16 are disposed.
- the conductive bumps 16 may be constituted of such as solder or gold, for instance. With the conductive bumps 16 , the semiconductor element 12 and the wiring substrate 11 are connected electrically and mechanically.
- connecting terminals 17 are disposed, and on the connecting terminals 17 , solder balls 18 are arranged in array. That is, the semiconductor package 10 is a semiconductor package of a BGA type. Incidentally, connecting terminals 15 and 17 of the wiring substrate 11 are connected through the interconnection such as through holes, conductive pillars and the like, for instance.
- the wiring substrate 11 for instance, a glass cloth is used as a base material and therein organic material such as BT (Bis-maleimide Triazine) resin or epoxy resin is impregnated and is cured, the resultant cured resin polymer is adopted as an insulating layer. Further, the mold layer 13 is formed of epoxy based polymer, for instance.
- organic material such as BT (Bis-maleimide Triazine) resin or epoxy resin is impregnated and is cured, the resultant cured resin polymer is adopted as an insulating layer.
- the mold layer 13 is formed of epoxy based polymer, for instance.
- FIG. 14 is a diagram diagrammatically showing a structure of an electronic device having a mother wiring substrate the semiconductor package of the present invention being mounted.
- the semiconductor package of the invention having a high coplanality, therefore, a reliability of the electronic device is promoted.
- FIG. 2 is a diagram showing diagrammatically another example of a semiconductor package of the present invention.
- under-fill 19 consisting of a resin of a smaller Young's modulus than that constituting the mold layer 13 is filled.
- a relatively soft resin can be disposed on the circumference of the conductive bumps 16 .
- the stress exerting on the conductive bumps 16 can be alleviated, accordingly reliability of connection between the wiring substrate 11 and the semiconductor element 12 can be promoted.
- FIG. 3 is a diagram showing diagrammatically another example of a semiconductor package of the present invention. This semiconductor package is a modification example of the semiconductor packages illustrated in FIG. 1 and FIG. 2.
- a conductive plate 20 is disposed on a rear face of a main face of a semiconductor element 12 .
- Main face is where an integrated circuit being formed.
- This conductive plate is composed of conductive materials consisting of Cu, 42 alloy, SUS, Ti, Fe, Ni and alloy materials mainly consisting thereof, for instance.
- This conductive plate 20 is adhered to the rear surface of the semiconductor element 12 with an adhesive layer 21 therein filler is dispersed.
- filler one in which silver is dispersed as a filler is desirable, one in which silver is dispersed in high density is more desirable.
- SG-2105S product of Ablestick Co,
- DM4030HK product of Diemat Co,
- As a filler material being dispersed in a binder resin other than silver aluminum hydroxide, alumina, silicon carbide, silica and the like can be cited, for instance.
- a semiconductor package of the present invention can be made small in its deformation and extremely high in its flatness, at the same time, due to the conductive plate 20 , heat due to operation of the semiconductor element 12 can be effectively dissipated. Therefore, a semiconductor package of high reliability can be provided. Further, extraneous electromagnetic noise such as EMI coming from outside the semiconductor package can be attenuated by the conductive plate 21 . In this case, the conductive plate 21 can be provided with a means of securing ground potential.
- FIG. 4 is a diagram showing diagrammatically a plan configuration of the semiconductor package illustrated in FIG. 1.
- the plane shapes of a wiring substrate 11 , a semiconductor element 12 and a mold layer 13 are almost square. In this plan view, since an under-fill 19 is disposed underneath the semiconductor element 12 , it is omitted in the figure.
- the length x of one side of the wiring substrate 11 is either equal with the length z of one side of a lower surface of the package or longer than that.
- the thickness of the semiconductor element 12 is desirable to be 0.2 to 0.8 mm, that of the wiring substrate 11 is 0.3 to 10.0 mm, that of the first resin layer of the mold layer 13 , that is, a spacing between the semiconductor element 12 and the wiring substrate 11 , is 0.01 to 0.2 mm, respectively.
- the ratio of an area of the mold layer 13 to a packaging area of the wiring substrate is preferable to be 5 to 100%. Further, the thickness of the mold layer 13 is desirable to be 50 to 300% of that of the wiring substrate.
- FIG. 5 is a diagram explaining a connection structure between a wiring substrate 11 and a semiconductor element 12 .
- the semiconductor element 12 is connected to the wiring substrate 11 through a conductive bump 16 .
- a connecting electrode 14 consisting of aluminum or the like is formed.
- a passivation film 22 such as oxide film and the like.
- a plating film 23 of such as copper or the like is formed, and thereon, for instance, a conductive bump 16 consisting of Pb—Sn solder is connected.
- a connecting pad 15 is formed, other than this is covered by a resist film 24 .
- a connecting electrode 17 is formed, the connecting electrode 17 is electrically connected to the connecting pad 15 through an interior wiring 25 of copper or the like formed inside the wiring substrate 11 .
- the connecting electrode 17 can be provided with a conductive bump and a solder ball.
- FIG. 6 is a diagram showing diagrammatically another example of a configuration of a semiconductor package of the present invention.
- this semiconductor package adopts a so-called over-coat structure, and a semiconductor element 12 is completely covered with a mold layer 13 .
- the thickness Hu of the under-fill filled in between the semiconductor element and the wiring substrate is extremely thin (for instance, approximately 0.2 mm or less). Accordingly, influence on the strain of the semiconductor package as a whole due to this portion is very small. Therefore, the thickness Hr of the resin layer is set as a thickness of a resin layer disposed on the second face of the semiconductor element. Further, the resin layer disposed as the under-fill and the resin layer sealing the semiconductor element as a whole may be constituted of different materials.
- the size of the semiconductor element 12 was set to 1 to 20 mm square, the thickness was set to 0.25 to 1.0 mm, the size of the wiring substrate 11 was set to 40 mm square, the thickness Hs was set to 0.2 to 1 mm, the coplarnarity of the semiconductor package was evaluated with these values through simulation. Incidentally, ( ⁇ c ⁇ Ec)/( ⁇ s ⁇ Es) was set approximately 1.6.
- the type of a semiconductor package shown in FIG. 6 also can be mounted on a mother board (cf. FIG. 14).
- FIG. 7 is a chart showing examples of results of this evaluation.
- Smax denotes a limit of the size of a board in which displacement of the strain of a semiconductor package becomes smaller than 80 ⁇ m. From this table, it is recognized that, in the case of the value of R being smaller than approximately 0.6, the size of the board of less than 40 mm square is required to suppress too much displacement of the strain. In addition, in the case of the value of R being larger than approximately 0.6, it is recognized that, even if the size of the board is made more than 40 mm square, the displacement of the strain can be suppressed smaller than 80 ⁇ m. When an actual error during manufacturing is estimated as approximately 20 ⁇ m, according to the present invention, the displacement of the strain of the semiconductor package could be suppressed smaller than 100 ⁇ m.
- FIG. 8 is a diagram explaining coplanality of the most lowest surface of the terminals.
- datum S is calculated based on the least square surface of the connecting terminals 17 or the solder balls 18 disposed on the wiring substrate 11 , the distance from this S to the most lowest point of each terminal is measured. Then, the maximum value of the measured values was made the coplanality y of the most lowest surface of the terminals.
- the semiconductor package of the present invention a semiconductor package of small deformity and of high coplanarity can be obtained. Further, when the semiconductor package of the present invention is packaged in a mother board, reliability can be improved.
- FIG. 9A and FIG. 9B are cross-sectional views of a molding die for resin sealing to be used for formation of a mold layer 13 .
- an upper mold 30 and a lower mold 32 are sealed to form a cavity 38 accommodating the semiconductor element 12 and the wiring substrate 11 thereon the semiconductor element 12 is mounted.
- an exhausting groove is formed on the upper mold 30 .
- a clearance 50 deeper than the exhausting groove is formed as a clearance for the preceding surface of the wiring substrate 11 .
- an exhausting valve 51 is disposed to seal the exhausting groove when a resin is injected into a cavity 38 .
- a pot 33 accommodating tablets of an epoxy resin is formed.
- a plunger 40 moves freely up and down therein. From the pot 33 to the cavity 38 , a resin path of a runner 34 and a gate 35 are formed.
- the semiconductor element 12 and the wiring substrate 11 are set in the lower mold 32 of the molding die (FIG. 9A).
- the tablets of the epoxy resin are supplied into the pot 33 .
- the semiconductor element 12 being disposed in close vicinity of the interior surface of the upper mold, is not over-coated, a semiconductor package of the present invention shown in FIG. 1 is formed.
- resin materials are selected, when thermal expansion coefficient, Young's modulus and thickness of the wiring substrate 11 are ⁇ s, Es and Hs, respectively, and thermal expansion coefficient, Young's modulus and thickness of the resin layer 13 are ⁇ r, Er and Hr, respectively, for the value of ( ⁇ r ⁇ Er ⁇ Hr)/( ⁇ s ⁇ Es ⁇ Hs) to be approximately 0.6 or more.
- a decompressing seal 37 of such as fluorinated rubber or the like is desirable to be disposed.
- the seal 37 is made to have a structure in which high vacuum can be obtained even in the case of being held only for several seconds with a gap of approximately 1 mm between the upper and the lower molds immediately before complete clamping.
- the cavity 38 is made a high vacuum of less than 10 Torr. Then, the molding die is completely clamped.
- the tablets of the resin 13 i moves through the runner 34 to the cavity 38 from the gate 35 .
- the tablets of the resin 13 i is supplied an appropriate amount of resin in advance into the pot 33 .
- a ring of Teflon or the like equivalent to a sealing member can be formed to meet the exterior shape of the plunger to the interior diameter of the pot.
- the ring is exchangeable, and a structure capable of exchanging with speed upon occurrence of attrition or the like is desirable.
- the gate 35 an inlet of a resin to be injected into the cavity 38 , is disposed in a part of an exterior circumference of a flip-chip type semiconductor package, however, in the case of being formed on the side surface, for instance, the gate can be formed with a width of one side of the semiconductor element 12 . Further, in order to prevent the resin from remaining on the wiring substrate 11 of the flip-chip type semiconductor package after molding, on the upper surface portion of the semiconductor element, a gate can be disposed.
- the resin 13 i is kept being pressurized under a pressure of approximately 1 to 20 MPa.
- the resin 13 i is kept pressurized until being free of void, after the resin is filled in uniformly between the wiring substrate 11 and the semiconductor element 12 , pressurizing is stopped.
- the molding die is cooled, thereby the resin is cured to seal the semiconductor element 12 to be a resin sealed body, the mold layer 13 consisting thereof is eliminated of superfluous resin, thus a flip-chip type semiconductor package is formed.
- the resin in short time, the resin can be filled in uniformly between the wiring substrate 11 and the semiconductor element 12 , and between the conductive bumps.
- the mold layer 13 of the semiconductor package of the present invention is a convex type in its cross-sectional structure, and has a protruded structure at the edge portion. Therefore, warp of the package can be reduced, and reliability to thermal stress can be heightened.
- the resin used by the transfer molding resins of low viscosity such as multi-functional epoxy resin and biphenyl type epoxy resin are used. Further, the particle diameter of the filler to be dispersed with the resin is suppressed at 45 ⁇ m or less when a gap between the wiring substrate 11 and the semiconductor element 12 .
- the thickness of the under-fill is 100 ⁇ m or less.
- the gap between a wiring substrate and a semiconductor element is approximately 50 to 100 ⁇ m.
- the particle diameter of the filler to be mixed with the resin is approximately 75 to 100 ⁇ m, the filler is clogged, accordingly can not be well filled in the gap between the wiring substrate and the semiconductor element.
- the thickness of the resin layer formed by transfer molding method is at least approximately 100 to 200 ⁇ m.
- the inventors have solved such problems by employing a resin of low viscosity type resin among multi-functional epoxy resin and biphenyl type epoxy resin and, in addition to this, by suppressing the diameter of the filler smaller than a gap between the wiring substrate 11 and the semiconductor element 12 .
- a resin of low viscosity type resin among multi-functional epoxy resin and biphenyl type epoxy resin and, in addition to this, by suppressing the diameter of the filler smaller than a gap between the wiring substrate 11 and the semiconductor element 12 .
- a resin of low viscosity as a binder, even if the diameter of the filler is controlled smaller, viscosity of the mixture thereof can be prevented from increasing.
- tablets contains about 80% by weight of filler (silica). Further, it is confirmed that tablets contains 90% by weight of filler has identical effect. It is not desirable to use those tablets contain less than 70% by weight in view of a hygroscopic property.
- FIG. 10 is a diagram explaining dependence of relation between coplanality of the most lowest surface of terminals of a semiconductor package and size of the mold layer on the thickness of the mold layer.
- FIG. 16 and FIG. 17 are diagrams for explaining coplanarity of a semiconductor package of the present invention.
- the degree of flexure of a semiconductor package is different each other in zone 1 , zone 2 , and zone 3 (FIG. 17).
- the shape of cross-section of a semiconductor package is a convex above arc in zone 1 , a convex below arc in zone 2 , and is a straight line in zone 3 .
- ⁇ i is a radius of curvature of zone i.
- x axis is situated so as to go through a contact point of 2 circles
- y axis is situated so as to go through a center of a circle 1 .
- Point A is one that the circle 1 intersects with the y axis.
- Y coordinate of the point A corresponds to the coplanarity of the zone 1 .
- This point corresponds to a center of the bottom surface (a surface of the side opposite to the surface where a semiconductor element 12 is mounted) of the wiring substrate 11 .
- Point B corresponds to a boundary of zone 2 and zone 3 , and is a point shifted by the length of zone 2 along the circumference of the circle 2 from the contact point of 2 circles. Further, the point B corresponds to an exterior edge of a portion where a resin layer 13 is formed on the wiring substrate 11 .
- the point C is the point where y coordinate of the circle 2 shows the minimum value.
- Point D is a point shifted by a length of zone 3 along a tangent line at the point B of the circle 2 and corresponds to an edge portion of the wiring substrate 11 .
- y 2 ⁇ 2 cos( ⁇ 2 ⁇ 1 /2) ⁇ 2 cos ⁇ 1 /2( ⁇ 2 > ⁇ 1 /2) or
- y 4 y 3 ⁇ a ⁇ sin( ⁇ 1 /2 ⁇ 2 /2)
- the point D is taken at the edge portion of the wiring substrate 11 , however, it can be taken as the lowest point of a ball 18 disposed at the most exterior portion.
- thermosetting type epoxy resin of thermal expansion coefficient of 20 to 40 ppm/K and of elasticity modulus of 2 to 13 GPa is adopted.
- the thickness of the wiring substrate 11 was set 0.4 to 1.2 mm.
- a semiconductor package in which a semiconductor element 12 of which the thickness is 0.25 to 0.75 mm was mounted on a wiring substrate 11 will be described.
- the length of one side (y) of the semiconductor element 12 is 20 mm, and the length of one side (x) of the wiring substrate 11 is 40 mm.
- the connecting terminals 17 and the solder balls 18 are arranged on the wiring substrate in a full grid of a matrix array. However, it is possible not to form the connecting terminals 17 and the solder balls 18 at a part of the matrix array.
- the vertical coordinate of FIG. 10 denotes warp of the package, that is, coplanality y (mm) of the most lowest surface of the terminals, and the horizontal coordinate denotes the size of the mold layer (z) (mm).
- the thickness of the mold layer Hr 0.695 mm and 1 mm relation between the size of the wiring substrate of the semiconductor package and the coplanality y (mm) of the most lowest surface of the terminals is simulated.
- the warp of the package decreases as the thickness of the mold layer increases, resulting in higher coplanality of the most lowest surface of the terminals. Further, with the increase of the package size (z), the warp of the package becomes small.
- thermosetting resin such as silicone resin, vinyl polymerization resin, phenolic resin, unsaturated polyester resin, diallyl phthalate resin, cyanate ester and acrylic resin can be employed.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Mechanical Engineering (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
In order to suppress the warp of a semiconductor package of an over-coat structure, when thermal expansion coefficient, Young's modulus and thickness of the wiring substrate are αs, Es and Hs, respectively, and thermal expansion coefficient, Young's modulus and thickness of the resin layer are αr, Er and Hr, respectively, the value R of (αr·Er·Hr)/(αs·Es·Hs) is set to be approximately 0.6 or more. With adoption of such a configuration, stress exerting on a semiconductor package can be effectively alleviated, and coplanarity of the semiconductor package can be improved.
Description
- 1. Field of the Invention
- The present invention relates to semiconductor devices such as semiconductor packages, particularly relates to thin and highly reliable semiconductor packages.
- 2. Description of the Related Art
- As electronic instruments become compact, development of a technology packaging various kinds of electronic components in high density into electronic instruments is being in progress. Further, upon packaging the electronic components with high density, the electronic components such as semiconductor packages and the like are desired to be made smaller and thinner. This is because, in order to realize a compact and highly functional electronic instrument, not only improvement of integration of a semiconductor element but also compactness of a semiconductor package in which a semiconductor element is packaged are required. In order to correspond to such a requirement, various types of thin semiconductor packages are being proposed.
- A means for mounting a semiconductor element on a wiring substrate can be generally divided into a face-up type bonding (wire bonding), and face-down type bonding (flip chip bonding).
- In the face-up type mounting, connecting electrodes of a semiconductor element and connecting electrodes of a wiring substrate are connected with bonding wires. Then, by molding the semiconductor element including the bonding wires on the wiring substrate, a semiconductor package is formed.
- On the other hand, in the face-down type mounting, connecting electrodes of a semiconductor element and connecting electrodes of a wiring substrate are connected with conductive bumps and the like.
- In the semiconductor package of the flip chip type, there are an over-coat type in which a semiconductor element is molded as a whole, and a bare chip type in which a semiconductor element is exposed. Even in the latter case, it is generally done to seal a gap between a semiconductor element and a wiring substrate with a resin and the like. Semiconductor packages of the flip chip type, because they can be made thinner than those of the face-up type, are recently used much in CSP (Chip Size Package) and the like. The CSPs are used much in, for instance, computers, semiconductor packages of high frequency and integrated function used in communication instruments, or portable information instruments such as a PDA.
- FIG. 11 is a diagram showing a structure of a conventional semiconductor package.
- In the
semiconductor package 90 illustrated in FIG. 11, a semiconductor element (chip) 92 is mounted in a face-down manner on awiring substrate 91. Connectingterminals 92 a of thesemiconductor element 92 and pads 93 disposed on thewiring substrate 91 are connected withconductive bumps 94. The conductive bumps are composed of, for instance, solder, gold and the like. - Further, a gap between the
wiring substrate 91 and thesemiconductor element 92 is sealed with aresin layer 95 called an under-fill. Here, a semiconductor package of a structure in which a rear surface of thesemiconductor 92 is exposed is illustrated, however, if thesemiconductor element 92 is covered with a molding resin as a whole, a semiconductor package of the over-coat structure can be obtained. - Further, on the rear surface of the semiconductor mounting surface of the
wiring substrate 91, connectingpads 96 connected to the bonding pads 93 are disposed, on the connectingpads 96solder balls 97 are disposed. Thosesolder balls 97 and theconductive bumps 94 are connected electrically with interior wiring. - In the
wiring substrate 91, glass fabric based epoxy resin is employed as an insulating layer. As thewiring substrate 91, that of two-layered structure is employed here, however, that of multi-layered structure such as three-layered structure or more may be employed. Further, on the rear surface (upper surface) of the semiconductor chip, a metallic cap or a heat-sink is disposed in some cases. - Further, the solder balls are disposed as BGA (ball grid array) type terminals. Incidentally, the connecting
terminals 96 to which thesolder balls 97 are disposed and the bonding pads 93 of the wiring substrate are connected between layers with, for instance, through holes, conductive pillars consisting of conductive resin and the like. - FIG. 12A, FIG. 12B and FIG. 12C are diagrams explaining a method forming a resin layer95 (under-fill).
- First, on the circumference of a
semiconductor element 92, aliquid resin 95 i such as epoxy resin or the like is supplied from adispense nozzle 99. Viscosity of the resin is selected and adjusted according to demands. Thedispense nozzle 99 is attached to a syringe in which theresin 95 i is stocked. Theresin 95 i permeates into a gap between thewiring substrate 91 and thesemiconductor element 92 due to capillary action (FIG. 12A). That is, theresin 95 i supplied from thedispense nozzle 99 is dripped on the circumference of the wiring substrate 91 (FIG. 12B), then the dripped resin permeates into the gap between thewiring substrate 91 and the semiconductor element 92 (FIG. 12C), thus the under-fill is formed thereby. - However, such a thin semiconductor package as described above has a problem described in the following. That is, in order to reduce thickness of a semiconductor package as a whole, strength is sacrificed, accordingly the semiconductor package is liable to suffer deformation such as warp and the like.
- When such a warp of the semiconductor package occurs, the connecting
terminals 96 and thesolder balls 97 constituting the BGA, for instance, are not arranged on the same plane, to deteriorate so-called coplanarity. Therefore, there occur such problems that a semiconductor package is made impossible to be packaged on a mother board, or, even after packaging, in the course of time, due to the added thermal load and the like, reliability of connection can not be maintained. Therefore, in the case of a thin semiconductor package being used actually, how to improve productivity and reliability is a problem to be solved. - In the manufacturing steps of a semiconductor package of flip-chip type such as aforementioned, in the step of forming a
resin layer 95, the liquid resin is cured thermally in the temperature range of 100 to 180° C. Therefore, in the course of returning to room temperature, the semiconductor package suffers warp. - Thermal expansion coefficient of a semiconductor element and that of a wiring substrate differ approximately one digit in general. The thermal expansion coefficient of a semiconductor element (chip) consisting of silicon, for instance, is about 3-4 ppm/K, whereas the thermal expansion coefficient of a wiring substrate having an organic insulating layer such as FR-4, FR-5 or BT resin (Bis maleimide triazine) is about 12 to 20 ppm/K. Therefore, deformation due to thermal load is larger for the wiring substrate than that of the semiconductor chip. Therefore, stress pulling the
semiconductor element 92 occurs, due to this stress, the semiconductor package suffers warp. - FIG. 13A, FIG. 13B and FIG. 13C are diagrams explaining stress suffered by a semiconductor package. Here, appearance of chip crack and resin crack observed in TCT (Thermal Cycle Test) which is a generally adopted environment test of semiconductor package is shown schematically.
- In this test, a so-called fan-in type semiconductor package, in which a
wiring substrate 91 is smaller than asemiconductor element 92, was employed. - On a
wiring substrate 91 is mounted asemiconductor element 92, aresin layer 95 is filled in a gap formed between thewiring substrate 91 and the semiconductor element. In general, compared with thicknesses of thewiring substrate 91 andsemiconductor element 92, that of an under-fill resin layer 95 is extremely thin. - When the aforementioned thermal load is added on such a semiconductor package, on the rear surface side of the
semiconductor element 92 a tensile stress works, due to this stress chip crack occurs (FIG. 13A, FIG. 13B). - Further, even in the case of stiffness of the chip enduring the stress, due to the stress working in a direction to peel a semiconductor element and a wiring substrate, fillet crack occurs (FIG. 13C). Thus, in any cases, due to bimetal structure, warp occurs.
- Displacement of warp of a semiconductor package after an under-fill is formed is desirable to be suppressed at 100 μm or less at most, preferable to be 80 μm or less. Further, the displacement of the warp of the semiconductor package is further desirable to be suppressed approximately 50 to 70 μm or less. That is implemented so that there does not occur any inconvenience when
solder balls 97 or caps are attached after the under-fill is formed, or package coplanarity guaranty (ordinarily the maximum of 100 μm) is to be satisfied. - For instance, according to the result of simulation of the displacement of the warp caused when a semiconductor element of 20 mm square is mounted on a multi-layered wiring substrate on which a BT of a thickness of 0.8 mm is employed as an insulating layer, approximately 89 μm of displacement of warp is for a chip of a thickness of 0.3 mm, approximately 77 μm for a chip of a thickness of 0.45 mm, and approximately 62 μm for a chip of a thickness of 0.625 mm.
- The above described calculation of the coplanarity of the semiconductor package was carried out under the following conditions.
- Thermal expansion coefficient of the semiconductor element αc: 3.5 [ppm/K],
- modulus of elasticity of the semiconductor element: 166 [GPa],
- thermal expansion coefficient of resin layer (under-fill): 26 [ppm/K],
- modulus of elasticity of the resin layer (under-fill): 10 [GPa},
- thermal expansion coefficient of the wiring substrate: 14.6 [ppm/K],
- modulus of elasticity of the substrate: 24 [GPa], and
- temperature difference between cure temperature (150° C.) and room temperature (25° C.): 125° C.
- First, radius of curvature ρ is calculated as follows.
- FIG. 15 is a diagram for explaining flexure of a multi-layer composite beam.
- Here,
- t is a coordinate between t(i+1) and t(i) and corresponds to a displacement in the direction of the thickness of the semiconductor package.
- Here,
- t1: front surface of resin layer of overcoat (t1=0),
- t2: a boundary between the resin layer of the overcoat and the semiconductor element,
- t3: a boundary between the semiconductor element and the resin layer of the under-fill,
- t4: a boundary between the resin layer of the under-fill and the wiring substrate,
- t5: bottom surface of the wiring substrate.
- Further,
- αi: thermal expansion coefficient of the layer i,
- Ei: modulus of elasticity of the layer i,
- σi thermal stress thereto the layer i is subjected,
- εi thermal strain (displacement) of the layer i,
- (t−δ)/ρ: distortion (displacement) due to flexure of the i-th layer,
- δi: coordinate of a neutral line,
- ρ: radius of curvature.
- Here, σi and εi can be expressed with the following equations.
- σi=[εi+(t−δ)/ρ]Ei
- εi=[ΣE J(t J+1 −t j)(αj−α1)ΔT]/ΣE J(t J+1 −t J)
- The neutral line δ and the radius of curvature ρ are expressed, respectively, by
- δ=T/S,ρ=U/S.
- Therefore,
- S=−6[ΣE jεJ(t J+1 −t J)·ΣE J(tj+1 2 −t j 2)−ΣE Jεj(tJ+1 2 −t j 2)·ΣE J(tJ+1 −t j)],
- T=−4ΣE jεj(t j+1 −t J)·ΣE J(t j+1 3 −t J 3)+3ΣE jεJ(tj+1 2 −t j 2)·ΣE j(t j+1 2 −t J 2), and
- U=3[ΣE J(t j+1 2 −t j 2)]2−4ΣE j(t j+1 3 −t j 3)·ΣE J(t J+1 −t j).
- From the above, the coplanarity of a semiconductor package becomes
- ρ−ρcos(L/ρ/2)(L is the length of one side of semiconductor package).
- When considered dimensional tolerance, approximately 20 μm of allowance is necessary. Therefore, a chip of a standard size of flip-chip (thickness: 0.3 to 0.625 mm) becomes too large in its warp to be capable of securing sufficient accuracy.
- Thus, due to discrepancy of the thermal expansion coefficients of constituent elements of a semiconductor package, there occur problems such as destruction and peeling of the semiconductor element, destruction and peeling of the under-fill, or lowering of coplanarity of the semiconductor package. Such problems are becoming problematic as a semiconductor package becomes thinner.
- Another problem of the flip-chip type semiconductor package is in its difficulty of securing heat releasing path for a semiconductor element. In the case of a semiconductor element being mounted on a wiring substrate in a face-up way, a rear surface of the semiconductor element (the surface opposite to the surface where integrated circuit is formed) is connected onto die pads of the wiring substrate. Therefore, heat from the semiconductor element can be released to the wiring substrate side.
- Whereas, in the case of a semiconductor package of the flip-chip type, heat generated by the semiconductor can not be released easily towards the wiring substrate side. This is because connection between the semiconductor element and the wiring substrate is implemented with fine conductive bumps, and because resin of small thermal conductivity is filled in the gap between the semiconductor element and the wiring substrate.
- Therefore, in a semiconductor package of flip-chip type suitable for high density packaging, a technology enabling enhancement of heat release efficiency of a semiconductor element is in strong demand.
- The present invention was carried out to solve these problems. That is, an object of the present invention is to provide a semiconductor package which is thin, compact and highly reliable. Further, another object of the present invention is to provide a thin semiconductor package of high connection reliability. Still another object of the present invention is to provide a semiconductor package of a structure suitable for high density packaging.
- In order to solve such problems, a semiconductor package of the present invention adopts such a configuration as described below.
- The first aspect of a semiconductor package of the present invention comprises, a wiring substrate having a first face and a second face, the first face having a first area and a second area surrounds the first area, and at least a first connecting pad arranged in the first area; a semiconductor element having a first face and a second face, the semiconductor element having at least a connecting terminal formed on the first face, and the semiconductor element being mounted on the first area of the wiring substrate in a face-down type; at least a conductive bump connecting the first connecting pad of the wiring substrate and the connecting terminal of the semiconductor element; and, a resin layer disposed on the first face of the wiring substrate, the resin layer disposed so that the second face of the semiconductor element being exposed, side faces of the semiconductor element being sealed, and a gap between the first face of the wiring substrate and the first face of the semiconductor element being filled.
- It is also possible to comprises a wiring substrate which has a first face having a first area thereon a first connecting pads are disposed and a second area in the circumference of the first area and a second face; a semiconductor element which has a first face thereon connecting terminals are disposed and a second face, and is mounted in a face-down way on the first area of the first face of the wiring substrate; conductive bumps connecting the first connecting pads of the wiring substrate and connecting terminals of the semiconductor element; and a resin layer for sealing disposed such that the second face of the semiconductor element is exposed, and side surface of the semiconductor element is covered, and the resin layer fills a gap between the semiconductor element and the wiring substrate.
- In the semiconductor package of the present invention, the resin layer for sealing may have a first face substantially in parallel with the first face of the wiring substrate, in addition, may be disposed such that the first face of the resin layer for sealing and the second face of the semiconductor element are substantially in a same plane.
- In addition, the resin layer for sealing may be inclined in its side faces, and, at the same time, the first face of the wiring substrate can be made larger than the first face of the resin layer for sealing.
- Further, the resin layer for sealing may be disposed so that it covers substantially the second area of the first face of the wiring substrate.
- The semiconductor package of the present invention may further comprise a conductive plate on the second face of the semiconductor element. By disposing such a configuration, a heat releasing path of the semiconductor element can be secured. Therefore, reliability of the semiconductor package can be improved. Further, thermal load being put on the semiconductor package can be alleviated. Therefore, the stress generated due to discrepancy and the like of thermal expansion coefficients of the constituent elements such as a semiconductor element, a resin layer for sealing and a wiring substrate on the semiconductor package, can be alleviated. Therefore, a thin semiconductor package of high dimensional accuracy can be provided.
- It is desirable to connect the conductive plate and the second face of the semiconductor element with a conductive resin. Since the conductive resin is high in its thermal conductivity, the heat of the semiconductor element can be effectively released outsides.
- Further, the resin layer for sealing may be disposed such that it covers the side faces of the conductive plate. That is, with the resin layer for sealing, the conductive plate may be fixed. In this case, it is desirable from the view-point of securing heat releasing path to dispose the sealing resin layer with the conductive plate exposed.
- Incidentally, the second face of the semiconductor element may be disposed with not only the conductive plate but also a heat releasing plate with a heat-sink, for instance.
- The second aspect of a semiconductor package of the present invention comprises, a wiring substrate having a first face and a second face, the substrate having at least a first connecting pad formed on the first face; a semiconductor element having a first face and a second face, the semiconductor element having at least a connecting terminal formed on the first face, and the semiconductor element being mounted on the first area of the wiring substrate in a face-down type; at least a conductive bump connecting the first connecting pad of the wiring substrate and the connecting terminal of the semiconductor element; and, a resin layer disposed on the first face of the wiring substrate and the second face of the semiconductor element so that the semiconductor element being sealed; wherein, (αr·Er·Hr)/(αs·Es·Hs) is approximately 0.6 or more, when αr is a thermal expansion coefficient of the resin layer, Er is a Young's modulus if the resin layer, Hr is a thickness of the resin layer, αs is a thermal expansion coefficient of the wiring substrates, Es is a Young's modulus of the wiring substrate and Hs is a thickness of the wiring substrates.
- It is also possible to comprise a wiring substrate having a first face thereon a first connecting pads are disposed and a second face; a semiconductor element which has a first face thereon connecting terminals are disposed and a second face, and is mounted in a face-down way on the first face of the wiring substrate; conductive bumps connecting the first connecting pads of the wiring substrate and the connecting terminals of the semiconductor element; and a resin layer disposed on the first face of the wiring substrate in such a manner that seals the semiconductor element; wherein, when thermal expansion coefficient, Young's modulus and thickness of the wiring substrate is αs, Es and Hs, respectively, and thermal expansion coefficient, Young's modulus and thickness of the resin layer is αr, Er and Hr, respectively, (αr·Er·Hr)/(αs·Es·Hs) is approximately 0.6 or more.
- When thermal expansion coefficient and Young's modulus of the semiconductor is αc, Ec, respectively, (αc·Ec)/(αs·Es) may be designed to be approximately 1.5 or more.
- The present inventors found that, by adjusting thermal expansion coefficient αs, Young's modulus Es and thickness Hs of the wiring substrate, and, thermal expansion coefficient αr, Young's modulus Er and thickness Hr of the resin layer, the stress being put on the semiconductor package can be effectively alleviated. The present invention is based on such findings.
- That is, when thermal expansion coefficient, Young's modulus and thickness of the wiring substrate are αs, Es and Hs, respectively, and thermal expansion coefficient, Young's modulus and thickness of the resin layer are αr, Er and Hr, respectively, by setting respective parameters for the value of (αr·Er·Hr)/(αs·Es·Hs) to be approximately 0.6 or more, a semiconductor package of small deformation and high coplanarity can be obtained. Further, reliability during packaging a semiconductor package of the present invention on a mother substrate can be enhanced.
- Incidentally, the thickness of a resin layer (under-fill) filled in between a semiconductor element and a wiring substrate is ordinarily extremely thin (for instance, approximately 0.2 mm or less). Therefore, this part exerts very slight influence on the distortion of the whole semiconductor package. Therefore, the thickness Hr of the resin layer is set as a thickness of the resin layer disposed on the second face of the semiconductor element. Further, the resin layer disposed as the under-fill and the resin layer sealing the whole semiconductor element can be composed of different materials.
- For instance, the resin layer for sealing may be divided into a first portion filled in between the wiring substrate and the semiconductor element and a second portion covering the semiconductor element from above the second face of the semiconductor element, and the first portion may be constituted of a resin layer of smaller Young's modulus than that of the second portion. By adopting such a constitution, a soft resin can be disposed in the circumference of the conductive bumps, thereby deformation and rupture of the conductive bumps can be prevented from occurring. Therefore, a semiconductor package of high reliability and high productivity can be provided.
- The third aspect of a manufacturing method of a semiconductor package of the present invention comprises, a step of mounting a semiconductor element on a first face of a wiring substrate, a first face of the semiconductor having at least a connecting terminal, the first face of the wiring substrate having at least a first connecting pad, the connecting terminal of the semiconductor element being connected by a conductive bump; and a step of forming a resin layer on the first face of the wiring substrate so that the semiconductor element is sealed; wherein, αr, Er, Hr, αs, Es, Hs are arranged so that (αr·Er·Hr)/(αs·Es·Hs) is approximately 0.6 or more, when αr is a thermal expansion coefficient of the resin layer, Er is a Young's modulus if the resin layer, Hr is a thickness of the resin layer, αs is a thermal expansion coefficient of the wiring substrates, Es is a Young's modulus of the wiring substrate and Hs is a thickness of the wiring substrates.
- It is preferable to adjust αr, Er, or Hr of the resin so as to meet the equation.
- The step of forming the resin layer can be carried out with transfer molding in which, after setting a wiring substrate mounted a semiconductor element thereon in a cavity, resin is supplied to be cured. Further, in this case, the resin layer may be supplied under pressure, and, at the same time, curing can be carried out thermally.
- Further, with tablets of a resin of low melt viscosity such as epoxy based resin, the resin layer may be formed with transfer mold method.
- The semiconductor package of the present invention may be provided with a sealing resin body consisting of a first resin layer filling a gap between a first face thereon conductive bumps of a semiconductor element are formed and a main surface of a wiring substrate, and a second resin layer which contacts at least circumference of a semiconductor element, and is formed so as to surround the semiconductor element.
- A semiconductor package of the present invention comprises at least one semiconductor element having conductive bumps; a wiring substrate the main surface thereof is electrically connected to the semiconductor element through the conductive bumps; and a sealing resin formed on the main surface of the wiring substrate; wherein the sealing resin may be constituted of a first resin layer filling a gap between a first face thereon the conductive bumps of the semiconductor element are formed and the main surface of the wiring substrate, and a second resin layer contacting at least circumference of the semiconductor element and formed so as to surround the semiconductor element.
- Further, according to the manufacturing method of the present invention, in a manufacturing method of the flip-chip type semiconductor package, to a gap between a wiring substrate accommodated in a cavity of a molding die and a semiconductor element connected thereon, and on exterior circumference thereof, a liquid resin is injected under pressure by a transfer method or an injection molding method, by curing this, the sealing resin is formed.
- Incidentally, the present invention can be applied to various kinds of semiconductor packages and semiconductor devices. For instance, the semiconductor package of the present invention also includes an MCM (multi-chip module). In addition, as a semiconductor element to be mounted, a CPU, a DSP, various kinds of memory chips including a flash type non-volatile semiconductor memory, or a composite chip thereof can be cited.
- FIG. 1 is a diagram showing diagrammatically one example of a configuration of a semiconductor package of the present invention;
- FIG. 2 is a diagram showing diagrammatically another example of a configuration of a semiconductor package of the present invention;
- FIG. 3 is a diagram showing diagrammatically another example of a configuration of a semiconductor package of the present invention;
- FIG. 4 is a diagram showing diagrammatically a plan configuration of the semiconductor package illustrated in FIG. 1;
- FIG. 5 is a diagram explaining a connection structure of a wiring substrate and a semiconductor element;
- FIG. 6 is a diagram showing diagrammatically another example of a configuration of a semiconductor package of the present invention;
- FIG. 7 is a chart showing results of coplanarity of a semiconductor package evaluated by simulation;
- FIG. 8 is a diagram explaining coplanarity of the most lowest surface of terminal;
- FIG. 9A and FIG. 9B are cross-sectional views of a molding die used for resin sealing for formation of a
mold layer 13; - FIG. 10 is a diagram explaining dependence of relation between coplanality of the most lowest surface of the terminals of a semiconductor package and size of the mold layer on the thickness of the mold layer;
- FIG. 11 is a diagram diagrammatically showing a structure of a conventional semiconductor package;
- FIG. 12A, FIG. 12B and FIG. 12C are diagrams explaining a method of forming a resin layer95 (under-fill); and
- FIG. 13A, FIG. 13B and FIG. 13C are diagrams explaining stress exerted on a semiconductor package.
- FIG. 14 is a diagram diagrammatically showing a structure of an electronic device having a mother wiring substrate the semiconductor package of the present invention being mounted;
- FIG. 15 is a diagram for explaining a warping of a multi-layered lamination.
- FIG. 16 and FIG. 17 are diagrams for explaining coplanarity of a semiconductor package of the present invention.
- (Embodiment 1)
- FIG. 1 is a diagram showing an example of a configuration of a semiconductor package of the present invention.
- The
semiconductor package 10 comprises awiring substrate 11 having a wiring layer on a first face and another wiring layer on a second face, asemiconductor element 12 mounted on the first face of thewiring substrate 11, and amold layer 13 which is disposed on the first face, where the semiconductor element being mounted on. The mold layer is consisting of a resin. Thismold layer 13 is disposed such that a rear surface of asemiconductor element 12 is exposed. - The
semiconductor element 12 is mounted in a face-down manner on awiring substrate 11. That is, between connectingterminals 14 of thesemiconductor element 12 and connectingpads 15 disposed as a part of wiring pattern of the wiring substrate, theconductive bumps 16 are disposed. Theconductive bumps 16 may be constituted of such as solder or gold, for instance. With theconductive bumps 16, thesemiconductor element 12 and thewiring substrate 11 are connected electrically and mechanically. - On the other hand, on the second face of the
wiring substrate 11, connectingterminals 17 are disposed, and on the connectingterminals 17,solder balls 18 are arranged in array. That is, thesemiconductor package 10 is a semiconductor package of a BGA type. Incidentally, connectingterminals wiring substrate 11 are connected through the interconnection such as through holes, conductive pillars and the like, for instance. - Here, in the
wiring substrate 11, for instance, a glass cloth is used as a base material and therein organic material such as BT (Bis-maleimide Triazine) resin or epoxy resin is impregnated and is cured, the resultant cured resin polymer is adopted as an insulating layer. Further, themold layer 13 is formed of epoxy based polymer, for instance. - FIG. 14 is a diagram diagrammatically showing a structure of an electronic device having a mother wiring substrate the semiconductor package of the present invention being mounted. The semiconductor package of the invention having a high coplanality, therefore, a reliability of the electronic device is promoted.
- FIG. 2 is a diagram showing diagrammatically another example of a semiconductor package of the present invention.
- In this semiconductor package, in a gap between a
wiring substrate 11 and asemiconductor element 12, under-fill 19 consisting of a resin of a smaller Young's modulus than that constituting themold layer 13 is filled. - By adopting such a configuration, a relatively soft resin can be disposed on the circumference of the conductive bumps16. Thereby, the stress exerting on the
conductive bumps 16 can be alleviated, accordingly reliability of connection between thewiring substrate 11 and thesemiconductor element 12 can be promoted. - When a semiconductor package of the present invention is constituted with the aforementioned configuration, coplanality of the
wiring substrate 11 was excellent. Therefore, upon mounting on a mother substrate, for instance, coplanarity of the connectingterminals 17 disposed in a ball grid array type was also excellent, accordingly connection of reliability could be enhanced. - FIG. 3 is a diagram showing diagrammatically another example of a semiconductor package of the present invention. This semiconductor package is a modification example of the semiconductor packages illustrated in FIG. 1 and FIG. 2.
- In this semiconductor package, a
conductive plate 20 is disposed on a rear face of a main face of asemiconductor element 12. Main face is where an integrated circuit being formed. This conductive plate is composed of conductive materials consisting of Cu, 42 alloy, SUS, Ti, Fe, Ni and alloy materials mainly consisting thereof, for instance. Thisconductive plate 20 is adhered to the rear surface of thesemiconductor element 12 with an adhesive layer 21 therein filler is dispersed. As an adhesive layer, one in which silver is dispersed as a filler is desirable, one in which silver is dispersed in high density is more desirable. For instance, SG-2105S (product of Ablestick Co,), DM4030HK (product of Diemat Co,) may be preferably employed. As a filler material being dispersed in a binder resin other than silver, aluminum hydroxide, alumina, silicon carbide, silica and the like can be cited, for instance. - By adopting such a configuration, a semiconductor package of the present invention can be made small in its deformation and extremely high in its flatness, at the same time, due to the
conductive plate 20, heat due to operation of thesemiconductor element 12 can be effectively dissipated. Therefore, a semiconductor package of high reliability can be provided. Further, extraneous electromagnetic noise such as EMI coming from outside the semiconductor package can be attenuated by the conductive plate 21. In this case, the conductive plate 21 can be provided with a means of securing ground potential. - FIG. 4 is a diagram showing diagrammatically a plan configuration of the semiconductor package illustrated in FIG. 1. The plane shapes of a
wiring substrate 11, asemiconductor element 12 and amold layer 13 are almost square. In this plan view, since an under-fill 19 is disposed underneath thesemiconductor element 12, it is omitted in the figure. - The length x of one side of the
wiring substrate 11 is either equal with the length z of one side of a lower surface of the package or longer than that. The thickness of thesemiconductor element 12 is desirable to be 0.2 to 0.8 mm, that of thewiring substrate 11 is 0.3 to 10.0 mm, that of the first resin layer of themold layer 13, that is, a spacing between thesemiconductor element 12 and thewiring substrate 11, is 0.01 to 0.2 mm, respectively. The ratio of an area of themold layer 13 to a packaging area of the wiring substrate is preferable to be 5 to 100%. Further, the thickness of themold layer 13 is desirable to be 50 to 300% of that of the wiring substrate. - FIG. 5 is a diagram explaining a connection structure between a
wiring substrate 11 and asemiconductor element 12. - The
semiconductor element 12 is connected to thewiring substrate 11 through aconductive bump 16. On a surface of thesemiconductor element 12 where an integrated circuit is formed, a connectingelectrode 14 consisting of aluminum or the like is formed. Of the surface of the semiconductor element thereon an integrated circuit is formed, other region than that thereon the connectingelectrode 14 is formed is covered and protected by apassivation film 22 such as oxide film and the like. On the surface of the connectingelectrode 14, aplating film 23 of such as copper or the like is formed, and thereon, for instance, aconductive bump 16 consisting of Pb—Sn solder is connected. On the other hand, on the surface of thewiring substrate 11, a connectingpad 15 is formed, other than this is covered by a resistfilm 24. On the rear surface of thewiring substrate 11, a connectingelectrode 17 is formed, the connectingelectrode 17 is electrically connected to the connectingpad 15 through aninterior wiring 25 of copper or the like formed inside thewiring substrate 11. The connectingelectrode 17 can be provided with a conductive bump and a solder ball. With such a configuration, signals from the integrated circuit formed on thesemiconductor element 12 or signals entering the integrated circuit are inputted/outputted to/from the exterior circuits. - (Embodiment 2)
- FIG. 6 is a diagram showing diagrammatically another example of a configuration of a semiconductor package of the present invention.
- The principal structure of this semiconductor package is identical as that of the aforementioned one. However, this semiconductor package adopts a so-called over-coat structure, and a
semiconductor element 12 is completely covered with amold layer 13. - And, in this semiconductor package, when thermal expansion coefficient, Young's modulus and thickness of the wiring substrate are αs, Es and Hs, respectively, and thermal expansion coefficient, Young's modulus and thickness of the resin layer are αr, Er and Hr, respectively, the value R of (60 r·Er·Hr)/(αs·Es·Hs) is set to be approximately 0.6 or more. Further, when thermal expansion coefficient and Young's modulus of the semiconductor are αc, Ec, respectively, (αc·Ec)/(αs·Es) is set to be approximately 1.5 or more. By adopting such a configuration, the stress exerting on the semiconductor device such as a semiconductor package and the like can be effectively alleviated.
- Incidentally, in general, among resin layers, the thickness Hu of the under-fill filled in between the semiconductor element and the wiring substrate is extremely thin (for instance, approximately 0.2 mm or less). Accordingly, influence on the strain of the semiconductor package as a whole due to this portion is very small. Therefore, the thickness Hr of the resin layer is set as a thickness of a resin layer disposed on the second face of the semiconductor element. Further, the resin layer disposed as the under-fill and the resin layer sealing the semiconductor element as a whole may be constituted of different materials.
- In the semiconductor package illustrated in FIG. 6, the size of the
semiconductor element 12 was set to 1 to 20 mm square, the thickness was set to 0.25 to 1.0 mm, the size of thewiring substrate 11 was set to 40 mm square, the thickness Hs was set to 0.2 to 1 mm, the coplarnarity of the semiconductor package was evaluated with these values through simulation. Incidentally, (αc·Ec)/(αs·Es) was set approximately 1.6. - The type of a semiconductor package shown in FIG. 6 also can be mounted on a mother board (cf. FIG. 14).
- FIG. 7 is a chart showing examples of results of this evaluation.
- Smax denotes a limit of the size of a board in which displacement of the strain of a semiconductor package becomes smaller than 80 μm. From this table, it is recognized that, in the case of the value of R being smaller than approximately 0.6, the size of the board of less than 40 mm square is required to suppress too much displacement of the strain. In addition, in the case of the value of R being larger than approximately 0.6, it is recognized that, even if the size of the board is made more than 40 mm square, the displacement of the strain can be suppressed smaller than 80 μm. When an actual error during manufacturing is estimated as approximately 20 μm, according to the present invention, the displacement of the strain of the semiconductor package could be suppressed smaller than 100 μm.
- Actual measurement of the displacement of the strain of the semiconductor package was carried out according to the measurement method of coplanality of the lowest surfaces of the terminals defined in EIAJ ED-7304.
- FIG. 8 is a diagram explaining coplanality of the most lowest surface of the terminals. First, measure the distance from calculate datum S based on least square method (LSM) to the lowest point of every solder ball. Coplanality of the solder balls y to be the maximum value of the measured distance. In other word, datum S is calculated based on the least square surface of the connecting
terminals 17 or thesolder balls 18 disposed on thewiring substrate 11, the distance from this S to the most lowest point of each terminal is measured. Then, the maximum value of the measured values was made the coplanality y of the most lowest surface of the terminals. - As the result of the measurement, it is confirmed that, in the semiconductor package wherein the present invention is applied, the uniformity y of the most lowest surface of the terminals became less than 100 μm, thus the coplanarity was maintained high.
- Thus, according to the semiconductor package of the present invention, a semiconductor package of small deformity and of high coplanarity can be obtained. Further, when the semiconductor package of the present invention is packaged in a mother board, reliability can be improved.
- (Embodiment 3)
- Here, a manufacturing method of a semiconductor package of the present invention will be outlined. Here, formation of molding resin due to transfer mold method will be described.
- FIG. 9A and FIG. 9B are cross-sectional views of a molding die for resin sealing to be used for formation of a
mold layer 13. In the molding die, anupper mold 30 and alower mold 32 are sealed to form a cavity 38 accommodating thesemiconductor element 12 and thewiring substrate 11 thereon thesemiconductor element 12 is mounted. In the vicinity of the cavity 38, an exhausting groove is formed on theupper mold 30. Preceding the exhausting groove, aclearance 50 deeper than the exhausting groove is formed as a clearance for the preceding surface of thewiring substrate 11. In the exhausting groove, anexhausting valve 51 is disposed to seal the exhausting groove when a resin is injected into a cavity 38. - In the
lower mold 32, apot 33 accommodating tablets of an epoxy resin is formed. In thepot 33, aplunger 40 moves freely up and down therein. From thepot 33 to the cavity 38, a resin path of arunner 34 and agate 35 are formed. - During molding, the
semiconductor element 12 and thewiring substrate 11 are set in thelower mold 32 of the molding die (FIG. 9A). The tablets of the epoxy resin are supplied into thepot 33. Thesemiconductor element 12, being disposed in close vicinity of the interior surface of the upper mold, is not over-coated, a semiconductor package of the present invention shown in FIG. 1 is formed. - Here, resin materials are selected, when thermal expansion coefficient, Young's modulus and thickness of the
wiring substrate 11 are αs, Es and Hs, respectively, and thermal expansion coefficient, Young's modulus and thickness of theresin layer 13 are αr, Er and Hr, respectively, for the value of (αr·Er·Hr)/(αs·Es·Hs) to be approximately 0.6 or more. - In order to obtain a cavity of a space of high vacuum, in the circumference of the molding die, a decompressing
seal 37 of such as fluorinated rubber or the like is desirable to be disposed. In order to make short the access time for attaining high vacuum, theseal 37 is made to have a structure in which high vacuum can be obtained even in the case of being held only for several seconds with a gap of approximately 1 mm between the upper and the lower molds immediately before complete clamping. - The tablets of the resin13 i in the
pot 33 are pressed by aplunger 40 to push up the exhausting valve 41, resulting in sealing of the exhausting groove. - In order to implementing molding, first, before complete clamping, the cavity38 is made a high vacuum of less than 10 Torr. Then, the molding die is completely clamped.
- The tablets of the resin13 i moves through the
runner 34 to the cavity 38 from thegate 35. The tablets of the resin 13 i is supplied an appropriate amount of resin in advance into thepot 33. In order to make the gap between the pot and the plunger as small as possible, on the exterior surface of the plunger, a ring of Teflon or the like equivalent to a sealing member can be formed to meet the exterior shape of the plunger to the interior diameter of the pot. The ring is exchangeable, and a structure capable of exchanging with speed upon occurrence of attrition or the like is desirable. - The
gate 35, an inlet of a resin to be injected into the cavity 38, is disposed in a part of an exterior circumference of a flip-chip type semiconductor package, however, in the case of being formed on the side surface, for instance, the gate can be formed with a width of one side of thesemiconductor element 12. Further, in order to prevent the resin from remaining on thewiring substrate 11 of the flip-chip type semiconductor package after molding, on the upper surface portion of the semiconductor element, a gate can be disposed. - The resin13 i is kept being pressurized under a pressure of approximately 1 to 20 MPa. The resin 13 i is kept pressurized until being free of void, after the resin is filled in uniformly between the
wiring substrate 11 and thesemiconductor element 12, pressurizing is stopped. - Thereafter, the molding die is cooled, thereby the resin is cured to seal the
semiconductor element 12 to be a resin sealed body, themold layer 13 consisting thereof is eliminated of superfluous resin, thus a flip-chip type semiconductor package is formed. - According to this filling method of resin, in short time, the resin can be filled in uniformly between the
wiring substrate 11 and thesemiconductor element 12, and between the conductive bumps. - The
mold layer 13 of the semiconductor package of the present invention is a convex type in its cross-sectional structure, and has a protruded structure at the edge portion. Therefore, warp of the package can be reduced, and reliability to thermal stress can be heightened. - Incidentally, here, as the resin used by the transfer molding, resins of low viscosity such as multi-functional epoxy resin and biphenyl type epoxy resin are used. Further, the particle diameter of the filler to be dispersed with the resin is suppressed at 45 μm or less when a gap between the
wiring substrate 11 and thesemiconductor element 12. - There are many cases where the thickness of the under-fill is 100 μm or less. In the case of C4 flip chip of being now popular, the gap between a wiring substrate and a semiconductor element is approximately 50 to 100 μm. When the particle diameter of the filler to be mixed with the resin is approximately 75 to 100 μm, the filler is clogged, accordingly can not be well filled in the gap between the wiring substrate and the semiconductor element. In addition, if the particle diameter of the filler is made small, viscosity of a mixture of the resin and the filler becomes large, again the gap between the wiring substrate and the semiconductor can not be filled. Therefore, the thickness of the resin layer formed by transfer molding method is at least approximately 100 to 200 μm.
- The inventors have solved such problems by employing a resin of low viscosity type resin among multi-functional epoxy resin and biphenyl type epoxy resin and, in addition to this, by suppressing the diameter of the filler smaller than a gap between the
wiring substrate 11 and thesemiconductor element 12. In this example, in a distribution of the diameter, there is a cut off around 45 μm so that the diameters of the filler being smaller than a gap between the wiring substrate and the semiconductor element. By employing a resin of low viscosity as a binder, even if the diameter of the filler is controlled smaller, viscosity of the mixture thereof can be prevented from increasing. Therefore, with the transfer molding method, even into the gap between the wiring substrate and the semiconductor element, resin layer for sealing can be formed. Further, according to such a method, the under-fill can be integrally formed in a forming step of the resin layer for sealing of the other portion. Therefore, productivity of semiconductor packages can be remarkably improved. - In this example, tablets contains about 80% by weight of filler (silica). Further, it is confirmed that tablets contains 90% by weight of filler has identical effect. It is not desirable to use those tablets contain less than 70% by weight in view of a hygroscopic property.
- FIG. 10 is a diagram explaining dependence of relation between coplanality of the most lowest surface of terminals of a semiconductor package and size of the mold layer on the thickness of the mold layer.
- FIG. 16 and FIG. 17 are diagrams for explaining coplanarity of a semiconductor package of the present invention.
- The degree of flexure of a semiconductor package is different each other in
zone 1,zone 2, and zone 3 (FIG. 17). The shape of cross-section of a semiconductor package is a convex above arc inzone 1, a convex below arc inzone 2, and is a straight line inzone 3. - ρi is a radius of curvature of zone i.
- Further, x axis is situated so as to go through a contact point of 2 circles, and y axis is situated so as to go through a center of a
circle 1. - Point A is one that the
circle 1 intersects with the y axis. Y coordinate of the point A corresponds to the coplanarity of thezone 1. This point corresponds to a center of the bottom surface (a surface of the side opposite to the surface where asemiconductor element 12 is mounted) of thewiring substrate 11. - Point B corresponds to a boundary of
zone 2 andzone 3, and is a point shifted by the length ofzone 2 along the circumference of thecircle 2 from the contact point of 2 circles. Further, the point B corresponds to an exterior edge of a portion where aresin layer 13 is formed on thewiring substrate 11. - The point C is the point where y coordinate of the
circle 2 shows the minimum value. - Point D is a point shifted by a length of
zone 3 along a tangent line at the point B of thecircle 2 and corresponds to an edge portion of thewiring substrate 11. - When ρ1 is radius of curvature of the
zone 1 and ρ2 is radius of curvature of thezone 2, yi can be obtained as follows. -
y 1 32 ρ1−ρ1 cos θ1 - y 2=ρ2 cos(θ2−θ1/2)−ρ2 cos θ1/2(θ2>θ1/2) or
- −ρ2 cos(−θ2+θ1/2)+ρ2 cos θ1/2(θ2≦θ1/2)
- y 3=ρ2 cos θ1/2−ρ2
- y 4 =y 3 −a×sin(θ1/2−θ2/2)
- Here,
- θ1 =L/2ρ1 and θ2 =b/2ρ2.
- Thus, y1, y2, y3, and y4 are obtained. And, by extracting arbitrary 2 points of yi, the maximum value of their difference is made the coplanarity.
- Incidentally, in this example, the point D is taken at the edge portion of the
wiring substrate 11, however, it can be taken as the lowest point of aball 18 disposed at the most exterior portion. - Here, as an insulating layer of the
wiring substrate 11, a thermosetting type epoxy resin of thermal expansion coefficient of 20 to 40 ppm/K and of elasticity modulus of 2 to 13 GPa is adopted. The thickness of thewiring substrate 11 was set 0.4 to 1.2 mm. A semiconductor package in which asemiconductor element 12 of which the thickness is 0.25 to 0.75 mm was mounted on awiring substrate 11 will be described. The length of one side (y) of thesemiconductor element 12 is 20 mm, and the length of one side (x) of thewiring substrate 11 is 40 mm. - In this case, the connecting
terminals 17 and thesolder balls 18 are arranged on the wiring substrate in a full grid of a matrix array. However, it is possible not to form the connectingterminals 17 and thesolder balls 18 at a part of the matrix array. - The vertical coordinate of FIG. 10 denotes warp of the package, that is, coplanality y (mm) of the most lowest surface of the terminals, and the horizontal coordinate denotes the size of the mold layer (z) (mm). By varying the thickness of the mold layer Hr 0.695 mm and 1 mm, relation between the size of the wiring substrate of the semiconductor package and the coplanality y (mm) of the most lowest surface of the terminals is simulated.
- As can be recognized from FIG. 10, the warp of the package decreases as the thickness of the mold layer increases, resulting in higher coplanality of the most lowest surface of the terminals. Further, with the increase of the package size (z), the warp of the package becomes small.
- Further, as materials of the resin layer, thermosetting resin such as silicone resin, vinyl polymerization resin, phenolic resin, unsaturated polyester resin, diallyl phthalate resin, cyanate ester and acrylic resin can be employed.
- Further, as materials if resin layer, and also an insulator of the wiring substrate super engineering plastic such as PPS or the like can be employed. Other than the ordinary epoxy resin, even in the case of use of above described resin, the present invention was confirmed to be effective.
Claims (16)
1. A semiconductor package, comprising:
a wiring substrate having a first face and a second face, the first face having a first area and a second area surrounds the first area, and at least a first connecting pad arranged in the first area;
a semiconductor element having a first face and a second face, the semiconductor element having at least a connecting terminal formed on the first face, and the semiconductor element being mounted on the first area of the wiring substrate in a face-down type;
at least a conductive bump connecting the first connecting pad of the wiring substrate and the connecting terminal of the semiconductor element; and
a resin layer disposed on the first face of the wiring substrate, the resin layer disposed so that the second face of the semiconductor element being exposed, side faces of the semiconductor element being sealed, and a gap between the first face of the wiring substrate and the first face of the semiconductor element being filled.
2. The semiconductor package as set forth in ,
claim 1
wherein the resin layer having a first face substantially in parallel with the first face of the wiring substrate, and the first face of the resin layer is substantially flushed with the second face of the semiconductor element.
3. The semiconductor package as set forth in ,
claim 2
wherein side faces of the resin layer for sealing is inclined, and the first face of the wiring substrate is larger than the first face of the resin layer.
4. The semiconductor package as set forth in ,
claim 1
wherein the second area of the first face of the wiring substrate is substantially covered with the resin layer.
5. The semiconductor package as set forth in , further comprising a conductive plate disposed on the second face of the semiconductor element.
claim 1
6. The semiconductor package as set forth in ,
claim 5
wherein the conductive plate and the second face of the semiconductor element are connected by a conductive resin.
7. The semiconductor package as set forth in ,
claim 5
wherein the resin layer is disposed so that at least a side surface of the conductive plate being covered.
8. A semiconductor package, comprising:
a wiring substrate having a first face and a second face, the substrate having at least a first connecting pad formed on the first face;
a semiconductor element having a first face and a second face, the semiconductor element having at least a connecting terminal formed on the first face, and the semiconductor element being mounted on the first area of the wiring substrate in a face-down type;
at least a conductive bump connecting the first connecting pad of the wiring substrate and the connecting terminal of the semiconductor element; and
a resin layer disposed on the first face of the wiring substrate and the second face of the semiconductor element so that the semiconductor element being sealed;
wherein, (αr·Er·Hr)/(αs·Es·Hs) is approximately 0.6 or more, when αr is a thermal expansion coefficient of the resin layer, Er is a Young's modulus if the resin layer, Hr is a thickness of the resin layer, αs is a thermal expansion coefficient of the wiring substrates, Es is a Young's modulus of the wiring substrate and Hs is a thickness of the wiring substrates.
9. The semiconductor package as set forth in ,
claim 8
wherein, (αc·Ec)/(αs·Es) is approximately 1.5 or more, when αc is a thermal expansion coefficient of the semiconductor element and Ec is a Young's modulus of the semiconductor element.
10. The semiconductor package as set forth in ,
claim 8
wherein the resin layer for sealing has a first portion filled in between the wiring substrate and the semiconductor element, and a second portion covering the semiconductor element from above the second face of the semiconductor element, and
wherein a Young's modulus of the first portion of the resin is smaller than a Young's Modulus of the second portion of the resin.
11. The semiconductor package as set forth in ,
claim 8
wherein the resin layer for sealing has a first portion filled in between the wiring substrate and the semiconductor element, and a second portion covering the semiconductor element from above the second face of the semiconductor element, and
wherein the first portion and the second portion are formed of an identical resin.
12. The semiconductor package as set forth in ,
claim 8
wherein the resin forming the first portion and the second portion containing a filler having a distribution of a diameter less than a gap between the wiring substrate and the semiconductor element.
13. A manufacturing method of a semiconductor package, comprising steps of:
mounting a semiconductor element on a first face of a wiring substrate, a first face of the semiconductor having at least a connecting terminal, the first face of the wiring substrate having at least a first connecting pad, the connecting terminal of the semiconductor element being connected by a conductive bump; and
forming a resin layer on the first face of the wiring substrate so that the semiconductor element is sealed;
wherein, αr, Er, Hr, αs, Es, Hs are arranged so that (αr·Er·Hr)/(αs·Es·Hs) is approximately 0.6 or more, when αr is a thermal expansion coefficient of the resin layer, Er is a Young's modulus if the resin layer, Hr is a thickness of the resin layer, αs is a thermal expansion coefficient of the wiring substrates, Es is a Young's modulus of the wiring substrate and Hs is a thickness of the wiring substrates.
14. The manufacturing method of a semiconductor package as set forth in ,
claim 13
wherein the step for forming the resin layer is carried out with transfer mold method.
15. The manufacturing method of a semiconductor package as set forth in ,
claim 14
a resin forming the resin layer containing a filler having a distribution of a diameter less than a gap between the wiring substrate and the semiconductor element.
16. The manufacturing method of a semiconductor package as set forth in ,
claim 13
wherein the a resin forming the resin layer is cured under pressure.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/850,265 US20010020736A1 (en) | 1997-10-15 | 2001-05-08 | Semiconductor package and manufacturing method thereof |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29940497 | 1997-10-15 | ||
JPP9-299404 | 1997-10-15 | ||
US09/172,038 US6448665B1 (en) | 1997-10-15 | 1998-10-14 | Semiconductor package and manufacturing method thereof |
US09/850,265 US20010020736A1 (en) | 1997-10-15 | 2001-05-08 | Semiconductor package and manufacturing method thereof |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/172,038 Continuation US6448665B1 (en) | 1997-10-15 | 1998-10-14 | Semiconductor package and manufacturing method thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
US20010020736A1 true US20010020736A1 (en) | 2001-09-13 |
Family
ID=17872129
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/172,038 Expired - Fee Related US6448665B1 (en) | 1997-10-15 | 1998-10-14 | Semiconductor package and manufacturing method thereof |
US09/850,265 Abandoned US20010020736A1 (en) | 1997-10-15 | 2001-05-08 | Semiconductor package and manufacturing method thereof |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/172,038 Expired - Fee Related US6448665B1 (en) | 1997-10-15 | 1998-10-14 | Semiconductor package and manufacturing method thereof |
Country Status (2)
Country | Link |
---|---|
US (2) | US6448665B1 (en) |
KR (1) | KR100348098B1 (en) |
Cited By (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6593169B2 (en) * | 2001-06-28 | 2003-07-15 | Sanyo Electric Co., Ltd. | Method of making hybrid integrated circuit device |
US6621152B2 (en) * | 2000-12-19 | 2003-09-16 | Fairchild Korea Semiconductor Ltd. | Thin, small-sized power semiconductor package |
US6750546B1 (en) * | 2001-11-05 | 2004-06-15 | Skyworks Solutions, Inc. | Flip-chip leadframe package |
US20050139974A1 (en) * | 2003-12-31 | 2005-06-30 | Advanced Semiconductor Engineering Inc. | Chip package structure |
US20070087479A1 (en) * | 2005-07-07 | 2007-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing low CTE substrates for use with low-k flip-chip package devices |
US20070114884A1 (en) * | 2005-11-22 | 2007-05-24 | Hidenori Harima | Method of manufacturing surface mount type crystal oscillator |
US20070138652A1 (en) * | 2005-12-19 | 2007-06-21 | Fujitsu Limited | Peel strength simulating apparatus, peel strength simulating program storage medium, and peel strength simulating method |
EP1840953A1 (en) * | 2005-03-14 | 2007-10-03 | Sumitomo Bakelite Co., Ltd. | Semiconductor device |
US20080014681A1 (en) * | 2003-12-25 | 2008-01-17 | Casio Computer Co., Ltd. | Semiconductor device including a hard sheet to reduce warping of a base plate and method of fabricating the same |
US20080116574A1 (en) * | 2006-11-17 | 2008-05-22 | Powertech Technology Inc. | BGA package with encapsulation on bottom of substrate |
US20080121845A1 (en) * | 2006-08-11 | 2008-05-29 | General Electric Company | Oxetane composition, associated method and article |
US20080128664A1 (en) * | 2004-12-17 | 2008-06-05 | Takashi Kitae | Flip-Chip Mounting Resin Composition and Bump Forming Resin Composition |
US20080128920A1 (en) * | 2006-12-05 | 2008-06-05 | Denso Corporation | Resin-sealed electronic device and method of manufacturing the same |
US20080237838A1 (en) * | 2007-03-29 | 2008-10-02 | Sharp Kabushiki Kaisha | Semiconductor device |
US20090115070A1 (en) * | 2007-09-20 | 2009-05-07 | Junji Tanaka | Semiconductor device and method for manufacturing thereof |
US20100038762A1 (en) * | 2007-02-16 | 2010-02-18 | Sumitomo Bakelite Co., Ltd. | Circuit board manufacturing method, semiconductor manufacturing apparatus, circuit board and semiconductor device |
US20110068485A1 (en) * | 2006-07-11 | 2011-03-24 | Thorsten Meyer | Component and method for producing a component |
US20110193098A1 (en) * | 2010-02-09 | 2011-08-11 | Tracy Autry | High voltage high package pressure semiconductor package |
CN102446776A (en) * | 2010-09-30 | 2012-05-09 | 富士通株式会社 | Method of manufacturing electronic device and electronic device |
US8587107B2 (en) | 2010-02-09 | 2013-11-19 | Microsemi Corporation | Silicon carbide semiconductor |
US20150069596A1 (en) * | 2013-09-12 | 2015-03-12 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US20160204081A1 (en) * | 2006-12-27 | 2016-07-14 | Cypress Semiconductor Corporation | Semiconductor device and method of manufacturing the same |
US20160330839A1 (en) * | 2014-02-21 | 2016-11-10 | Mitsui Mining & Smelting Co., Ltd. | Copper clad laminate for forming of embedded capacitor layer, multilayered printed wiring board, and manufacturing method of multilayered printed wiring board |
Families Citing this family (93)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3339838B2 (en) * | 1999-06-07 | 2002-10-28 | ローム株式会社 | Semiconductor device and method of manufacturing the same |
JP2001102486A (en) * | 1999-07-28 | 2001-04-13 | Seiko Epson Corp | Substrate for semiconductor device, semiconductor-chip mounting substrate, semiconductor device, their manufacturing method, circuit board and electronic device |
US10388626B2 (en) * | 2000-03-10 | 2019-08-20 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming flipchip interconnect structure |
WO2001068311A1 (en) | 2000-03-10 | 2001-09-20 | Chippac, Inc. | Flip chip interconnection structure |
JP2001313314A (en) * | 2000-04-28 | 2001-11-09 | Sony Corp | Semiconductor device using bump, its manufacturing method, and method for forming bump |
US6624005B1 (en) * | 2000-09-06 | 2003-09-23 | Amkor Technology, Inc. | Semiconductor memory cards and method of making same |
US6635971B2 (en) * | 2001-01-11 | 2003-10-21 | Hitachi, Ltd. | Electronic device and optical transmission module |
JP2003007962A (en) * | 2001-06-19 | 2003-01-10 | Toshiba Corp | Multilayer semiconductor module |
DE10205208A1 (en) * | 2002-02-08 | 2003-09-18 | Conti Temic Microelectronic | Circuit arrangement with a circuit board equipped with a programmable memory element |
US7138583B2 (en) * | 2002-05-08 | 2006-11-21 | Sandisk Corporation | Method and apparatus for maintaining a separation between contacts |
DE60233077D1 (en) * | 2002-08-09 | 2009-09-03 | Fujitsu Microelectronics Ltd | SEMICONDUCTOR COMPONENT AND METHOD FOR THE PRODUCTION THEREOF |
JP4390541B2 (en) * | 2003-02-03 | 2009-12-24 | Necエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
US6768209B1 (en) * | 2003-02-03 | 2004-07-27 | Micron Technology, Inc. | Underfill compounds including electrically charged filler elements, microelectronic devices having underfill compounds including electrically charged filler elements, and methods of underfilling microelectronic devices |
TW583757B (en) * | 2003-02-26 | 2004-04-11 | Advanced Semiconductor Eng | A structure of a flip-chip package and a process thereof |
US7230331B2 (en) * | 2003-04-22 | 2007-06-12 | Industrial Technology Research Institute | Chip package structure and process for fabricating the same |
JP4175197B2 (en) * | 2003-06-27 | 2008-11-05 | 株式会社デンソー | Flip chip mounting structure |
KR100886292B1 (en) | 2003-09-09 | 2009-03-04 | 산요덴키가부시키가이샤 | Semiconductor module and semiconductor device including circuit components, manufacturing method and display device thereof |
JP3977796B2 (en) * | 2003-10-29 | 2007-09-19 | 株式会社東芝 | Semiconductor device |
TWI358776B (en) * | 2003-11-08 | 2012-02-21 | Chippac Inc | Flip chip interconnection pad layout |
US8853001B2 (en) * | 2003-11-08 | 2014-10-07 | Stats Chippac, Ltd. | Semiconductor device and method of forming pad layout for flipchip semiconductor die |
US20060216860A1 (en) * | 2005-03-25 | 2006-09-28 | Stats Chippac, Ltd. | Flip chip interconnection having narrow interconnection sites on the substrate |
US7659633B2 (en) | 2004-11-10 | 2010-02-09 | Stats Chippac, Ltd. | Solder joint flip chip interconnection having relief structure |
US8350384B2 (en) * | 2009-11-24 | 2013-01-08 | Stats Chippac, Ltd. | Semiconductor device and method of forming electrical interconnect with stress relief void |
USRE44500E1 (en) | 2003-11-10 | 2013-09-17 | Stats Chippac, Ltd. | Semiconductor device and method of forming composite bump-on-lead interconnection |
US9029196B2 (en) | 2003-11-10 | 2015-05-12 | Stats Chippac, Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
US8076232B2 (en) * | 2008-04-03 | 2011-12-13 | Stats Chippac, Ltd. | Semiconductor device and method of forming composite bump-on-lead interconnection |
US20070105277A1 (en) | 2004-11-10 | 2007-05-10 | Stats Chippac Ltd. | Solder joint flip chip interconnection |
KR101249555B1 (en) | 2003-11-10 | 2013-04-01 | 스태츠 칩팩, 엘티디. | Bump-on-lead flip chip interconnection |
US8129841B2 (en) | 2006-12-14 | 2012-03-06 | Stats Chippac, Ltd. | Solder joint flip chip interconnection |
US8574959B2 (en) | 2003-11-10 | 2013-11-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming bump-on-lead interconnection |
US8026128B2 (en) | 2004-11-10 | 2011-09-27 | Stats Chippac, Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
USRE47600E1 (en) | 2003-11-10 | 2019-09-10 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming electrical interconnect with stress relief void |
US8216930B2 (en) | 2006-12-14 | 2012-07-10 | Stats Chippac, Ltd. | Solder joint flip chip interconnection having relief structure |
US7005720B2 (en) * | 2004-01-23 | 2006-02-28 | Siliconware Precision Industries Co., Ltd. | Semiconductor package with photosensitive chip and fabrication method thereof |
TWI236109B (en) * | 2004-02-26 | 2005-07-11 | Advanced Semiconductor Eng | Chip package |
JP4058642B2 (en) | 2004-08-23 | 2008-03-12 | セイコーエプソン株式会社 | Semiconductor device |
JP4880218B2 (en) * | 2004-12-22 | 2012-02-22 | 三洋電機株式会社 | Circuit equipment |
TWI251319B (en) * | 2004-12-31 | 2006-03-11 | Chipmos Technologies Inc | Chip-on-film package |
US8841779B2 (en) | 2005-03-25 | 2014-09-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate |
US20060255473A1 (en) | 2005-05-16 | 2006-11-16 | Stats Chippac Ltd. | Flip chip interconnect solder mask |
US9258904B2 (en) * | 2005-05-16 | 2016-02-09 | Stats Chippac, Ltd. | Semiconductor device and method of forming narrow interconnect sites on substrate with elongated mask openings |
WO2007001018A1 (en) * | 2005-06-29 | 2007-01-04 | Rohm Co., Ltd. | Semiconductor device and semiconductor device assembly |
JP4753642B2 (en) * | 2005-07-04 | 2011-08-24 | 株式会社リコー | Manufacturing method of electronic component mounting body |
KR100761387B1 (en) * | 2005-07-13 | 2007-09-27 | 서울반도체 주식회사 | Mold for forming a molding member and method of fabricating a molding member using the same |
CN101546735B (en) * | 2005-08-17 | 2011-08-17 | 南茂科技股份有限公司 | Packaging structure of bug-hole downwards wafer and manufacturing method thereof |
US7385299B2 (en) * | 2006-02-25 | 2008-06-10 | Stats Chippac Ltd. | Stackable integrated circuit package system with multiple interconnect interface |
CA2637812C (en) * | 2006-04-20 | 2015-02-24 | Sumitomo Bakelite Co., Ltd. | Semiconductor device |
JP2008071953A (en) * | 2006-09-14 | 2008-03-27 | Nec Electronics Corp | Semiconductor device |
US7713782B2 (en) * | 2006-09-22 | 2010-05-11 | Stats Chippac, Inc. | Fusible I/O interconnection systems and methods for flip-chip packaging involving substrate-mounted stud-bumps |
US9847309B2 (en) | 2006-09-22 | 2017-12-19 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming vertical interconnect structure between semiconductor die and substrate |
US9761435B1 (en) | 2006-12-14 | 2017-09-12 | Utac Thai Limited | Flip chip cavity package |
US9082607B1 (en) | 2006-12-14 | 2015-07-14 | Utac Thai Limited | Molded leadframe substrate semiconductor package |
US7498198B2 (en) * | 2007-04-30 | 2009-03-03 | International Business Machines Corporation | Structure and method for stress reduction in flip chip microelectronic packages using underfill materials with spatially varying properties |
JP5425404B2 (en) * | 2008-01-18 | 2014-02-26 | 東京エレクトロン株式会社 | Method for processing amorphous carbon film and method for manufacturing semiconductor device using the same |
US8349721B2 (en) | 2008-03-19 | 2013-01-08 | Stats Chippac, Ltd. | Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding |
US9345148B2 (en) | 2008-03-25 | 2016-05-17 | Stats Chippac, Ltd. | Semiconductor device and method of forming flipchip interconnection structure with bump on partial pad |
US7759137B2 (en) * | 2008-03-25 | 2010-07-20 | Stats Chippac, Ltd. | Flip chip interconnection structure with bump on partial pad and method thereof |
US20090250814A1 (en) * | 2008-04-03 | 2009-10-08 | Stats Chippac, Ltd. | Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method Thereof |
US7851928B2 (en) * | 2008-06-10 | 2010-12-14 | Texas Instruments Incorporated | Semiconductor device having substrate with differentially plated copper and selective solder |
US9947605B2 (en) * | 2008-09-04 | 2018-04-17 | UTAC Headquarters Pte. Ltd. | Flip chip cavity package |
US7897502B2 (en) * | 2008-09-10 | 2011-03-01 | Stats Chippac, Ltd. | Method of forming vertically offset bond on trace interconnects on recessed and raised bond fingers |
JPWO2010029726A1 (en) * | 2008-09-11 | 2012-02-02 | 住友ベークライト株式会社 | Semiconductor device and resin composition used for semiconductor device |
US8198186B2 (en) | 2008-12-31 | 2012-06-12 | Stats Chippac, Ltd. | Semiconductor device and method of confining conductive bump material during reflow with solder mask patch |
US8659172B2 (en) | 2008-12-31 | 2014-02-25 | Stats Chippac, Ltd. | Semiconductor device and method of confining conductive bump material with solder mask patch |
JP5213736B2 (en) * | 2009-01-29 | 2013-06-19 | パナソニック株式会社 | Semiconductor device |
US20100237500A1 (en) * | 2009-03-20 | 2010-09-23 | Stats Chippac, Ltd. | Semiconductor Substrate and Method of Forming Conformal Solder Wet-Enhancement Layer on Bump-on-Lead Site |
JP5271949B2 (en) | 2009-09-29 | 2013-08-21 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
JP5250524B2 (en) * | 2009-10-14 | 2013-07-31 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
US8198131B2 (en) * | 2009-11-18 | 2012-06-12 | Advanced Semiconductor Engineering, Inc. | Stackable semiconductor device packages |
TWI408785B (en) | 2009-12-31 | 2013-09-11 | Advanced Semiconductor Eng | Semiconductor package |
US8569894B2 (en) | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
TWI419283B (en) | 2010-02-10 | 2013-12-11 | Advanced Semiconductor Eng | Package structure |
US8039384B2 (en) | 2010-03-09 | 2011-10-18 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces |
TWI411075B (en) | 2010-03-22 | 2013-10-01 | Advanced Semiconductor Eng | Semiconductor package and manufacturing method thereof |
US8278746B2 (en) | 2010-04-02 | 2012-10-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages including connecting elements |
US8624374B2 (en) | 2010-04-02 | 2014-01-07 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof |
US8409978B2 (en) | 2010-06-24 | 2013-04-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertically offset bond on trace interconnect structure on leadframe |
JP5384443B2 (en) * | 2010-07-28 | 2014-01-08 | 日東電工株式会社 | Flip chip type semiconductor back film, dicing tape integrated semiconductor back film, semiconductor device manufacturing method, and flip chip type semiconductor device |
US8492197B2 (en) | 2010-08-17 | 2013-07-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate |
US8435834B2 (en) | 2010-09-13 | 2013-05-07 | Stats Chippac, Ltd. | Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in FO-WLCSP |
KR20120040536A (en) * | 2010-10-19 | 2012-04-27 | 삼성전자주식회사 | Semiconductor packages and methods of fabricating the same |
TWI451546B (en) | 2010-10-29 | 2014-09-01 | Advanced Semiconductor Eng | Stacked semiconductor package, semiconductor package thereof and method for making a semiconductor package |
US8698303B2 (en) | 2010-11-23 | 2014-04-15 | Ibiden Co., Ltd. | Substrate for mounting semiconductor, semiconductor device and method for manufacturing semiconductor device |
RU2449422C1 (en) * | 2010-12-28 | 2012-04-27 | Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Национальный исследовательский ядерный университет "МИФИ" (НИЯУ МИФИ) | Light diode source of radiation |
US9171792B2 (en) | 2011-02-28 | 2015-10-27 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages having a side-by-side device arrangement and stacking functionality |
KR101227735B1 (en) * | 2011-04-28 | 2013-01-29 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and fabricating method thereof |
US9437512B2 (en) * | 2011-10-07 | 2016-09-06 | Mediatek Inc. | Integrated circuit package structure |
US9349663B2 (en) * | 2012-06-29 | 2016-05-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package-on-package structure having polymer-based material for warpage control |
US8884443B2 (en) | 2012-07-05 | 2014-11-11 | Advanced Semiconductor Engineering, Inc. | Substrate for semiconductor package and process for manufacturing |
KR102164545B1 (en) | 2014-09-11 | 2020-10-12 | 삼성전자 주식회사 | Semiconductor package and package-on-package device including the same and mobile device including the same |
US10032645B1 (en) | 2015-11-10 | 2018-07-24 | UTAC Headquarters Pte. Ltd. | Semiconductor package with multiple molding routing layers and a method of manufacturing the same |
US10276477B1 (en) | 2016-05-20 | 2019-04-30 | UTAC Headquarters Pte. Ltd. | Semiconductor package with multiple stacked leadframes and a method of manufacturing the same |
CN110349945A (en) * | 2019-07-15 | 2019-10-18 | 星科金朋半导体(江阴)有限公司 | A kind of encapsulating structure and its packaging method of multi-chip |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5491612A (en) * | 1995-02-21 | 1996-02-13 | Fairchild Space And Defense Corporation | Three-dimensional modular assembly of integrated circuits |
US5726079A (en) * | 1996-06-19 | 1998-03-10 | International Business Machines Corporation | Thermally enhanced flip chip package and method of forming |
US5912316A (en) * | 1996-11-08 | 1999-06-15 | Johnson Matthey, Inc. | Flexible interpenetrating networks formed by epoxy-cyanate ester compositions via a polyamide |
US6008536A (en) * | 1997-06-23 | 1999-12-28 | Lsi Logic Corporation | Grid array device package including advanced heat transfer mechanisms |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6066843A (en) * | 1983-09-22 | 1985-04-17 | Hitachi Ltd | Integrated circuit package |
JPS63263394A (en) * | 1987-04-17 | 1988-10-31 | Ngk Insulators Ltd | Rotary regenerative type ceramic heat exchanger |
US5847467A (en) * | 1990-08-31 | 1998-12-08 | Texas Instruments Incorporated | Device packaging using heat spreaders and assisted deposition of wire bonds |
KR100280762B1 (en) * | 1992-11-03 | 2001-03-02 | 비센트 비.인그라시아 | Thermally Reinforced Semiconductor Devices Having Exposed Backsides and Methods of Manufacturing the Same |
JPH0831988A (en) * | 1994-07-20 | 1996-02-02 | Nec Corp | Sealing structure of tape carrier package |
JP3400877B2 (en) * | 1994-12-14 | 2003-04-28 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
US5864178A (en) * | 1995-01-12 | 1999-01-26 | Kabushiki Kaisha Toshiba | Semiconductor device with improved encapsulating resin |
JPH08279571A (en) | 1995-04-10 | 1996-10-22 | Shinko Electric Ind Co Ltd | Semiconductor device |
JPH08316361A (en) | 1995-05-24 | 1996-11-29 | Nec Kyushu Ltd | Semiconductor device |
JPH0964080A (en) | 1995-08-28 | 1997-03-07 | Hitachi Ltd | Semiconductor device and method of manufacturing it |
JP3366506B2 (en) | 1995-09-01 | 2003-01-14 | 新光電気工業株式会社 | Method for manufacturing semiconductor device |
JP3311215B2 (en) * | 1995-09-28 | 2002-08-05 | 株式会社東芝 | Semiconductor device |
JP3176542B2 (en) * | 1995-10-25 | 2001-06-18 | シャープ株式会社 | Semiconductor device and manufacturing method thereof |
US5723369A (en) * | 1996-03-14 | 1998-03-03 | Lsi Logic Corporation | Method of flip chip assembly |
JPH09260436A (en) | 1996-03-27 | 1997-10-03 | Mitsubishi Electric Corp | Semiconductor device |
KR0185512B1 (en) * | 1996-08-19 | 1999-03-20 | 김광호 | Column lead type package and method of making the same |
-
1998
- 1998-10-14 US US09/172,038 patent/US6448665B1/en not_active Expired - Fee Related
- 1998-10-15 KR KR1019980043181A patent/KR100348098B1/en not_active IP Right Cessation
-
2001
- 2001-05-08 US US09/850,265 patent/US20010020736A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5491612A (en) * | 1995-02-21 | 1996-02-13 | Fairchild Space And Defense Corporation | Three-dimensional modular assembly of integrated circuits |
US5726079A (en) * | 1996-06-19 | 1998-03-10 | International Business Machines Corporation | Thermally enhanced flip chip package and method of forming |
US5912316A (en) * | 1996-11-08 | 1999-06-15 | Johnson Matthey, Inc. | Flexible interpenetrating networks formed by epoxy-cyanate ester compositions via a polyamide |
US6008536A (en) * | 1997-06-23 | 1999-12-28 | Lsi Logic Corporation | Grid array device package including advanced heat transfer mechanisms |
Cited By (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6621152B2 (en) * | 2000-12-19 | 2003-09-16 | Fairchild Korea Semiconductor Ltd. | Thin, small-sized power semiconductor package |
US6593169B2 (en) * | 2001-06-28 | 2003-07-15 | Sanyo Electric Co., Ltd. | Method of making hybrid integrated circuit device |
US6750546B1 (en) * | 2001-11-05 | 2004-06-15 | Skyworks Solutions, Inc. | Flip-chip leadframe package |
US20080014681A1 (en) * | 2003-12-25 | 2008-01-17 | Casio Computer Co., Ltd. | Semiconductor device including a hard sheet to reduce warping of a base plate and method of fabricating the same |
US7867828B2 (en) * | 2003-12-25 | 2011-01-11 | Casio Computer Co., Ltd. | Method of fabricating a semiconductor device including forming an insulating layer with a hard sheet buried therein |
US20050139974A1 (en) * | 2003-12-31 | 2005-06-30 | Advanced Semiconductor Engineering Inc. | Chip package structure |
US8709293B2 (en) * | 2004-12-17 | 2014-04-29 | Panasonic Corporation | Flip-chip mounting resin composition and bump forming resin composition |
US20080128664A1 (en) * | 2004-12-17 | 2008-06-05 | Takashi Kitae | Flip-Chip Mounting Resin Composition and Bump Forming Resin Composition |
EP1840953A1 (en) * | 2005-03-14 | 2007-10-03 | Sumitomo Bakelite Co., Ltd. | Semiconductor device |
EP1840953A4 (en) * | 2005-03-14 | 2011-09-21 | Sumitomo Bakelite Co | Semiconductor device |
US20070087479A1 (en) * | 2005-07-07 | 2007-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing low CTE substrates for use with low-k flip-chip package devices |
US7491624B2 (en) * | 2005-07-07 | 2009-02-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing low CTE substrates for use with low-k flip-chip package devices |
US7486149B2 (en) * | 2005-11-22 | 2009-02-03 | Nihon Dempa Kogyo Co., Ltd. | Method of manufacturing surface mount type crystal oscillator |
US20070114884A1 (en) * | 2005-11-22 | 2007-05-24 | Hidenori Harima | Method of manufacturing surface mount type crystal oscillator |
US20070138652A1 (en) * | 2005-12-19 | 2007-06-21 | Fujitsu Limited | Peel strength simulating apparatus, peel strength simulating program storage medium, and peel strength simulating method |
US7596477B2 (en) * | 2005-12-19 | 2009-09-29 | Fujitsu Limited | Peel strength simulating apparatus, peel strength simulating program storage medium, and peel strength simulating method |
US20110068485A1 (en) * | 2006-07-11 | 2011-03-24 | Thorsten Meyer | Component and method for producing a component |
US8742563B2 (en) * | 2006-07-11 | 2014-06-03 | Intel Mobile Communications GmbH | Component and method for producing a component |
US20080121845A1 (en) * | 2006-08-11 | 2008-05-29 | General Electric Company | Oxetane composition, associated method and article |
US20080116574A1 (en) * | 2006-11-17 | 2008-05-22 | Powertech Technology Inc. | BGA package with encapsulation on bottom of substrate |
US20080128920A1 (en) * | 2006-12-05 | 2008-06-05 | Denso Corporation | Resin-sealed electronic device and method of manufacturing the same |
US7786606B2 (en) * | 2006-12-05 | 2010-08-31 | Denso Corporation | Resin-sealed electronic device and method of manufacturing the same |
US9887178B2 (en) * | 2006-12-27 | 2018-02-06 | Cypress Semiconductor Corporation | Semiconductor device and method of manufacturing the same |
US20160204081A1 (en) * | 2006-12-27 | 2016-07-14 | Cypress Semiconductor Corporation | Semiconductor device and method of manufacturing the same |
US20100038762A1 (en) * | 2007-02-16 | 2010-02-18 | Sumitomo Bakelite Co., Ltd. | Circuit board manufacturing method, semiconductor manufacturing apparatus, circuit board and semiconductor device |
US8592256B2 (en) * | 2007-02-16 | 2013-11-26 | Sumitomo Bakelite Co., Ltd. | Circuit board manufacturing method, semiconductor manufacturing apparatus, circuit board and semiconductor device |
US20080237838A1 (en) * | 2007-03-29 | 2008-10-02 | Sharp Kabushiki Kaisha | Semiconductor device |
US8018048B2 (en) * | 2007-03-29 | 2011-09-13 | Sharp Kabushiki Kaisha | Semiconductor device |
US20090115070A1 (en) * | 2007-09-20 | 2009-05-07 | Junji Tanaka | Semiconductor device and method for manufacturing thereof |
US8587107B2 (en) | 2010-02-09 | 2013-11-19 | Microsemi Corporation | Silicon carbide semiconductor |
US8237171B2 (en) * | 2010-02-09 | 2012-08-07 | Microsemi Corporation | High voltage high package pressure semiconductor package |
US20110193098A1 (en) * | 2010-02-09 | 2011-08-11 | Tracy Autry | High voltage high package pressure semiconductor package |
CN102446776A (en) * | 2010-09-30 | 2012-05-09 | 富士通株式会社 | Method of manufacturing electronic device and electronic device |
US20150069596A1 (en) * | 2013-09-12 | 2015-03-12 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US20160330839A1 (en) * | 2014-02-21 | 2016-11-10 | Mitsui Mining & Smelting Co., Ltd. | Copper clad laminate for forming of embedded capacitor layer, multilayered printed wiring board, and manufacturing method of multilayered printed wiring board |
US9924597B2 (en) * | 2014-02-21 | 2018-03-20 | Mitsui Mining & Smelting Co., Ltd. | Copper clad laminate for forming of embedded capacitor layer, multilayered printed wiring board, and manufacturing method of multilayered printed wiring board |
US20180160536A1 (en) * | 2014-02-21 | 2018-06-07 | Mitsui Mining & Smelting Co., Ltd. | Copper clad laminate for forming of embedded capacitor layer, multilayered printed wiring board, and manufacturing method of multilayered printed wiring board |
US10524360B2 (en) * | 2014-02-21 | 2019-12-31 | Mitsui Mining & Smelting Co., Ltd. | Copper clad laminate for forming of embedded capacitor layer, multilayered printed wiring board, and manufacturing method of multilayered printed wiring board |
Also Published As
Publication number | Publication date |
---|---|
KR19990037125A (en) | 1999-05-25 |
KR100348098B1 (en) | 2002-12-26 |
US6448665B1 (en) | 2002-09-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6448665B1 (en) | Semiconductor package and manufacturing method thereof | |
JPH11220077A (en) | Semiconductor device and manufacture of the semiconductor device | |
KR101387706B1 (en) | Semiconductor Package, Method of Fabricating the Same and Electronic Device Including the Same | |
US6621172B2 (en) | Semiconductor device and method of fabricating the same, circuit board, and electronic equipment | |
US7170158B2 (en) | Double-sided circuit board and multi-chip package including such a circuit board and method for manufacture | |
US8035127B2 (en) | Packaging substrate structure with a semiconductor chip embedded therein | |
US5467253A (en) | Semiconductor chip package and method of forming | |
US7911047B2 (en) | Semiconductor device and method of fabricating the semiconductor device | |
US6326700B1 (en) | Low profile semiconductor package and process for making the same | |
US8304917B2 (en) | Multi-chip stacked package and its mother chip to save interposer | |
US20030218245A1 (en) | Semiconductor device and a method of manufacturing the same | |
KR100669830B1 (en) | Stack package using acf | |
KR101837511B1 (en) | Semiconductor package and method of manufacturing the same | |
JPH1117048A (en) | Semiconductor chip package | |
KR20050063700A (en) | A manufacturing method of a semiconductor device | |
US20070020812A1 (en) | Circuit board structure integrated with semiconductor chip and method of fabricating the same | |
CN110459521B (en) | Flip chip package substrate and electronic package | |
JP2010263199A (en) | Manufacturing method of semiconductor device, and semiconductor device | |
JP4836847B2 (en) | Semiconductor device and manufacturing method of semiconductor device | |
US7276800B2 (en) | Carrying structure of electronic components | |
US8063313B2 (en) | Printed circuit board and semiconductor package including the same | |
JP2002270717A (en) | Semiconductor device | |
JPWO2003012863A1 (en) | Semiconductor device and manufacturing method thereof | |
US11462461B2 (en) | System in package for lower z height and reworkable component assembly | |
US20020124955A1 (en) | Attachment of a heat spreader for fabricating a cavity down plastic chip carrier |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |