US20010003207A1 - Method and apparatus of measuring power consumption in a computer system to meet the power delivery specifications of a power outlet - Google Patents

Method and apparatus of measuring power consumption in a computer system to meet the power delivery specifications of a power outlet Download PDF

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US20010003207A1
US20010003207A1 US09/219,578 US21957898A US2001003207A1 US 20010003207 A1 US20010003207 A1 US 20010003207A1 US 21957898 A US21957898 A US 21957898A US 2001003207 A1 US2001003207 A1 US 2001003207A1
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Prior art keywords
computer system
power
processor
threshold
power consumed
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US09/219,578
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US6367023B2 (en
Inventor
Ralph M. Kling
Edward T. Grochowski
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Intel Corp
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Intel Corp
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Priority to US09/219,578 priority Critical patent/US6367023B2/en
Assigned to INTEL CORPORATION, INC. reassignment INTEL CORPORATION, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GROCHOWSKI, EDWARD T., KLING, RALPH M.
Priority to GB0114526A priority patent/GB2361326B/en
Priority to DE19983848A priority patent/DE19983848B3/en
Priority to PCT/US1999/028047 priority patent/WO2000039661A1/en
Priority to CN998163449A priority patent/CN1344389B/en
Priority to KR1020017007988A priority patent/KR20020008110A/en
Priority to AU19227/00A priority patent/AU1922700A/en
Publication of US20010003207A1 publication Critical patent/US20010003207A1/en
Publication of US6367023B2 publication Critical patent/US6367023B2/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/20—Cooling means
    • G06F1/206—Cooling means comprising thermal management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to computer systems and more particularly to limiting the power consumed in a computer system by throttling the power consumed by an integrated circuit in response to a high power condition.
  • Computer systems from small handheld electronic devices to medium-sized mobile and desktop systems to large servers and workstations, are becoming increasingly pervasive in our society.
  • Computer systems typically include one or more processors.
  • a processor manipulates and controls the flow of data in a computer by executing instructions.
  • processor designers strive to continually increase the operating speed of the processor.
  • the power consumed by the processor tends to increase as well.
  • the power consumed by the processor has been limited by two factors. First, as power consumption increases, the processor tends to run hotter, leading to thermal dissipation problems. Second, as power consumption increases, the battery life of mobile computer systems decreases, leading to less attractive systems for consumers.
  • processor designers have developed numerous methods to deal with these issues. For example, processor designers implement specialized circuit design techniques that reduce power consumption. In addition, modern computer systems are designed to shut down portions of the system that are not needed during a particular period of time. Both of these techniques conserve power and help extend battery life.
  • Some processor packages include a thermal sensor to monitor the temperature of the processor. If the processor temperature exceeds a particular threshold, the processor is placed into low power mode until it cools off. If these precautions are not taken, the processor may destroy itself by its own heat.
  • a method and apparatus are described for managing the power consumed in a computer system.
  • a measurement is taken of an electrical parameter that is approximately proportional to the power consumed by at least a portion of a computer system. This measurement is then used to determine if the power consumed by the portion of the computer system has reached a threshold.
  • FIG. 1 is a computer system formed in accordance with an embodiment of the present invention
  • FIG. 1A is a switching regulator in a power supply of FIG. 1;
  • FIG. 2A is a graph showing total power consumption versus time for an embodiment of the present invention.
  • FIG. 2B is a graph showing total power consumption versus time for an alternate embodiment of the present invention.
  • FIG. 3 is a computer system including a processor formed in accordance with an embodiment of the present invention.
  • FIG. 4 is a flow chart showing a method of reducing power consumption of a processor in accordance with an embodiment of the present invention
  • FIG. 5 is a flow chart showing the method of FIG. 4 in a first embodiment of the present invention.
  • FIG. 6 is a flow chart showing the method of FIG. 4 in a second embodiment of the present invention.
  • FIG. 7 is a flow chart showing the method of FIG. 4 in a third embodiment of the present invention.
  • the power consumed by at least a portion of a computer system is monitored by measuring a parameter that is approximately proportional to the consumed power, such as voltage, current, or the duty cycle of a switching signal in a power supply. These measurements are provided to a power controller.
  • the portion of the computer system that is monitored may include one or more processors of the computer system in addition to other integrated circuits (ICs) that consume a significant amount of power such as, for example, the bridge (or “chipset”) or the video terminal.
  • ICs integrated circuits
  • a throttle signal is sent to one or more ICs of the computer system by the controller.
  • one or more of the ICs reduces its power consumption.
  • a processor of the computer system reduces its core frequency while maintaining a consistent bus frequency in response to receiving the throttle signal.
  • the processor stalls all or a portion of one or more pipelines, or issues no-ops to one or more pipelines, in response to receiving the throttle signal.
  • FIG. 1 is a multiprocessor computer system formed in accordance with an embodiment of the present invention.
  • Primary bridge 110 is coupled to processors 100 and 101 via a system bus.
  • Bridge 110 is used to couple the processors to main memory 115 and to couple the processors to peripheral components 120 and 130 via a peripheral bus.
  • Secondary bridge 125 couples external memory 140 and video terminal 145 to the peripheral bus.
  • Peripheral components 120 and 130 of FIG. 1 may include audio and video input/output devices such as audio/video generators, accelerators, or analyzers.
  • External memory 140 may include a hard drive, floppy disk, tape drive, or other non-volatile, machine-readable, storage medium.
  • Video terminal 145 may include any video display device such as a cathode ray tube (CRT) terminal or a flat panel display such as a liquid crystal display (LCD).
  • Main memory 115 may include dynamic RAM (DRAM), static RAM (SRAM), flash EPROM, or other high speed, high capacity storage medium.
  • the computer system of FIG. 1 may be modified to be a uniprocessor system, or it may include more than two processors.
  • Each device of the computer system of FIG. 1 is supplied power by a power supply, V cc , and this power is monitored by a meter.
  • Power controller 150 is coupled to each device and to each meter.
  • each device may include one or more ICs that consume power.
  • the computer system includes one or more independent power supplies, each of which provides power to one or more ICs.
  • a meter may monitor the power consumed by a single IC or any number of ICs.
  • one or more meters may be coupled to only a selected number of ICs, monitoring the power consumption of those selected ICs.
  • the monitored ICs may be those ICs that consume the majority of power in the computer system. For example, only the power consumed by processor A 100 and processor B 101 , alone, or in addition to bridge 110 , video terminal 145 , and external memory 140 may be monitored.
  • power controller 150 may be coupled to all or only a selected number of ICs or meters.
  • power controller 150 of FIG. 1 is a stand-alone IC or is a unit included within another IC.
  • power controller 150 may be included in a bridge or a processor of the computer system.
  • the power controller is software code executed by a processor of the computer system to implement the functionality described below.
  • One or more of the meters of the computer system of FIG. 1 monitor power consumption by measuring a parameter that is approximately proportional to the power consumed by one or more ICs. These measurements are then provided to power controller 150 .
  • a meter may measure power, current, or voltage. Current consumption may be measured magnetically by, for example, hall-effect sensors that measure induction. Alternatively, the voltage drop across a resistor having a known resistance may be measured.
  • FIG. 1A is a switching regulator in a power supply of FIG. 1.
  • the AC power signal from the power outlet is rectified, filtered, and conditioned by input circuit 160 .
  • the input to circuit 160 may be the DC power signal from another power supply.
  • the power signal need not be rectified by input circuit 160 .
  • the resulting high voltage DC power signal from input circuit 160 is pulse modulated by switching transistors 161 and 162 under control of pulse width modulator 163 .
  • Modulator 163 controls the power signal modulation by providing a switching signal to the bases of the transistors.
  • the resulting, pulsed power signal is provided to transformer 164 , the output of which is rectified, filtered, and conditioned by output circuit 165 .
  • the resulting DC power signal, V cc is provided to one or more ICs of the computer system, and is fed back to pulse width modulator 163 . This feedback signal is monitored by modulator 163 to regulate the pulse width of the switching signal. If V cc falls below the desired output voltage, modulator 163 increases the pulse width. If V cc rises above the desired output voltage, the modulator decreases the pulse width.
  • One or more parameters of the switching signal provided from modulator 163 to the bases of switching transistors 161 or 162 may be proportional to the power or current consumed by the ICs coupled to the V cc output.
  • the pulse width or duty cycle (both of which are referred to herein as the duty cycle) may be proportional to the power consumption. Therefore, in accordance with one embodiment of the present invention, the duty cycle of the switching signal is measured by the associated meter of FIG. 1, and these measurements are provided to power controller 150 . The duty cycle may be measured from the switching signal provided to one or both bases of the switching transistors.
  • pulse width modulator 163 may provide a separate signal that indicates the duty cycle of the switching signal.
  • the duty cycle of the switching signal is indirectly measured by measuring the duty cycle of the pulsed power signal provided from the switching transistors to transformer 164 .
  • the measurements from the meters may be converted into digital format for processing by power controller 150 .
  • the measurements may remain as analog current or voltage levels.
  • Power controller 150 gathers the measurements from one or more of the meters of the computer system of FIG. 1 and calculates the total power consumed by the portion of the computer system comprising the associated ICs. Alternatively, power controller 150 may calculate a total of any value, such as current, voltage, or duty cycle, that is proportional to the total power consumed by the portion of the computer system. If the total power consumed reaches a threshold, or if the total of a value that is proportional to the total power consumed reaches a threshold, controller 150 sends a throttle signal to one or more ICs of the computer system. In response to receiving a throttle signal, an IC reduces its power consumption. Note that for simplicity, as used henceforth, the term “power” includes either actual power or a value, such as current, voltage, duty cycle, or other measurement, that is proportional to power.
  • the ICs that receive the throttle signal and, in turn, reduce their power consumption may be selected by power controller 150 of FIG. 1 in any of a number of different ways.
  • power controller 150 sends a throttle signal to the one or more ICs that consume the majority of power in the computer system.
  • the throttle signal may be sent to one or both of processors 100 or 101 .
  • power controller 150 sends a throttle signal to the one or more ICs having a low impact on the operation of the computer system.
  • the throttle signal may be sent to video terminal 145 or external memory 140 .
  • the throttle signal may be sent to one or both of peripheral components 120 or 130 if these devices are either inactive or not necessary to the near term execution of instructions in processors 100 or 101 .
  • FIG. 2A is a graph showing the total power consumption versus time for all or a portion of the computer system of FIG. 1 in accordance with one embodiment of the present invention.
  • the upward spikes in the graph are indicative of periods of overactivity by one or more ICs of the computer system, typically the processors.
  • the upper threshold set in the power controller is shown as the upper limit line in the graph of FIG. 2A. This threshold may be permanently set within the power controller or may be modifiable by the system designer or system user via software or hardware control.
  • the upper limit is a constant value as shown in FIG. 2A.
  • This constant value may be associated with an approximately maximum power that can be reliably consumed by the computer system from a power outlet into which the system is plugged before the outlet's fuse or circuit breaker trips. This value may be changed by, for example, modifying the settings stored in the basic input/output system (BIOS) of the computer.
  • the threshold is not strictly a function of total power consumed but rather a function of both total power consumed and time. For example, some power outlets are able to sustain high power conditions for limited periods of time before their circuit breaker trips. In these cases, the total power value may be integrated over a period of time and compared to a threshold value associated with the total power delivery specifications of the outlet. For this example, power spikes may be tolerated for limited periods of time.
  • the power controller sends a throttle signal to one or more ICs of the computer system.
  • the throttle signal When an IC reduces its power consumption in response to the throttle signal, the total power consumption, as calculated by the power controller, is reduced as shown in FIG. 2A.
  • the throttle signal is continually asserted until the total power consumption, as calculated by the power controller, reaches the lower threshold indicated by the lower limit line. Once this lower threshold is reached, the throttle signal may be deasserted, and, in response, the IC resumes normal operation.
  • the lower threshold may be set to a predetermined value selected to provide hysteresis to reduce the occurrence of power oscillation between the upper and lower thresholds. This lower threshold may be hard wired into the power controller or hard wired into the IC that receives the throttle signal. Alternatively, the lower threshold may be modifiable by a user or automatically adjusted within the computer system to, for example, reduce power oscillation.
  • FIG. 2B is a graph showing the total power consumption versus time for all or a portion of the computer system of FIG. 1 in accordance with an alternate embodiment of the present invention.
  • the graph of FIG. 2B is similar to the graph of FIG. 2A except that for the embodiment of FIG. 2B, once the throttle signal is triggered, the signal is continually asserted for a predetermined period of time, 200 . Once this predetermined period of time, 200 , has passed, the throttle signal may be deasserted, and, in response, the IC resumes normal operation.
  • the predetermined period of time may be selected to reduce the occurrence of total power consumption oscillation.
  • This predetermined period of time, 200 may be hard wired into the power controller or hard wired into the IC that receives the throttle signal.
  • predetermined period of time, 200 may be modifiable by a user or automatically adjusted within the computer system to, for example, reduce power oscillation.
  • FIG. 3 is a computer system including processor 310 formed in accordance with an embodiment of the present invention.
  • System clock 301 and a throttle signal line are coupled to clock synchronizer 311 of processor 310 .
  • Processor 310 includes bus interface 312 and a core having pipeline 313 .
  • Bus interface 312 and pipeline 313 receive separate clock signals from clock synchronizer 311 .
  • Synchronization unit 314 of bus interface 312 is coupled to the input and output of pipeline 313 and communicates data with other ICs via system bus 320 .
  • clock synchronizer 311 of FIG. 3 receives system clock 301 and multiplies the system clock frequency by a first ratio to generate a bus frequency provided to bus interface 312 .
  • Other ICs (not shown) coupled to bus 320 communicate with processor 310 at this bus frequency.
  • Clock synchronizer 311 also multiplies the system clock frequency by a second ratio to generate a much higher frequency called a core frequency.
  • the core frequency is provided to pipeline 313 .
  • Pipeline 313 operates at this core frequency.
  • Synchronization unit 314 includes synchronization logic to communicate data with pipeline 313 at the core frequency and with bus interface 312 at the bus frequency.
  • the core frequency is reduced by multiplying the system clock frequency by a third ratio to generate a reduced core frequency that is slower than the original core frequency. This reduced core frequency is provided to pipeline 313 which then operates at this reduced core frequency.
  • the core frequency is increased to its original value by multiplying the system clock frequency by the second ratio and applying the resulting high core frequency to pipeline 313 .
  • the bus frequency provided to bus interface 312 remains consistent.
  • the operating frequency (core frequency) of processor 310 is adjusted in response to the throttle signal, the computer system continues to operate undisturbed because processor 310 communicates with the other ICs coupled to bus 320 at a consistent bus frequency.
  • an abrupt transition between core frequencies of processor 310 may be achieved by rapidly switching between two multiplication ratios within clock synchronizer 311 in response to the throttle signal.
  • a slower, smoother transition between core frequencies may be achieved by stepping through various multiplication ratios between the high and low core frequencies.
  • a rapid frequency transition may be desirable to provide good reaction time to the detection of a high power state by the power controller.
  • a slower frequency transition may be desirable to help reduce power supply transients.
  • the speed of the frequency transition may be selected to reduce the occurrence of total power consumption oscillation. The frequency transition speed may be hard wired into the processor, modifiable by a user, or automatically adjusted within the computer system to, for example, reduce power oscillation.
  • processor 310 of FIG. 3 in response to the assertion of a throttle signal, stalls all or a portion of pipeline 313 .
  • Stalling also called freezing or halting
  • a pipeline significantly reduces the power consumption of the processor because no or few instructions are executed while the processor is stalled.
  • the clock supplied to the stalled pipeline, or pipeline portion is turned off.
  • the pipeline stall is released upon deassertion of the throttle signal.
  • the stall may be global, in which all pipelines within processor 310 are stalled, or local, in which only select pipelines are stalled.
  • which pipeline, or which portion of the pipeline, is stalled may be predetermined by the processor designer and hard wired into the processor. Alternatively, this determination may be modifiable by a user or automatically selected by the processor.
  • processor 310 of FIG. 3 in response to the assertion of a throttle signal, processor 310 of FIG. 3 issues no-ops to pipeline 313 .
  • a no-op requires little or no servicing or activity by the processor upon execution, so the processor requires only a fraction of the power (e.g. less than half) to execute the no-op than it requires to execute most other instructions.
  • the clock supplied to the pipeline, or pipeline portion, that is executing the no-op is turned off.
  • the normal instructions of the program code are again issued to the pipeline upon deassertion of the throttle signal.
  • a mix of both no-ops and normal instructions are issued to the pipeline during assertion of the throttle signal.
  • the relative mix between no-ops and instructions may be predetermined by the processor designer and hard wired into the processor. Alternatively, this determination may be modifiable by a user or automatically selected by the processor.
  • FIG. 4 is a flow chart showing a method of reducing power consumption of a processor in accordance with an embodiment of the present invention.
  • the power, or a parameter that is proportional to power, consumed by the processor is measured. This power may be measured by a meter and the value provided in either digital or analog form to a power controller. For example, an ammeter may provide a measurement of the current consumed by the processor to the power controller.
  • the power controller determines if the power has reached an upper threshold. If the power has not reached the threshold, normal operation continues at step 400 . If, however, the power has reached the threshold, then, at step 410 , the amount of power being consumed by the processor is reduced. This reduction may be in response to a throttle signal sent from the power controller to the processor.
  • the power controller determines if the power has reached a lower threshold.
  • the power controller alternatively or additionally determines if a predetermined period of time has elapsed since reducing the power consumption at step 410 . If the determination proves to be false, then the power consumption continues to be reduced (or continues in a reduced state, for an alternate embodiment), at step 410 until the determination at step 415 holds true. Once the power has reached a lower threshold or the predetermined period of time has elapsed, normal operation is resumed at step 420 and the method proceeds back to step 400 .
  • FIG. 5 is a flow chart showing the method of FIG. 4 in a first embodiment of the present invention.
  • a processor core is operated at a high core frequency while the processor communicates with other ICs of the computer system via a bus operating at a bus frequency.
  • step 515 of FIG. 5 it is determined if the throttle signal to the processor has been deasserted. The frequency is maintained at the reduced state at step 510 until the throttle signal is deasserted. Once the throttle signal is deasserted at step 515 , the processor resumes normal operation at the high core frequency at step 520 , and the method proceeds back to step 500 .
  • FIG. 6 is a flow chart showing the method of FIG. 4 in a second embodiment of the present invention.
  • a processor is operated by continually issuing instructions and executing those instructions via the processor pipeline.
  • the power consumed by the processor is continually measured during this operation and monitored by a power controller.
  • the power controller determines if the power has reached an upper threshold. If the power has not reached the upper threshold, normal operation of the processor continues. If, however, the power has reached the upper threshold, then, at step 610 , all or a portion of the processor pipeline is stalled to reduce the power consumption of the processor.
  • the power controller determines if the power has reached a lower threshold, or, alternatively, the power controller may determine if a predetermined period of time has elapsed since stalling the pipeline at step 610 .
  • the pipeline continues to be stalled at step 610 until the power has reached a lower threshold or the predetermined period of time has elapsed.
  • normal operation is resumed at step 620 (e.g., the stall of the pipeline is released) and the method proceeds back to step 600 .
  • FIG. 7 is a flow chart showing the method of FIG. 4 in a third embodiment of the present invention.
  • a processor is operated by continually issuing instructions and executing those instructions via the processor pipeline.
  • the power consumed by the processor is continually measured during this operation and monitored by a power controller.
  • the power controller determines if the power has reached an upper threshold. If the power has not reached the upper threshold, normal operation of the processor continues. If, however, the power has reached the threshold, then, at step 710 , no-ops are inserted into the processor pipeline to reduce the power consumption of the processor.
  • the power controller determines if the power has reached a lower threshold, or, alternatively, the power controller may determine if a predetermined period of time has elapsed since inserting no-ops into the pipeline at step 710 . No-ops continue to be inserted into the pipeline at step 710 until the power has reached a lower threshold or the predetermined period of time has elapsed. Once the lower threshold is reached or the predetermined period of time has elapsed, normal operation is resumed at step 720 (e.g., the normal instruction flow is again issued into the pipeline) and the method proceeds back to step 700 .
  • step 720 e.g., the normal instruction flow is again issued into the pipeline

Abstract

A measurement is taken of an electrical parameter that is approximately proportional to the power consumed by at least a portion of a computer system. This measurement is then used to determine if the power consumed by the portion of the computer system reaches a threshold.

Description

  • The present invention relates to computer systems and more particularly to limiting the power consumed in a computer system by throttling the power consumed by an integrated circuit in response to a high power condition. [0001]
    • BACKGROUND
  • Computer systems, from small handheld electronic devices to medium-sized mobile and desktop systems to large servers and workstations, are becoming increasingly pervasive in our society. Computer systems typically include one or more processors. A processor manipulates and controls the flow of data in a computer by executing instructions. To provide more powerful computer systems for consumers, processor designers strive to continually increase the operating speed of the processor. Unfortunately, as processor speed increases, the power consumed by the processor tends to increase as well. Historically, the power consumed by the processor has been limited by two factors. First, as power consumption increases, the processor tends to run hotter, leading to thermal dissipation problems. Second, as power consumption increases, the battery life of mobile computer systems decreases, leading to less attractive systems for consumers. [0002]
  • Processor and computer system designers have developed numerous methods to deal with these issues. For example, processor designers implement specialized circuit design techniques that reduce power consumption. In addition, modern computer systems are designed to shut down portions of the system that are not needed during a particular period of time. Both of these techniques conserve power and help extend battery life. [0003]
  • To address the thermal issue, elaborate thermal dissipation systems are often affixed to the processor to help dissipate the heat from the processor to the ambient environment. Some processor packages include a thermal sensor to monitor the temperature of the processor. If the processor temperature exceeds a particular threshold, the processor is placed into low power mode until it cools off. If these precautions are not taken, the processor may destroy itself by its own heat. [0004]
    • SUMMARY OF THE INVENTION
  • A method and apparatus are described for managing the power consumed in a computer system. In accordance with one embodiment of the present invention, a measurement is taken of an electrical parameter that is approximately proportional to the power consumed by at least a portion of a computer system. This measurement is then used to determine if the power consumed by the portion of the computer system has reached a threshold. [0005]
  • Other features and advantages of the present invention will be apparent from the accompanying drawings and the detailed description that follows. [0006]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention is illustrated by way of example and not limitation in the accompanying figures in which like references indicate similar elements and in which: [0007]
  • FIG. 1 is a computer system formed in accordance with an embodiment of the present invention; [0008]
  • FIG. 1A is a switching regulator in a power supply of FIG. 1; [0009]
  • FIG. 2A is a graph showing total power consumption versus time for an embodiment of the present invention; [0010]
  • FIG. 2B is a graph showing total power consumption versus time for an alternate embodiment of the present invention; [0011]
  • FIG. 3 is a computer system including a processor formed in accordance with an embodiment of the present invention; [0012]
  • FIG. 4 is a flow chart showing a method of reducing power consumption of a processor in accordance with an embodiment of the present invention; [0013]
  • FIG. 5 is a flow chart showing the method of FIG. 4 in a first embodiment of the present invention; [0014]
  • FIG. 6 is a flow chart showing the method of FIG. 4 in a second embodiment of the present invention; and [0015]
  • FIG. 7 is a flow chart showing the method of FIG. 4 in a third embodiment of the present invention. [0016]
    • DETAILED DESCRIPTION
  • Computer system power consumption is now rapidly approaching the point at which the power required to operate the system can no longer be reliably supplied to the system. This is primarily due to the fact that one or more processors contained in a system plugged into a power outlet may consume more power during an overactive period than the power outlet can deliver. Under this situation, the fuse or circuit breaker that protects the power outlet can be tripped (or blown) during normal operation of the system. [0017]
  • In accordance with an embodiment of the present invention, the power consumed by at least a portion of a computer system is monitored by measuring a parameter that is approximately proportional to the consumed power, such as voltage, current, or the duty cycle of a switching signal in a power supply. These measurements are provided to a power controller. The portion of the computer system that is monitored may include one or more processors of the computer system in addition to other integrated circuits (ICs) that consume a significant amount of power such as, for example, the bridge (or “chipset”) or the video terminal. [0018]
  • Once the consumed power, as determined by the power controller, reaches a threshold, a throttle signal is sent to one or more ICs of the computer system by the controller. In response to receiving this throttle signal, one or more of the ICs reduces its power consumption. For example, for one embodiment of the present invention, a processor of the computer system reduces its core frequency while maintaining a consistent bus frequency in response to receiving the throttle signal. For another embodiment, the processor stalls all or a portion of one or more pipelines, or issues no-ops to one or more pipelines, in response to receiving the throttle signal. [0019]
  • By directly monitoring power consumption, or a value proportional thereto, temperature measurement inaccuracies related to poor positioning of thermal sensors in proximity to the processor are avoided. In addition, the response time between detecting a high power condition and reducing the power consumption of the computer system is greatly improved over the use of thermal sensors to detect the high power condition. A more detailed description of embodiments of the present invention, including various configurations and implementations, is provided below. [0020]
  • FIG. 1 is a multiprocessor computer system formed in accordance with an embodiment of the present invention. [0021] Primary bridge 110 is coupled to processors 100 and 101 via a system bus. Bridge 110 is used to couple the processors to main memory 115 and to couple the processors to peripheral components 120 and 130 via a peripheral bus. Secondary bridge 125 couples external memory 140 and video terminal 145 to the peripheral bus.
  • [0022] Peripheral components 120 and 130 of FIG. 1 may include audio and video input/output devices such as audio/video generators, accelerators, or analyzers. External memory 140 may include a hard drive, floppy disk, tape drive, or other non-volatile, machine-readable, storage medium. Video terminal 145 may include any video display device such as a cathode ray tube (CRT) terminal or a flat panel display such as a liquid crystal display (LCD). Main memory 115 may include dynamic RAM (DRAM), static RAM (SRAM), flash EPROM, or other high speed, high capacity storage medium. For an alternate embodiment of the present invention, the computer system of FIG. 1 may be modified to be a uniprocessor system, or it may include more than two processors.
  • Each device of the computer system of FIG. 1 is supplied power by a power supply, V[0023] cc, and this power is monitored by a meter. Power controller 150 is coupled to each device and to each meter. Note that each device may include one or more ICs that consume power. For one embodiment of the present invention, the computer system includes one or more independent power supplies, each of which provides power to one or more ICs. A meter may monitor the power consumed by a single IC or any number of ICs. For a simpler embodiment of the present invention, one or more meters may be coupled to only a selected number of ICs, monitoring the power consumption of those selected ICs. For this embodiment, it may be found advantageous for the monitored ICs to be those ICs that consume the majority of power in the computer system. For example, only the power consumed by processor A 100 and processor B 101, alone, or in addition to bridge 110, video terminal 145, and external memory 140 may be monitored. In addition, power controller 150 may be coupled to all or only a selected number of ICs or meters.
  • In accordance with one embodiment of the present invention, [0024] power controller 150 of FIG. 1 is a stand-alone IC or is a unit included within another IC. For example, for one embodiment of the present invention, power controller 150 may be included in a bridge or a processor of the computer system. For an alternate embodiment of the present invention, the power controller is software code executed by a processor of the computer system to implement the functionality described below.
  • One or more of the meters of the computer system of FIG. 1 monitor power consumption by measuring a parameter that is approximately proportional to the power consumed by one or more ICs. These measurements are then provided to [0025] power controller 150. For example, a meter may measure power, current, or voltage. Current consumption may be measured magnetically by, for example, hall-effect sensors that measure induction. Alternatively, the voltage drop across a resistor having a known resistance may be measured.
  • For an embodiment in which a power supply includes a switching regulator, one or more parameters of the switching signal may be measured by the associated meter of FIG. 1. FIG. 1A is a switching regulator in a power supply of FIG. 1. As shown in FIG. 1A, the AC power signal from the power outlet is rectified, filtered, and conditioned by [0026] input circuit 160. Alternatively, for an embodiment in which two or more power supplies are cascaded, the input to circuit 160 may be the DC power signal from another power supply. For this alternate embodiment, the power signal need not be rectified by input circuit 160.
  • The resulting high voltage DC power signal from [0027] input circuit 160 is pulse modulated by switching transistors 161 and 162 under control of pulse width modulator 163. Modulator 163 controls the power signal modulation by providing a switching signal to the bases of the transistors. The resulting, pulsed power signal is provided to transformer 164, the output of which is rectified, filtered, and conditioned by output circuit 165. The resulting DC power signal, Vcc, is provided to one or more ICs of the computer system, and is fed back to pulse width modulator 163. This feedback signal is monitored by modulator 163 to regulate the pulse width of the switching signal. If Vcc falls below the desired output voltage, modulator 163 increases the pulse width. If Vcc rises above the desired output voltage, the modulator decreases the pulse width.
  • One or more parameters of the switching signal provided from [0028] modulator 163 to the bases of switching transistors 161 or 162 may be proportional to the power or current consumed by the ICs coupled to the Vcc output. For example, the pulse width or duty cycle (both of which are referred to herein as the duty cycle) may be proportional to the power consumption. Therefore, in accordance with one embodiment of the present invention, the duty cycle of the switching signal is measured by the associated meter of FIG. 1, and these measurements are provided to power controller 150. The duty cycle may be measured from the switching signal provided to one or both bases of the switching transistors. Alternatively, pulse width modulator 163 may provide a separate signal that indicates the duty cycle of the switching signal. For another embodiment, the duty cycle of the switching signal is indirectly measured by measuring the duty cycle of the pulsed power signal provided from the switching transistors to transformer 164.
  • Referring again to FIG. 1, the measurements from the meters may be converted into digital format for processing by [0029] power controller 150. Alternatively, if power controller 150 includes analog circuitry, the measurements may remain as analog current or voltage levels.
  • [0030] Power controller 150 gathers the measurements from one or more of the meters of the computer system of FIG. 1 and calculates the total power consumed by the portion of the computer system comprising the associated ICs. Alternatively, power controller 150 may calculate a total of any value, such as current, voltage, or duty cycle, that is proportional to the total power consumed by the portion of the computer system. If the total power consumed reaches a threshold, or if the total of a value that is proportional to the total power consumed reaches a threshold, controller 150 sends a throttle signal to one or more ICs of the computer system. In response to receiving a throttle signal, an IC reduces its power consumption. Note that for simplicity, as used henceforth, the term “power” includes either actual power or a value, such as current, voltage, duty cycle, or other measurement, that is proportional to power.
  • The ICs that receive the throttle signal and, in turn, reduce their power consumption, may be selected by [0031] power controller 150 of FIG. 1 in any of a number of different ways. For one embodiment of the present invention, power controller 150 sends a throttle signal to the one or more ICs that consume the majority of power in the computer system. For example, for this embodiment the throttle signal may be sent to one or both of processors 100 or 101. For another embodiment, power controller 150 sends a throttle signal to the one or more ICs having a low impact on the operation of the computer system. For example, for this embodiment the throttle signal may be sent to video terminal 145 or external memory 140. As another example of this embodiment, the throttle signal may be sent to one or both of peripheral components 120 or 130 if these devices are either inactive or not necessary to the near term execution of instructions in processors 100 or 101.
  • FIG. 2A is a graph showing the total power consumption versus time for all or a portion of the computer system of FIG. 1 in accordance with one embodiment of the present invention. The upward spikes in the graph are indicative of periods of overactivity by one or more ICs of the computer system, typically the processors. The upper threshold set in the power controller is shown as the upper limit line in the graph of FIG. 2A. This threshold may be permanently set within the power controller or may be modifiable by the system designer or system user via software or hardware control. [0032]
  • For one embodiment of the present invention, the upper limit is a constant value as shown in FIG. 2A. This constant value may be associated with an approximately maximum power that can be reliably consumed by the computer system from a power outlet into which the system is plugged before the outlet's fuse or circuit breaker trips. This value may be changed by, for example, modifying the settings stored in the basic input/output system (BIOS) of the computer. For another embodiment of the present invention, the threshold is not strictly a function of total power consumed but rather a function of both total power consumed and time. For example, some power outlets are able to sustain high power conditions for limited periods of time before their circuit breaker trips. In these cases, the total power value may be integrated over a period of time and compared to a threshold value associated with the total power delivery specifications of the outlet. For this example, power spikes may be tolerated for limited periods of time. [0033]
  • Once the threshold is reached, the power controller sends a throttle signal to one or more ICs of the computer system. When an IC reduces its power consumption in response to the throttle signal, the total power consumption, as calculated by the power controller, is reduced as shown in FIG. 2A. [0034]
  • For the embodiment of FIG. 2A, once triggered, the throttle signal is continually asserted until the total power consumption, as calculated by the power controller, reaches the lower threshold indicated by the lower limit line. Once this lower threshold is reached, the throttle signal may be deasserted, and, in response, the IC resumes normal operation. In accordance with this embodiment, the lower threshold may be set to a predetermined value selected to provide hysteresis to reduce the occurrence of power oscillation between the upper and lower thresholds. This lower threshold may be hard wired into the power controller or hard wired into the IC that receives the throttle signal. Alternatively, the lower threshold may be modifiable by a user or automatically adjusted within the computer system to, for example, reduce power oscillation. [0035]
  • FIG. 2B is a graph showing the total power consumption versus time for all or a portion of the computer system of FIG. 1 in accordance with an alternate embodiment of the present invention. The graph of FIG. 2B is similar to the graph of FIG. 2A except that for the embodiment of FIG. 2B, once the throttle signal is triggered, the signal is continually asserted for a predetermined period of time, [0036] 200. Once this predetermined period of time, 200, has passed, the throttle signal may be deasserted, and, in response, the IC resumes normal operation. In accordance with this embodiment, the predetermined period of time may be selected to reduce the occurrence of total power consumption oscillation. This predetermined period of time, 200, may be hard wired into the power controller or hard wired into the IC that receives the throttle signal. Alternatively, predetermined period of time, 200, may be modifiable by a user or automatically adjusted within the computer system to, for example, reduce power oscillation.
  • FIG. 3 is a computer [0037] system including processor 310 formed in accordance with an embodiment of the present invention. System clock 301 and a throttle signal line are coupled to clock synchronizer 311 of processor 310. Processor 310 includes bus interface 312 and a core having pipeline 313. Bus interface 312 and pipeline 313 receive separate clock signals from clock synchronizer 311. Synchronization unit 314 of bus interface 312 is coupled to the input and output of pipeline 313 and communicates data with other ICs via system bus 320.
  • In accordance with one embodiment of the present invention, [0038] clock synchronizer 311 of FIG. 3 receives system clock 301 and multiplies the system clock frequency by a first ratio to generate a bus frequency provided to bus interface 312. Other ICs (not shown) coupled to bus 320 communicate with processor 310 at this bus frequency. Clock synchronizer 311 also multiplies the system clock frequency by a second ratio to generate a much higher frequency called a core frequency. The core frequency is provided to pipeline 313. Pipeline 313 operates at this core frequency. Synchronization unit 314 includes synchronization logic to communicate data with pipeline 313 at the core frequency and with bus interface 312 at the bus frequency.
  • When a throttle signal is received by [0039] clock synchronizer 311 of FIG. 3, the core frequency is reduced by multiplying the system clock frequency by a third ratio to generate a reduced core frequency that is slower than the original core frequency. This reduced core frequency is provided to pipeline 313 which then operates at this reduced core frequency. When the throttle signal is deasserted, the core frequency is increased to its original value by multiplying the system clock frequency by the second ratio and applying the resulting high core frequency to pipeline 313. During this core frequency manipulation, the bus frequency provided to bus interface 312 remains consistent. Thus, although the operating frequency (core frequency) of processor 310 is adjusted in response to the throttle signal, the computer system continues to operate undisturbed because processor 310 communicates with the other ICs coupled to bus 320 at a consistent bus frequency.
  • Reducing the core operating frequency of [0040] processor 310 of FIG. 3 reduces the power consumed by processor 310. In accordance with one embodiment of the present invention, an abrupt transition between core frequencies of processor 310 may be achieved by rapidly switching between two multiplication ratios within clock synchronizer 311 in response to the throttle signal. A slower, smoother transition between core frequencies may be achieved by stepping through various multiplication ratios between the high and low core frequencies. A rapid frequency transition may be desirable to provide good reaction time to the detection of a high power state by the power controller. A slower frequency transition may be desirable to help reduce power supply transients. In accordance with one embodiment of the present invention, the speed of the frequency transition may be selected to reduce the occurrence of total power consumption oscillation. The frequency transition speed may be hard wired into the processor, modifiable by a user, or automatically adjusted within the computer system to, for example, reduce power oscillation.
  • For an alternate embodiment of the present invention, in response to the assertion of a throttle signal, [0041] processor 310 of FIG. 3 stalls all or a portion of pipeline 313. Stalling (also called freezing or halting) a pipeline significantly reduces the power consumption of the processor because no or few instructions are executed while the processor is stalled. Alternatively, the clock supplied to the stalled pipeline, or pipeline portion, is turned off. The pipeline stall is released upon deassertion of the throttle signal. The stall may be global, in which all pipelines within processor 310 are stalled, or local, in which only select pipelines are stalled. For an embodiment in which a local stall is implemented, which pipeline, or which portion of the pipeline, is stalled may be predetermined by the processor designer and hard wired into the processor. Alternatively, this determination may be modifiable by a user or automatically selected by the processor.
  • For another embodiment of the present invention, in response to the assertion of a throttle signal, [0042] processor 310 of FIG. 3 issues no-ops to pipeline 313. A no-op requires little or no servicing or activity by the processor upon execution, so the processor requires only a fraction of the power (e.g. less than half) to execute the no-op than it requires to execute most other instructions. Alternatively, the clock supplied to the pipeline, or pipeline portion, that is executing the no-op is turned off. The normal instructions of the program code are again issued to the pipeline upon deassertion of the throttle signal. For one embodiment of the present invention, a mix of both no-ops and normal instructions are issued to the pipeline during assertion of the throttle signal. The relative mix between no-ops and instructions may be predetermined by the processor designer and hard wired into the processor. Alternatively, this determination may be modifiable by a user or automatically selected by the processor.
  • FIG. 4 is a flow chart showing a method of reducing power consumption of a processor in accordance with an embodiment of the present invention. At [0043] step 400, the power, or a parameter that is proportional to power, consumed by the processor is measured. This power may be measured by a meter and the value provided in either digital or analog form to a power controller. For example, an ammeter may provide a measurement of the current consumed by the processor to the power controller. Next, at step 405, the power controller determines if the power has reached an upper threshold. If the power has not reached the threshold, normal operation continues at step 400. If, however, the power has reached the threshold, then, at step 410, the amount of power being consumed by the processor is reduced. This reduction may be in response to a throttle signal sent from the power controller to the processor.
  • Next, at [0044] step 415 of FIG. 4, the power controller determines if the power has reached a lower threshold. For another embodiment of the present invention, the power controller alternatively or additionally determines if a predetermined period of time has elapsed since reducing the power consumption at step 410. If the determination proves to be false, then the power consumption continues to be reduced (or continues in a reduced state, for an alternate embodiment), at step 410 until the determination at step 415 holds true. Once the power has reached a lower threshold or the predetermined period of time has elapsed, normal operation is resumed at step 420 and the method proceeds back to step 400.
  • FIG. 5 is a flow chart showing the method of FIG. 4 in a first embodiment of the present invention. At [0045] step 500, a processor core is operated at a high core frequency while the processor communicates with other ICs of the computer system via a bus operating at a bus frequency. Next, at step 505, it is determined if the processor has received a throttle signal. This throttle signal may be sent to the processor by a power controller upon determining that the total power consumed by all or a portion of the computer system has reached a threshold. If the processor does not receive the throttle signal (or receives a deasserted throttle signal), normal operation of the processor at the high core frequency continues. If, however, the processor receives the throttle signal, then, at step 510, the core frequency of the processor is reduced. The bus continues to communicate with the other ICs of the computer system via the bus operating at the original bus frequency.
  • Next, at [0046] step 515 of FIG. 5, it is determined if the throttle signal to the processor has been deasserted. The frequency is maintained at the reduced state at step 510 until the throttle signal is deasserted. Once the throttle signal is deasserted at step 515, the processor resumes normal operation at the high core frequency at step 520, and the method proceeds back to step 500.
  • FIG. 6 is a flow chart showing the method of FIG. 4 in a second embodiment of the present invention. At [0047] step 600, a processor is operated by continually issuing instructions and executing those instructions via the processor pipeline. The power consumed by the processor is continually measured during this operation and monitored by a power controller. Next, at step 605, the power controller determines if the power has reached an upper threshold. If the power has not reached the upper threshold, normal operation of the processor continues. If, however, the power has reached the upper threshold, then, at step 610, all or a portion of the processor pipeline is stalled to reduce the power consumption of the processor.
  • Next, at [0048] step 615 of FIG. 6, the power controller determines if the power has reached a lower threshold, or, alternatively, the power controller may determine if a predetermined period of time has elapsed since stalling the pipeline at step 610. The pipeline continues to be stalled at step 610 until the power has reached a lower threshold or the predetermined period of time has elapsed. Once the lower threshold is reached or the predetermined period of time has elapsed, normal operation is resumed at step 620 (e.g., the stall of the pipeline is released) and the method proceeds back to step 600.
  • FIG. 7 is a flow chart showing the method of FIG. 4 in a third embodiment of the present invention. At [0049] step 700, a processor is operated by continually issuing instructions and executing those instructions via the processor pipeline. The power consumed by the processor is continually measured during this operation and monitored by a power controller. Next, at step 705, the power controller determines if the power has reached an upper threshold. If the power has not reached the upper threshold, normal operation of the processor continues. If, however, the power has reached the threshold, then, at step 710, no-ops are inserted into the processor pipeline to reduce the power consumption of the processor.
  • Next, at [0050] step 715 of FIG. 7, the power controller determines if the power has reached a lower threshold, or, alternatively, the power controller may determine if a predetermined period of time has elapsed since inserting no-ops into the pipeline at step 710. No-ops continue to be inserted into the pipeline at step 710 until the power has reached a lower threshold or the predetermined period of time has elapsed. Once the lower threshold is reached or the predetermined period of time has elapsed, normal operation is resumed at step 720 (e.g., the normal instruction flow is again issued into the pipeline) and the method proceeds back to step 700.
  • This invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident to persons having the benefit of this disclosure that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. [0051]

Claims (21)

What is claimed is:
1. A method of managing power consumption in a computer system comprising:
taking a measurement of a parameter that is approximately proportional to power consumed by at least a portion of the computer system; and
using the measurement to determine if the power consumed by the portion of the computer system has reached a threshold.
2. The method of
claim 1
, further comprising sending a throttle signal if the power consumed by the portion of the computer system has reached a threshold.
3. The method of
claim 2
, further comprising reducing the power consumed by the portion of the computer system in response to an integrated circuit (IC) receiving the throttle signal.
4. The method of
claim 3
, wherein reducing the power consumed by the portion of the computer system includes reducing a clock frequency or voltage supplied to the IC.
5. The method of
claim 3
, wherein taking the measurement includes measuring a duty cycle of a switching signal in a power supply coupled to a processor, and reducing the power includes reducing power consumed by the processor in response to the processor receiving the throttle signal.
6. The method of
claim 3
, wherein taking the measurement includes measuring a duty cycle of a switching signal in a power supply that supplies the power, and reducing the power includes reducing power consumed by the IC in response to the throttle signal, the IC having a low impact on operation of the computer system.
7. The method of
claim 1
, wherein taking the measurement includes measuring a duty cycle of a switching signal in a power supply coupled to the portion of the computer system.
8. The method of
claim 1
, wherein taking the measurement includes measuring a duty cycle of a switching signal in a power supply that supplies the power.
9. The method of
claim 1
, wherein using the measurement includes determining if the power consumed by the portion of the computer system has reached a threshold that is predetermined to be a constant value.
10. The method of
claim 1
, wherein using the measurement includes determining if the power consumed by the portion of the computer system has reached a threshold that is calculated as a function of time.
11. A method of limiting power consumed by a computer system comprising:
measuring a first parameter that is proportional to power consumed by a first portion of the computer system;
measuring a second parameter that is proportional to power consumed by a second portion of the computer system;
sending a throttle signal to an integrated circuit (IC) of the computer system if a calculation that combines at least the first and second parameters reaches a threshold; and
reducing power consumed by the IC in response to receiving the signal.
12. The method of
claim 11
, further comprising determining if the calculation reaches a threshold that is predetermined to be a user-defined value.
13. The method of
claim 11
, further comprising determining if the calculation reaches a threshold that is calculated as a function of time.
14. The method of
claim 11
, wherein the computer system is a multiprocessor computer system in which the first portion includes a first processor and the second portion includes a second processor.
15. The method of
claim 11
, wherein measuring the first parameter includes measuring a duty cycle of a switching signal of a first power supply coupled to the first portion of the computer system, and measuring the second parameter includes measuring a duty cycle of a switching signal of a second power supply coupled to the second portion of the computer system.
16. A computer system comprising:
a power supply to supply power consumed by the computer system;
a meter coupled to the power supply to measure a value of a parameter that is approximately proportional to the power; and
a controller to send a throttle signal to an integrated circuit (IC) of the computer system if an amount calculated using the value reaches a threshold.
17. The computer system of
claim 16
, wherein the IC is a processor.
18. The computer system of
claim 16
, wherein the parameter is a duty cycle of a switching signal of the power supply.
19. The computer system of
claim 16
, wherein the controller is contained within a bridge of the computer system.
20. The computer system of
claim 16
, wherein the threshold is predetermined to be a value associated with an approximate maximum power that can be consumed by the computer system.
21. The computer system of
claim 16
, wherein the threshold is a function of time.
US09/219,578 1998-12-23 1998-12-23 Method and apparatus of measuring current, voltage, or duty cycle of a power supply to manage power consumption in a computer system Expired - Lifetime US6367023B2 (en)

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US09/219,578 US6367023B2 (en) 1998-12-23 1998-12-23 Method and apparatus of measuring current, voltage, or duty cycle of a power supply to manage power consumption in a computer system
CN998163449A CN1344389B (en) 1998-12-23 1999-11-23 Method and system for managing power consumption in computer system
DE19983848A DE19983848B3 (en) 1998-12-23 1999-11-23 A method and apparatus for managing power consumption in a computer system
PCT/US1999/028047 WO2000039661A1 (en) 1998-12-23 1999-11-23 A method and apparatus for managing power consumption in a computer system
GB0114526A GB2361326B (en) 1998-12-23 1999-11-23 A method and apparatus for managing power consumption in a computer system
KR1020017007988A KR20020008110A (en) 1998-12-23 1999-11-23 A method and apparatus for managing power consumption in a computer system
AU19227/00A AU1922700A (en) 1998-12-23 1999-11-23 A method and apparatus for managing power consumption in a computer system

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Cited By (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003042800A1 (en) * 2001-11-12 2003-05-22 Endress + Hauser Gmbh+Co. Kg Method for regulating the power supply of a number of field devices
US20030177405A1 (en) * 2002-03-15 2003-09-18 Greiner Robert J. Processor temperature control interface
US20040003301A1 (en) * 2002-06-28 2004-01-01 Nguyen Don J. Methods and apparatus to control processor performance to regulate heat generation
US20040181698A1 (en) * 2003-03-13 2004-09-16 Sun Microsystems, Inc. Method and apparatus for supplying power in electronic equipment
US20040268166A1 (en) * 2003-06-30 2004-12-30 Farkas Keith Istvan Controlling power consumption of at least one computer system
US20050044429A1 (en) * 2003-08-22 2005-02-24 Ip-First Llc Resource utilization mechanism for microprocessor power management
US20050060596A1 (en) * 2003-09-12 2005-03-17 An-Sheng Chang Device and method that automatically adjust CPU work frequency
US20050081073A1 (en) * 2003-10-09 2005-04-14 Sun Microsystems, Inc Method and apparatus for controlling the power consumption of a semiconductor device
US20050283624A1 (en) * 2004-06-17 2005-12-22 Arvind Kumar Method and an apparatus for managing power consumption of a server
WO2006004975A1 (en) * 2004-06-30 2006-01-12 Sun Microsystems, Inc. Method and apparatus for power throttling in a multi-thread processor
WO2006037119A2 (en) * 2004-09-28 2006-04-06 Intel Corporation Method and apparatus for varying energy per instruction according to the amount of available parallelism
US20060136074A1 (en) * 2004-12-22 2006-06-22 Susumi Arai Thermal management of a multi-processor computer system
US20070204124A1 (en) * 2003-12-03 2007-08-30 Koninklijke Philips Electronics N.V. Power Saving Method And System
US20070250219A1 (en) * 2002-10-03 2007-10-25 Via Technologies, Inc. Microprocessor capable of dynamically reducing its power consumption in response to varying operating temperature
US20070250736A1 (en) * 2002-10-03 2007-10-25 Via Technologies, Inc. Microprocessor with improved performance during p-state transitions
US20070255972A1 (en) * 2002-10-03 2007-11-01 Via Technologies, Inc. Microprocessor capable of dynamically increasing its performance in response to varying operating temperature
US20080036613A1 (en) * 2002-10-03 2008-02-14 Via Technologies, Inc. Microprocessor with improved thermal monitoring and protection mechanism
US20080114998A1 (en) * 2006-11-12 2008-05-15 Microsemi Corp. - Analog Mixed Signal Group Ltd. Reduced Guard Band for Power Over Ethernet
CN100517264C (en) * 2006-09-20 2009-07-22 鸿富锦精密工业（深圳）有限公司 Computer system average power consumption supervisory instrument
US20110173432A1 (en) * 2010-01-08 2011-07-14 International Business Machines Corporation Reliability and performance of a system-on-a-chip by predictive wear-out based activation of functional components
US20110172984A1 (en) * 2010-01-08 2011-07-14 International Business Machines Corporation Efficiency of static core turn-off in a system-on-a-chip with variation
CN102200821A (en) * 2010-03-25 2011-09-28 联想(北京)有限公司 Computer and power management method thereof
WO2011149746A2 (en) * 2010-05-25 2011-12-01 Microsoft Corporation Resource-based adaptive server loading
US20110292802A1 (en) * 2008-05-05 2011-12-01 Dell Products L.P. System and Method for Automatic Throttling of Resources in an Information Handling System Chassis
US8108863B2 (en) 2005-12-30 2012-01-31 Intel Corporation Load balancing for multi-threaded applications via asymmetric power throttling
US20120159204A1 (en) * 2010-12-21 2012-06-21 Di Tang System and method for power management
WO2012145214A1 (en) 2011-04-22 2012-10-26 Qualcomm Incorporated Sensorless detection and management of thermal loading in a multi-processor wireless device
US8384244B2 (en) 2010-06-09 2013-02-26 Microsoft Corporation Rack-based uninterruptible power supply
US20130091373A1 (en) * 2011-10-06 2013-04-11 Qi-Yan Luo Monitoring device and method for monitoring power parameters of central processing unit of computing device
US8487473B2 (en) 2010-06-24 2013-07-16 Microsoft Corporation Hierarchical power smoothing
US8595515B1 (en) 2007-06-08 2013-11-26 Google Inc. Powering a data center
EP2746956A3 (en) * 2012-12-21 2014-07-23 Nomad Spectrum Limited Computer apparatus
TWI448882B (en) * 2006-11-12 2014-08-11 Microsemi Corp Analog Mixed Si Reduced guard band for power over ethernet
US8952566B2 (en) 2010-10-26 2015-02-10 Microsoft Technology Licensing, Llc Chassis slots accepting battery modules and other module types
US9009500B1 (en) 2012-01-18 2015-04-14 Google Inc. Method of correlating power in a data center by fitting a function to a plurality of pairs of actual power draw values and estimated power draw values determined from monitored CPU utilization of a statistical sample of computers in the data center
US20150323973A1 (en) * 2014-05-09 2015-11-12 Lenovo (Singapore) Pte. Ltd. Method for controlling output of a power supply unit to supply power to multiple processors
US20150378425A1 (en) * 2014-06-27 2015-12-31 Microsoft Corporation Low latency computer system power reduction
US9287710B2 (en) 2009-06-15 2016-03-15 Google Inc. Supplying grid ancillary services using controllable loads
US20160209895A1 (en) * 2003-08-15 2016-07-21 Apple Inc. Methods and apparatuses for operating a data processing system
US20170364132A1 (en) * 2016-06-15 2017-12-21 Intel Corporation Current control for a multicore processor
US10488900B2 (en) 2015-07-28 2019-11-26 Oneplus Technology (Shenzhen) Co., Ltd. Heat dissipation control method for operation resources, operation control system, and storage medium
WO2022031264A1 (en) * 2020-08-03 2022-02-10 Hewlett-Packard Development Company, L.P. Controllers to drive power circuits based on currents drawn
US11342146B2 (en) * 2013-09-06 2022-05-24 Texas Instruments Incorporated System and method for energy monitoring

Families Citing this family (84)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9092595B2 (en) 1997-10-08 2015-07-28 Pact Xpp Technologies Ag Multiprocessor having associated RAM units
JP3297389B2 (en) * 1998-12-07 2002-07-02 インターナショナル・ビジネス・マシーンズ・コーポレーション Power consumption control method and electric equipment
DE69920460T2 (en) * 1999-10-25 2005-01-20 Texas Instruments Inc., Dallas Intelligent power control in distributed processing systems
US6651176B1 (en) * 1999-12-08 2003-11-18 Hewlett-Packard Development Company, L.P. Systems and methods for variable control of power dissipation in a pipelined processor
US6564328B1 (en) * 1999-12-23 2003-05-13 Intel Corporation Microprocessor with digital power throttle
US6694442B2 (en) * 2000-12-18 2004-02-17 Asustek Computer Inc. Method for saving power in a computer by idling system controller and reducing frequency of host clock signal used by system controller
US7164885B2 (en) * 2000-12-18 2007-01-16 Telefonaktiebolaget L M Ericsson (Publ) Method and apparatus for selective service access
US6472848B2 (en) 2001-01-18 2002-10-29 Hewlett-Packard Company Reducing battery discharge current by throttling CPU power
US6745138B2 (en) * 2001-02-23 2004-06-01 Power Measurement, Ltd. Intelligent electronic device with assured data storage on powerdown
US6871150B2 (en) * 2001-02-23 2005-03-22 Power Measurement Ltd. Expandable intelligent electronic device
US7249265B2 (en) * 2001-02-23 2007-07-24 Power Measurement, Ltd. Multi-featured power meter with feature key
US7085824B2 (en) 2001-02-23 2006-08-01 Power Measurement Ltd. Systems for in the field configuration of intelligent electronic devices
US6598209B1 (en) * 2001-02-28 2003-07-22 Sequence Design, Inc. RTL power analysis using gate-level cell power models
US6772366B2 (en) * 2001-03-09 2004-08-03 Intel Corporation Method and apparatus for detecting AC removal
US7111178B2 (en) 2001-09-28 2006-09-19 Intel Corporation Method and apparatus for adjusting the voltage and frequency to minimize power dissipation in a multiprocessor system
US7111179B1 (en) 2001-10-11 2006-09-19 In-Hand Electronics, Inc. Method and apparatus for optimizing performance and battery life of electronic devices based on system and application parameters
US6639428B2 (en) * 2001-12-20 2003-10-28 Advanced Technology Materials, Inc. Method and system for dynamically clocking digital systems based on power usage
TW567408B (en) * 2002-03-29 2003-12-21 Uniwill Comp Corp Apparatus and method for controlling power and clock speed of electronic system
JP3692089B2 (en) * 2002-04-02 2005-09-07 株式会社東芝 Power consumption control method and information processing apparatus
US7230933B2 (en) * 2002-04-17 2007-06-12 Microsoft Corporation Reducing idle power consumption in a networked battery operated device
US7243243B2 (en) * 2002-08-29 2007-07-10 Intel Corporatio Apparatus and method for measuring and controlling power consumption of a computer system
TWI225586B (en) * 2002-09-09 2004-12-21 Quanta Comp Inc Dynamically changing the power consumption apparatus for a computer system
US20040054938A1 (en) * 2002-09-17 2004-03-18 Belady Christian L. Controlling a computer system based on an environmental condition
JP4006634B2 (en) * 2002-10-10 2007-11-14 ソニー株式会社 Information processing apparatus and method, and program
US20040117677A1 (en) * 2002-12-13 2004-06-17 Sanjeev Jahagirdar Throttle of an integrated device
US7210048B2 (en) * 2003-02-14 2007-04-24 Intel Corporation Enterprise power and thermal management
DE10310780B4 (en) * 2003-03-12 2005-12-08 Fujitsu Siemens Computers Gmbh Control of the power consumption of a data processing system
JP2007502477A (en) * 2003-05-27 2007-02-08 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ Power consumption monitoring and control
US7010363B2 (en) * 2003-06-13 2006-03-07 Battelle Memorial Institute Electrical appliance energy consumption control methods and electrical energy consumption systems
US7149605B2 (en) * 2003-06-13 2006-12-12 Battelle Memorial Institute Electrical power distribution control methods, electrical energy demand monitoring methods, and power management devices
TWI280475B (en) * 2003-06-16 2007-05-01 Wistron Corp Method of controlling operation mode of a computer system
US20050086545A1 (en) * 2003-10-17 2005-04-21 Dell Products L.P. Information handling system including fast acting current monitoring and throttling capability
US7034556B1 (en) * 2003-11-05 2006-04-25 Lockheed Martin Corporation Pulsed thermal monitor
US7240225B2 (en) * 2003-11-10 2007-07-03 Dell Products L.P. System and method for throttling power in one or more information handling systems
US7155623B2 (en) * 2003-12-03 2006-12-26 International Business Machines Corporation Method and system for power management including local bounding of device group power consumption
US7752470B2 (en) * 2003-12-03 2010-07-06 International Business Machines Corporation Method and system for power management including device controller-based device use evaluation and power-state control
US20050188231A1 (en) * 2004-02-24 2005-08-25 Lai Terng H. Method and apparatus for indicating use state of SATA external storage device
US7272736B2 (en) 2004-03-03 2007-09-18 Intel Corporation Method and system for fast frequency switch for a power throttle in an integrated device
US6969979B2 (en) * 2004-03-09 2005-11-29 Texas Instruments Incorporated Multiple mode switching regulator having an automatic sensor circuit for power reduction
DE602004030049D1 (en) * 2004-07-15 2010-12-23 Nokia Corp ADAPTIVE VOLTAGE ADJUSTMENT
US7603571B2 (en) * 2004-10-08 2009-10-13 Dell Products L.P. System and method for regulating the power consumption of a computer system
US7388189B2 (en) * 2004-10-27 2008-06-17 Electro Industries/Gauge Tech System and method for connecting electrical devices using fiber optic serial communication
US7430672B2 (en) * 2004-10-27 2008-09-30 Intel Corporation Method and apparatus to monitor power consumption of processor
US7271996B2 (en) * 2004-12-03 2007-09-18 Electro Industries/Gauge Tech Current inputs interface for an electrical device
US20060156041A1 (en) * 2005-01-07 2006-07-13 Lee Zaretsky System and method for power management of plural information handling systems
US7353410B2 (en) * 2005-01-11 2008-04-01 International Business Machines Corporation Method, system and calibration technique for power measurement and management over multiple time frames
US8581169B2 (en) * 2005-01-24 2013-11-12 Electro Industries/Gauge Tech System and method for data transmission between an intelligent electronic device and a remote device
US7472292B2 (en) * 2005-10-03 2008-12-30 Hewlett-Packard Development Company, L.P. System and method for throttling memory power consumption based on status of cover switch of a computer system
US20070094521A1 (en) * 2005-10-24 2007-04-26 Brooks Robert C Current-sensing control system for a microprocessor
CN100377041C (en) * 2005-12-02 2008-03-26 威盛电子股份有限公司 Power source management device and method for multi-processor system
US7650517B2 (en) * 2005-12-19 2010-01-19 International Business Machines Corporation Throttle management for blade system
JP2007233782A (en) * 2006-03-02 2007-09-13 Lenovo Singapore Pte Ltd Control method for heating value, and computer
US7983860B2 (en) * 2006-11-10 2011-07-19 Ocz Technology Group, Inc. Method and system for monitoring power consumption of a computer component
US20080018325A1 (en) * 2006-07-21 2008-01-24 Hon Hai Precision Industry Co., Ltd. Apparatus and method for measuring an output power of a power supply
US7689851B2 (en) * 2006-10-27 2010-03-30 Hewlett-Packard Development Company, L.P. Limiting power state changes to a processor of a computer device
US7832820B2 (en) * 2006-10-31 2010-11-16 Hewlett-Packard Development Company, L.P. Regulating energy based on delivered energy
US7783903B2 (en) 2007-08-07 2010-08-24 International Business Machines Corporation Limiting power consumption by controlling airflow
US7877620B2 (en) 2007-08-17 2011-01-25 International Business Machines Corporation Managing power in a parallel computer
US8034235B2 (en) * 2008-02-14 2011-10-11 Baxter International Inc. Dialysis system including supplemental power source
US8175825B2 (en) * 2008-09-10 2012-05-08 Dell Products L.P. Methods and systems for auto-calibrated power metering in portable information handling systems
US20100286935A1 (en) * 2009-05-05 2010-11-11 POWRtec Methods for Extrapolating an Energy Measurement
US8183826B2 (en) 2009-05-15 2012-05-22 Battelle Memorial Institute Battery charging control methods, electric vehicle charging methods, battery charging apparatuses and rechargeable battery systems
WO2011031175A1 (en) * 2009-09-14 2011-03-17 Akademia Gorniczo-Hutnicza Im. Stanislawa Staszica Method of power control in microprocessor structures and a power control system in microprocessor structures
US20110077878A1 (en) * 2009-09-30 2011-03-31 Lathrop Frederick L Power supply with data communications
US20110145612A1 (en) * 2009-12-16 2011-06-16 International Business Machines Corporation Method and System to Determine and Optimize Energy Consumption of Computer Systems
US8356194B2 (en) 2010-01-28 2013-01-15 Cavium, Inc. Method and apparatus for estimating overshoot power after estimating power of executing events
US8478452B2 (en) 2010-04-06 2013-07-02 Battelle Memorial Institute Grid regulation services for energy storage devices based on grid frequency
US8615672B2 (en) 2010-06-30 2013-12-24 Via Technologies, Inc. Multicore processor power credit management to allow all processing cores to operate at elevated frequency
CN102221875B (en) * 2010-06-30 2014-06-25 威盛电子股份有限公司 Microprocessor, method of operating the microprocessor and computer program product
US9189042B2 (en) 2010-09-27 2015-11-17 Hewlett-Packard Development Company, L.P. Computer system with power measurement
US20120144215A1 (en) * 2010-12-03 2012-06-07 Advanced Micro Devices, Inc. Maximum current limiting method and apparatus
US11234608B2 (en) * 2011-09-02 2022-02-01 Battelle Memorial Institute Extravasation and infiltration detection device with fluid guide provided on a substrate of the detection device to adjust fluid rate based on detection signal
CN102510538A (en) * 2011-11-03 2012-06-20 深圳创维－Rgb电子有限公司 Method and device for processing abnormal state and television
DE102012008926A1 (en) * 2012-02-08 2013-08-08 Liebherr-Hausgeräte Ochsenhausen GmbH Cooling and/or freezing apparatus, has device controller connected with component of apparatus and comprising measuring unit that measures current and/or power consumption of component connected with device controller
JP5880962B2 (en) * 2012-06-12 2016-03-09 ソニー株式会社 Electronic apparatus, calculation method, program, and information processing apparatus
US9223378B2 (en) * 2012-09-26 2015-12-29 Hewlett Packard Enterprise Development Lp Sensing current to protect a fuse
US9846463B2 (en) * 2012-09-28 2017-12-19 Intel Corporation Computing system and processor with fast power surge detection and instruction throttle down to provide for low cost power supply unit
WO2014084842A1 (en) * 2012-11-30 2014-06-05 Intel Corporation Enforcing a power consumption duty cycle in a processor
US9280200B1 (en) 2013-05-20 2016-03-08 Western Digital Technologies, Inc. Automatic peak current throttle of tiered storage elements
US9671844B2 (en) 2013-09-26 2017-06-06 Cavium, Inc. Method and apparatus for managing global chip power on a multicore system on chip
US10585125B2 (en) 2015-05-27 2020-03-10 Electro Industries/ Gaugetech Devices, systems and methods for data transmission over a communication media using modular connectors
US11516899B2 (en) 2015-05-27 2022-11-29 Electro Industries/Gauge Tech Devices, systems and methods for electrical utility submetering
US11023025B2 (en) * 2016-11-16 2021-06-01 Cypress Semiconductor Corporation Microcontroller energy profiler
CN107807693A (en) * 2017-12-01 2018-03-16 普联技术有限公司 Temprature control method, device and the computer-readable recording medium of radio-frequency module

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3941989A (en) * 1974-12-13 1976-03-02 Mos Technology, Inc. Reducing power consumption in calculators
EP0057645A1 (en) 1981-02-04 1982-08-11 FAIRCHILD CAMERA & INSTRUMENT CORPORATION Electrically coded identification of integrated circuit devices
US4465965A (en) * 1981-10-26 1984-08-14 Alan Chernotsky Power limiting apparatus
US4471408A (en) 1982-01-04 1984-09-11 Mcgraw-Edison Company Piggyback code switch device
JPH0833790B2 (en) * 1986-12-26 1996-03-29 株式会社東芝 Power shutdown device for computer
US4951171A (en) * 1989-05-11 1990-08-21 Compaq Computer Inc. Power supply monitoring circuitry for computer system
AU629019B2 (en) * 1989-09-08 1992-09-24 Apple Computer, Inc. Power management for a laptop computer
US5532935A (en) * 1991-10-02 1996-07-02 Kabushiki Kaisha Toshiba Electronic device capable of automatically controlling power assumption of components employed in accordance with operating time period by user
JP3090767B2 (en) * 1992-04-02 2000-09-25 ダイヤセミコンシステムズ株式会社 Computer system power saving controller
JP2563056B2 (en) * 1992-09-09 1996-12-11 克己 金田 Binder binding device having an opening / closing mechanism
US5483656A (en) * 1993-01-14 1996-01-09 Apple Computer, Inc. System for managing power consumption of devices coupled to a common bus
JP3161123B2 (en) * 1993-01-29 2001-04-25 株式会社デンソー Load control device protection device
US5416723A (en) * 1993-03-03 1995-05-16 Milltronics Ltd. Loop powered process control transmitter
US5534734A (en) * 1993-12-09 1996-07-09 Compusci, Inc. Power shedding device
US5452277A (en) 1993-12-30 1995-09-19 International Business Machines Corporation Adaptive system for optimizing disk drive power consumption
US5513361A (en) * 1994-07-25 1996-04-30 Intel Corporation Method and apparatus for reducing power consumption of a fan in a computer system
US5812617A (en) 1994-12-28 1998-09-22 Silcom Research Limited Synchronization and battery saving technique
US5624572A (en) 1995-06-07 1997-04-29 Cobe Laboratories, Inc. Power management system and method for maximizing heat delivered to dialysate in a dialysis machine
US5719800A (en) * 1995-06-30 1998-02-17 Intel Corporation Performance throttling to reduce IC power consumption
US5670825A (en) 1995-09-29 1997-09-23 Intel Corporation Integrated circuit package with internally readable permanent identification of device characteristics
US5740410A (en) 1995-12-15 1998-04-14 Cyrix Corporation Static clock generator
US5926053A (en) 1995-12-15 1999-07-20 National Semiconductor Corporation Selectable clock generation mode
US5694029A (en) * 1996-01-02 1997-12-02 Dell Usa, L.P. Digital measurement of switching regulator current
JPH09251334A (en) * 1996-03-18 1997-09-22 Hitachi Ltd Power consumption control system
GB2313004A (en) 1996-05-07 1997-11-12 Advanced Risc Mach Ltd Digital to analogue converter
US5983355A (en) 1996-05-20 1999-11-09 National Semiconductor Corporation Power conservation method and apparatus activated by detecting specific fixed interrupt signals indicative of system inactivity and excluding prefetched signals
JP3402953B2 (en) * 1996-09-13 2003-05-06 株式会社東芝 Communication method, communication system and communication device
EP1355410A1 (en) 1997-04-30 2003-10-22 Fidelix Y.K. A power supply apparatus
US5978864A (en) * 1997-06-25 1999-11-02 Sun Microsystems, Inc. Method for thermal overload detection and prevention for an intergrated circuit processor
US5948106A (en) * 1997-06-25 1999-09-07 Sun Microsystems, Inc. System for thermal overload detection and prevention for an integrated circuit processor
JPH1138079A (en) 1997-07-17 1999-02-12 Nec Corp Testing method for ball grid array type integrated circuit
JPH11135938A (en) 1997-10-28 1999-05-21 Matsushita Electric Ind Co Ltd Check method of semiconductor device and mounting board
US6167524A (en) * 1998-04-06 2000-12-26 International Business Machines Corporation Apparatus and method for efficient battery utilization in portable personal computers
US6415388B1 (en) * 1998-10-30 2002-07-02 Intel Corporation Method and apparatus for power throttling in a microprocessor using a closed loop feedback system
US6182232B1 (en) * 1999-01-29 2001-01-30 Micron Electronics, Inc. Power and thermal management based on a power supply output

Cited By (104)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003042800A1 (en) * 2001-11-12 2003-05-22 Endress + Hauser Gmbh+Co. Kg Method for regulating the power supply of a number of field devices
US20050055585A1 (en) * 2001-11-12 2005-03-10 Stefan Maier Method for regulating the power supply of a number of multiple field devices
US7231283B2 (en) 2001-11-12 2007-06-12 Endress+ Hauser Gmbh+ Co. Kg Method for regulating the power supply of a number of multiple field devices
US20050273634A1 (en) * 2002-03-15 2005-12-08 Greiner Robert J Processor temperature control interface
US20030177405A1 (en) * 2002-03-15 2003-09-18 Greiner Robert J. Processor temperature control interface
WO2003079170A2 (en) * 2002-03-15 2003-09-25 Intel Corporation (A Delaware Corporation) Processor temperature control interface
WO2003079170A3 (en) * 2002-03-15 2004-09-10 Intel Corp Processor temperature control interface
JP2012238337A (en) * 2002-03-15 2012-12-06 Intel Corp Processor temperature control interface
US7761723B2 (en) 2002-03-15 2010-07-20 Intel Corporation Processor temperature control interface
CN100342300C (en) * 2002-03-15 2007-10-10 英特尔公司 Processor temperature control interface
US20040003301A1 (en) * 2002-06-28 2004-01-01 Nguyen Don J. Methods and apparatus to control processor performance to regulate heat generation
US7814350B2 (en) 2002-10-03 2010-10-12 Via Technologies, Inc. Microprocessor with improved thermal monitoring and protection mechanism
US20070250219A1 (en) * 2002-10-03 2007-10-25 Via Technologies, Inc. Microprocessor capable of dynamically reducing its power consumption in response to varying operating temperature
US7698583B2 (en) 2002-10-03 2010-04-13 Via Technologies, Inc. Microprocessor capable of dynamically reducing its power consumption in response to varying operating temperature
US7774627B2 (en) 2002-10-03 2010-08-10 Via Technologies, Inc. Microprocessor capable of dynamically increasing its performance in response to varying operating temperature
US8412962B2 (en) 2002-10-03 2013-04-02 Via Technologies, Inc. Microprocessor with improved thermal monitoring and protection mechanism
US20100324750A1 (en) * 2002-10-03 2010-12-23 Via Technologies, Inc. Microprocessor with improved thermal monitoring and protection mechanism
US20080036613A1 (en) * 2002-10-03 2008-02-14 Via Technologies, Inc. Microprocessor with improved thermal monitoring and protection mechanism
US20070255972A1 (en) * 2002-10-03 2007-11-01 Via Technologies, Inc. Microprocessor capable of dynamically increasing its performance in response to varying operating temperature
US7770042B2 (en) 2002-10-03 2010-08-03 Via Technologies, Inc. Microprocessor with improved performance during P-state transitions
US20070250736A1 (en) * 2002-10-03 2007-10-25 Via Technologies, Inc. Microprocessor with improved performance during p-state transitions
US7139920B2 (en) * 2003-03-13 2006-11-21 Sun Microsystems, Inc. Method and apparatus for supplying power in electronic equipment
US20040181698A1 (en) * 2003-03-13 2004-09-16 Sun Microsystems, Inc. Method and apparatus for supplying power in electronic equipment
US7272732B2 (en) * 2003-06-30 2007-09-18 Hewlett-Packard Development Company, L.P. Controlling power consumption of at least one computer system
US20040268166A1 (en) * 2003-06-30 2004-12-30 Farkas Keith Istvan Controlling power consumption of at least one computer system
US10775863B2 (en) 2003-08-15 2020-09-15 Apple Inc. Methods and apparatuses for controlling the temperature of a data processing system
US20160209895A1 (en) * 2003-08-15 2016-07-21 Apple Inc. Methods and apparatuses for operating a data processing system
US20050044429A1 (en) * 2003-08-22 2005-02-24 Ip-First Llc Resource utilization mechanism for microprocessor power management
US20050060596A1 (en) * 2003-09-12 2005-03-17 An-Sheng Chang Device and method that automatically adjust CPU work frequency
US7200763B2 (en) 2003-10-09 2007-04-03 Sun Microsystems, Inc. Method and apparatus for controlling the power consumption of a semiconductor device
US20050081073A1 (en) * 2003-10-09 2005-04-14 Sun Microsystems, Inc Method and apparatus for controlling the power consumption of a semiconductor device
US7702940B2 (en) * 2003-12-03 2010-04-20 Koninklijke Philips Electronics N.V. Power saving method and system
US20070204124A1 (en) * 2003-12-03 2007-08-30 Koninklijke Philips Electronics N.V. Power Saving Method And System
WO2006007146A3 (en) * 2004-06-17 2006-03-30 Intel Corp A method and apparatus for managing power consumption of a server
US7418608B2 (en) 2004-06-17 2008-08-26 Intel Corporation Method and an apparatus for managing power consumption of a server
US20050283624A1 (en) * 2004-06-17 2005-12-22 Arvind Kumar Method and an apparatus for managing power consumption of a server
WO2006007146A2 (en) * 2004-06-17 2006-01-19 Intel Corporation A method and apparatus for managing power consumption of a server
US7330988B2 (en) 2004-06-30 2008-02-12 Sun Microsystems, Inc. Method and apparatus for power throttling in a multi-thread processor
US20060020831A1 (en) * 2004-06-30 2006-01-26 Sun Microsystems, Inc. Method and appratus for power throttling in a multi-thread processor
WO2006004975A1 (en) * 2004-06-30 2006-01-12 Sun Microsystems, Inc. Method and apparatus for power throttling in a multi-thread processor
US7437581B2 (en) 2004-09-28 2008-10-14 Intel Corporation Method and apparatus for varying energy per instruction according to the amount of available parallelism
KR100880060B1 (en) 2004-09-28 2009-01-22 인텔 코오퍼레이션 Method and apparatus for varying energy per instruction according to the amount of available parallelism
WO2006037119A2 (en) * 2004-09-28 2006-04-06 Intel Corporation Method and apparatus for varying energy per instruction according to the amount of available parallelism
JP2013218721A (en) * 2004-09-28 2013-10-24 Intel Corp Method and apparatus for varying energy per instruction according to amount of available parallelism
JP2008513912A (en) * 2004-09-28 2008-05-01 インテル・コーポレーション Method and apparatus for varying energy per instruction according to the amount of parallelism available
WO2006037119A3 (en) * 2004-09-28 2007-01-25 Intel Corp Method and apparatus for varying energy per instruction according to the amount of available parallelism
JP2016076268A (en) * 2004-09-28 2016-05-12 インテル・コーポレーション Method and device for varying energy per instruction according to amount of available parallelism
JP2011210275A (en) * 2004-09-28 2011-10-20 Intel Corp Method and apparatus for varying energy per instruction according to amount of available parallelism
JP2015028810A (en) * 2004-09-28 2015-02-12 インテル・コーポレーション System for varying energy per instruction according to amount of available parallelism
US20060136074A1 (en) * 2004-12-22 2006-06-22 Susumi Arai Thermal management of a multi-processor computer system
US7793291B2 (en) * 2004-12-22 2010-09-07 International Business Machines Corporation Thermal management of a multi-processor computer system
US8839258B2 (en) 2005-12-30 2014-09-16 Intel Corporation Load balancing for multi-threaded applications via asymmetric power throttling
US8108863B2 (en) 2005-12-30 2012-01-31 Intel Corporation Load balancing for multi-threaded applications via asymmetric power throttling
CN100517264C (en) * 2006-09-20 2009-07-22 鸿富锦精密工业（深圳）有限公司 Computer system average power consumption supervisory instrument
TWI448882B (en) * 2006-11-12 2014-08-11 Microsemi Corp Analog Mixed Si Reduced guard band for power over ethernet
US7895456B2 (en) * 2006-11-12 2011-02-22 Microsemi Corp. - Analog Mixed Signal Group Ltd Reduced guard band for power over Ethernet
US20080114998A1 (en) * 2006-11-12 2008-05-15 Microsemi Corp. - Analog Mixed Signal Group Ltd. Reduced Guard Band for Power Over Ethernet
US8949646B1 (en) * 2007-06-08 2015-02-03 Google Inc. Data center load monitoring for utilizing an access power amount based on a projected peak power usage and a monitored power usage
US8621248B1 (en) 2007-06-08 2013-12-31 Exaflop Llc Load control in a data center
US11017130B1 (en) 2007-06-08 2021-05-25 Google Llc Data center design
US9946815B1 (en) 2007-06-08 2018-04-17 Google Llc Computer and data center load determination
US10339227B1 (en) 2007-06-08 2019-07-02 Google Llc Data center design
US8700929B1 (en) 2007-06-08 2014-04-15 Exaflop Llc Load control in a data center
US10558768B1 (en) 2007-06-08 2020-02-11 Google Llc Computer and data center load determination
US8645722B1 (en) 2007-06-08 2014-02-04 Exaflop Llc Computer and data center load determination
US8595515B1 (en) 2007-06-08 2013-11-26 Google Inc. Powering a data center
US8601287B1 (en) 2007-06-08 2013-12-03 Exaflop Llc Computer and data center load determination
US20110292802A1 (en) * 2008-05-05 2011-12-01 Dell Products L.P. System and Method for Automatic Throttling of Resources in an Information Handling System Chassis
US9287710B2 (en) 2009-06-15 2016-03-15 Google Inc. Supplying grid ancillary services using controllable loads
US20110173432A1 (en) * 2010-01-08 2011-07-14 International Business Machines Corporation Reliability and performance of a system-on-a-chip by predictive wear-out based activation of functional components
US8571847B2 (en) * 2010-01-08 2013-10-29 International Business Machines Corporation Efficiency of static core turn-off in a system-on-a-chip with variation
US8549363B2 (en) 2010-01-08 2013-10-01 International Business Machines Corporation Reliability and performance of a system-on-a-chip by predictive wear-out based activation of functional components
US20110172984A1 (en) * 2010-01-08 2011-07-14 International Business Machines Corporation Efficiency of static core turn-off in a system-on-a-chip with variation
CN102200821B (en) * 2010-03-25 2013-12-25 联想(北京)有限公司 Computer and power management method thereof
CN102200821A (en) * 2010-03-25 2011-09-28 联想(北京)有限公司 Computer and power management method thereof
US8782443B2 (en) 2010-05-25 2014-07-15 Microsoft Corporation Resource-based adaptive server loading
WO2011149746A3 (en) * 2010-05-25 2012-02-23 Microsoft Corporation Resource-based adaptive server loading
WO2011149746A2 (en) * 2010-05-25 2011-12-01 Microsoft Corporation Resource-based adaptive server loading
US8384244B2 (en) 2010-06-09 2013-02-26 Microsoft Corporation Rack-based uninterruptible power supply
US8487473B2 (en) 2010-06-24 2013-07-16 Microsoft Corporation Hierarchical power smoothing
US8952566B2 (en) 2010-10-26 2015-02-10 Microsoft Technology Licensing, Llc Chassis slots accepting battery modules and other module types
JP2014501982A (en) * 2010-12-21 2014-01-23 インテル・コーポレーション System and method for power management
CN103282854A (en) * 2010-12-21 2013-09-04 英特尔公司 System and method for power management
US8977871B2 (en) * 2010-12-21 2015-03-10 Intel Corporation System and method for power management using a basic input output system
US20120159204A1 (en) * 2010-12-21 2012-06-21 Di Tang System and method for power management
JP2014517956A (en) * 2011-04-22 2014-07-24 クアルコム，インコーポレイテッド Sensorless detection and management of thermal loads in multiprocessor wireless devices
WO2012145214A1 (en) 2011-04-22 2012-10-26 Qualcomm Incorporated Sensorless detection and management of thermal loading in a multi-processor wireless device
US9047067B2 (en) 2011-04-22 2015-06-02 Qualcomm Incorporated Sensorless detection and management of thermal loading in a multi-processor wireless device
US20130091373A1 (en) * 2011-10-06 2013-04-11 Qi-Yan Luo Monitoring device and method for monitoring power parameters of central processing unit of computing device
US9383791B1 (en) 2012-01-18 2016-07-05 Google Inc. Accurate power allotment
US9009500B1 (en) 2012-01-18 2015-04-14 Google Inc. Method of correlating power in a data center by fitting a function to a plurality of pairs of actual power draw values and estimated power draw values determined from monitored CPU utilization of a statistical sample of computers in the data center
EP2746956A3 (en) * 2012-12-21 2014-07-23 Nomad Spectrum Limited Computer apparatus
US11342146B2 (en) * 2013-09-06 2022-05-24 Texas Instruments Incorporated System and method for energy monitoring
US20150323973A1 (en) * 2014-05-09 2015-11-12 Lenovo (Singapore) Pte. Ltd. Method for controlling output of a power supply unit to supply power to multiple processors
US9817465B2 (en) * 2014-06-27 2017-11-14 Microsoft Technology Licensing, Llc Low latency computer system power reduction
US10528113B2 (en) 2014-06-27 2020-01-07 Microsoft Technology Licensing, Llc Low latency computer system power reduction
US20150378425A1 (en) * 2014-06-27 2015-12-31 Microsoft Corporation Low latency computer system power reduction
US10488900B2 (en) 2015-07-28 2019-11-26 Oneplus Technology (Shenzhen) Co., Ltd. Heat dissipation control method for operation resources, operation control system, and storage medium
US10613611B2 (en) * 2016-06-15 2020-04-07 Intel Corporation Current control for a multicore processor
US11237615B2 (en) * 2016-06-15 2022-02-01 Intel Corporation Current control for a multicore processor
US20170364132A1 (en) * 2016-06-15 2017-12-21 Intel Corporation Current control for a multicore processor
US20220197361A1 (en) * 2016-06-15 2022-06-23 Intel Corporation Current control for a multicore processor
US11762449B2 (en) * 2016-06-15 2023-09-19 Intel Corporation Current control for a multicore processor
WO2022031264A1 (en) * 2020-08-03 2022-02-10 Hewlett-Packard Development Company, L.P. Controllers to drive power circuits based on currents drawn

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US6367023B2 (en) 2002-04-02
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