EP2461484A1 - Improved device for configuring a programmable component, system including said device and associated method - Google Patents

Improved device for configuring a programmable component, system including said device and associated method Download PDF

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Publication number
EP2461484A1
EP2461484A1 EP11306114A EP11306114A EP2461484A1 EP 2461484 A1 EP2461484 A1 EP 2461484A1 EP 11306114 A EP11306114 A EP 11306114A EP 11306114 A EP11306114 A EP 11306114A EP 2461484 A1 EP2461484 A1 EP 2461484A1
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EP
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Prior art keywords
programmable component
configuration
programmable
memory space
configuration file
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EP11306114A
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German (de)
French (fr)
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EP2461484B1 (en
Inventor
Jean Murzeau
Jacques Galland
Sébastien Geairon
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Thales SA
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Thales SA
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS

Definitions

  • the subject of the invention is that of programmable components. More particularly, the invention is in the field of programmable components capable of managing the updating of their own configuration.
  • a programmable component When powering up a system comprising a programmable component to be configured, the latter initiates a configuration phase during which it reads a configuration file ("bitstream") contained in a read-only memory to which it is directly connected. the programmable component.
  • bitstream a configuration file
  • the programmable component is configured according to the configuration file.
  • a microprocessor is thus "embedded" in the programmable component. This microprocessor is then able to execute the instructions of an application code stored in another read-only memory, called application memory, which is also connected directly to the programmable component.
  • the application code is dedicated to the microprocessor that has been configured and is therefore associated with a configuration file.
  • the application code allows, thanks to the microprocessor, to download from outside the system and write in the corresponding memories, a new configuration file and the associated application code.
  • This new configuration file corresponds, for example, to a version of the microprocessor integrating functional evolutions, "bug fixes", etc.
  • the configuration phase of the programmable component fails and the programmable component is in a state that does not allow the execution of the application code.
  • the system is not functional. In particular, it is unable to download a new configuration file that would allow a correct reconfiguration of the programmable component. It is thus necessary to report the system to its manufacturer for it forces the reconfiguration of the programmable component from a configuration file stored in a memory external to the system, memory to which the programmable component accesses by means of a removable connector type "JTAG".
  • the invention therefore aims to address the aforementioned problems.
  • the invention aims to make reliable the startup of a programmable component.
  • the invention also relates to a programmable system, characterized in that it comprises a device according to the device presented above, as well as first and second configuration memory space respectively comprising first and second configuration files, and first and second application memory spaces respectively comprising first and second application codes, the first code being executable by the programmable component of said device configured from said first configuration file and the second code being executable by the programmable component of said device configured from said second configuration file, the reliability circuit configuration of the programmable component serving as a connection interface between the programmable component and said memory spaces.
  • the system is closed.
  • the programmable component 10 is of the FPGA (Field Programmable Gate Array) type. It comprises a programmable core 12 comprising a plurality of input / output tabs and logic elements. The core 12 also includes a programmable routing matrix for connecting the logic elements to each other and / or to the input / output tabs.
  • FPGA Field Programmable Gate Array
  • the programmable component 10 also comprises a logic configuration block 14 adapted to perform the configuration of the core 12 from a configuration file that the logic block 14 reads in a configuration read-only memory connected to the programmable component.
  • the core 12 is able to read an application code to be executed in an application read-only memory connected to the programmable component.
  • the configuration memory 20 comprises a first read-only memory 22 of the Flash memory type and a second read-only memory 24 of the Flash memory type.
  • the first memory stores a first configuration file 23.
  • the second memory stores a second configuration file 25.
  • the application memory 30 comprises a read-only memory of the Flash memory type comprising a first memory area 32 and a second memory area 34.
  • the first area stores a first application code 33.
  • the second area stores a second application code 35.
  • the application memory 30 includes an addressing tab corresponding to the most significant bit (here bit 24). If the state of the signal applied to this tab is low 0, the address of the memory 30 to be accessed will belong to the first zone 32. If the state of the signal applied to this tab is high, the address of the The memory 30 to be accessed will belong to the second zone 34.
  • the application memory includes a plurality of other tabs connected to as many tabs of the programmable component 10 to select an address in memory and tabs for reading and writing the programmable component at the selected address. These different legs were not represented on the Figure 1 for the sake of clarity.
  • the monitoring circuit 42 comprises an input tab WDI1 connected to the output tab WDI0 of the programmable component and a WDO ("WatchDog Input") output tab connected, via a diode 43, to the input tab CONFIG of FIG. programmable component.
  • the monitoring circuit 42 is able to emit a reconfiguration signal on its output WDO1 when no inhibition signal has been applied to its input WDI1 from a predetermined duration D.
  • the duration D is adjustable by choosing the values of the capacitor 41.
  • Flip-flop 44 is bistable. It can be in a low state 0 or a high state 1. This state is maintained even when the system is powered off.
  • a status signal of the flip-flop is output on the output tab Q thereof.
  • the flip-flop 44 also comprises a CLK input tab for controlling a change of state of the flip-flop. This input is connected to the output WDO of the monitoring circuit 42. Thus, each time a reconfiguration signal is received from the monitoring circuit 42, the flip-flop 44 changes state and goes from the high level 1 to the low level. 0 or from low level 0 to high level 1.
  • the output tab Q of the flip-flop 44 and the tab WR of the programmable component 10 are connected to the input of the first logic element "OR" 45, the output of which is connected to the node P1.
  • the input of the inverter logic element 49 is connected to the node P1, while its output is connected to the node P2. Thus, if the signal at P1 is high 1, the signal at P2 will be low 0 and if the signal at P1 is low 0, the signal at P2 will be high 1.
  • the three tabs DATA1, DCLK1 and ASD1 of the first configuration memory 22 are connected to the corresponding tabs DATA0, DCLK0, ASD0 of the programmable component 10.
  • the tab CS1 of the first configuration memory 22 is connected to the output of the second logic element "OR" 46, the inputs of which are respectively connected to the node P1 and to the tab CS0 of the programmable component 10.
  • the three tabs DATA2, DCLK2 and ASD2 of the second configuration memory 24 are also connected to the corresponding tabs DATA0, DCLK0, ASD0 of the programmable component 10, bypassing the corresponding connections between the first configuration memory 22 and the programmable component 10.
  • the tab CS2 of the second configuration memory 24 is connected to the output of the third logic element "OR" 48, the inputs of which are respectively connected to the node P2 and to the tab CS0 of the programmable component, as a by-pass of the corresponding connection between the first configuration memory 24 and the programmable component 10.
  • the inputs of the fourth logic element "OR” 47 are respectively connected to the output tab ADRO [24] of the programmable component 10 and to the node P2, while the output of the fourth logic element “OR” 47 is connected to the paw ADR [24] of the application memory 30.
  • the logical elements perform an "Exclusive OR” logical operation (corresponding to a "NAND” operation) whose truth table is as follows: ENTRY 1 ENTRY 2 EXIT 0 0 0 0 1 1 1 0 1 1 1 0
  • step 100 the system is powered up. This has the effect of initializing the clock of the monitoring circuit 42 (step 110). At this moment the flip-flop 44 is, for example, in the low state 0.
  • the latch 44 Since the latch 44 is in the low state 0 and the signal WR is, for example, in the low state 0, the signal at the node P1 is in the low state 0, while the signal at the node P2 is in the state high.
  • the configuration reliability circuit allows the programmable component 10 to access (step 130) the first configuration memory 22.
  • the programmable component 10 then reads the first configuration file 23.
  • step 140 the logic block 14 configures the heart 12 of the programmable component in accordance with the first configuration file.
  • the programmable component 10 accesses a zone the application memory grouping the addresses whose most significant bit is 0. Thus, the programmable component accesses the first zone 32 of the application memory.
  • the programmable component reads the first application code 33. This is actually the code that is executable by the first microprocessor resulting from the configuration of the programmable component according to the first file 23.
  • step 170 the programmable component executes this first application code which includes, among other things, instructions relating to the transmission of an inhibition signal of the reliability circuit 40.
  • step 180 the programmable component 10 transmits an inhibition signal SI taking the high value 1.
  • step 150 0
  • step 200 the monitoring circuit 42 outputs a SCONFIG reconfiguration signal.
  • the reconfiguration signal is applied to the CONFIG input of the programmable component 10 so that the logic block 14 of the programmable component initiates a new configuration phase (step 220).
  • the reconfiguration signal is applied to the input of flip-flop 44 to modify its state.
  • the current state of the flip-flop changes from value 0 to value 1 (step 210).
  • the signal Q being in the high state 1 and the signal WR being in the low state 0, the signal at the node P1 is in the high state 1, while the signal at the node P2 is in the low state 0.
  • the output signal of the logic element 46 is in the low state 0, while the signal at the output of the logic element 48 is in the high state 1.
  • the programmable component is now connected to and accesses the second configuration memory 24 (step 230).
  • the programmable component 10 then reads the second configuration file 25.
  • step 240 the logic block 14 configures the heart 12 of the programmable component according to this second configuration file for the purpose of configuring it as a second microprocessor.
  • the programmable component 10 accesses an area of the memory. application 30 characterized by addresses whose most significant bit is 1. Thus, the programmable component 10 actually accesses the second area 34 of the application memory.
  • the programmable component reads the second application code 35, which effectively corresponds to the code executable by the second microprocessor resulting from the configuration of the programmable component according to the second file 35.
  • step 270 the programmable component executes the second application code.
  • step 280 the programmable component transmits on its leg WDI0 a signal of SI inhibition taking the high value 1.
  • the method can advantageously continue, during the normal execution of the second application code, by a writing phase of a new configuration file instead of the first configuration file that has led to a failure of the configuration phase.
  • This write phase 320 will now be described with reference to the figure 3 .
  • the programmable component 10 downloads (step 330) a new configuration file and associated application code from outside the system, through a set of adapted connections.
  • the programmable component 10 is responsible for writing the new file in the configuration memory and the application code in the application memory.
  • the programmable component 10 To write to the first configuration memory, which is the memory that is opposed to that containing the current configuration file of the programmable component, in step 340, the programmable component 10 transmits a signal on its paw WR taking the high value 1 .
  • the flip-flop being in the high state 1, the output of the element 45 at the node P1 is in the low state 0, while the output of the logic element 49 at the node P2 is in the high state 1.
  • step 350 when the programmable component seeks to access the configuration memory by transmitting a signal CS0 in the high state 1, the output of the logic element 46 is in the high state 1, while that the output of the logic element 48 is in the low state 0.
  • the programmable component 10 writes (step 360) the new downloaded configuration file to the first configuration memory instead of the first corrupted configuration file.
  • the signals CS0 is placed in the low state 0 (step 370).
  • the programmable component therefore does not modify the second configuration file, which is stored in the second configuration memory 24 and which allowed the current configuration of the programmable component.
  • step 350 ' when the programmable component seeks to access the application memory, it transmits an ADRO signal [24] in the high state 1.
  • the output of the logic element 47 is in the low state 0.
  • the programmable component 10 writes (step 360 ') the new application code downloaded, in the first application memory instead of the first application code.
  • the signal ADRO [24] is placed in the low state 0 (step 370).
  • the programmable component therefore does not modify the second application code stored in the second application memory and which is currently executed by the programmable component.
  • figure 4 in the form of a timing diagram, the signals on the tabs WDO of the monitoring circuit, CS0 of the programmable component, CS1 of the first configuration memory 22, CS2 of the second configuration memory 24, and WDI1 of the monitoring circuit (corresponding to the WD0 tab of the programmable component).
  • the configuration memory accesses the configuration memory by changing the signal level CS0. This has the consequence of selecting the first configuration memory 22: the signal CS1 goes to the high state 1, while the signal CS2 remains in the low state 0.
  • the signal CS0 returns to the low state 0, just like the signal CS1.
  • the programmable component attempts to configure itself in accordance with the first configuration file 23.
  • This first configuration file being corrupted, the configuration phase fails and does not end before the duration D.
  • the programmable component then initiates a second configuration phase.
  • the programmable component seeks to access a configuration file. For this it modifies the level of the signal CS0 which passes in the state high 1.
  • the programmable component reads the second configuration file 25.
  • the programmable component places the signal CS0 in the low state 0. This is the reason why the signal CS2 also returns to its low level 0 at this instant.
  • the programmable component uses the second file to configure itself.
  • the configuration phase ends successfully.
  • the programmable component then loads the second application code 35 and executes it.
  • a muting signal SI is sent from the programmable component 10 to the monitoring circuit 42 at time t3.
  • the time interval between the instants t2 and t3 being less than the duration D, the clock of the monitoring circuit 42 is reset before a reconfiguration signal is emitted by the monitoring circuit on its output WDO.
  • the CONFIG tab of the programmable component and the tab WDO of the monitoring circuit are connected through a diode 43.
  • a reconfiguration signal generated by the monitoring circuit can thus be applied to the leg CONFIG while changing the state of the rocker 44, while a reconfiguration signal applied to the CONFIG tab from outside the system, for example by means of a JTAG link, can not be applied to the input of the flip-flop.
  • the diode protects the flip-flop and prevents inadvertent changes in the state of the flip-flop during an externally controlled configuration, for example when testing a configuration file and / or application code.
  • the first and second configuration memory spaces take the form of two memories independent of each other, while the first and second application memory spaces take the form of a single single memory divided into two separately addressable areas .
  • the first and second configuration memory spaces take the form of a single memory divided into two areas, and / or the first and second application memory spaces. take the form of two independent memories.
  • the programmable component must periodically transmit an inhibition signal of the monitoring circuit. This is a classic function for the usual "non-reconfigurable" microprocessors. Indeed, such a microprocessor is usually associated with a monitoring circuit which, if it does not receive an inhibition signal from the microprocessor (for example blocked in the execution of an endless instruction loop) , emits a reset signal ("reset") of the microprocessor.
  • the system comprises N configuration files, stored in N configuration memory spaces, and N application codes, stored in N application memory spaces. Each code is associated with a single configuration file.
  • the reliability circuit is therefore N levels.
  • the programmable component integrates all or part of the reliability circuit of its configuration.
  • Such an advanced programmable component corresponds advantageously at the meeting within the same device elements 10, 42, 43, 44, 45, 46, 47, 48, 49 of the figure 1 .
  • the elements mentioned above are of the same type as the constituent elements of the programmable components: monitoring circuits, flip-flops and logic elements ... It is easy to predict and integrate them during the manufacture of the component Programmable enhanced. In addition, these elements are simple and reliable.
  • the first configuration memory space is a non-reconfigurable memory having a factory configuration file and in which it is impossible to write again; while the second configuration memory space is a reconfigurable memory comprising a configuration update configuration file and in which it is possible to write a new configuration file by overwriting the previous one.
  • the use of the programmable component is then constrained in the sense that it is then possible to modify, during the use of the programmable component, only the second configuration file corresponding to an update of the configuration. This ensures that in case this second configuration file is corrupted, the programmable component can be configured from the factory configuration file.
  • the reliability circuit described in detail above must be adapted to not offer write access to the first configuration memory space. What has just been indicated for the configuration memory spaces is applicable to the application memory spaces.

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Abstract

The device has a selection unit formed of a bistable latch (44) and OR type logic components (45-49), and connecting a programmable component (10) i.e. field-programmable gate array, with configuration memory spaces (22, 24) comprising configuration files (23, 25), when the component searches for file reading access, in two states, respectively. A watchdog circuit (42) has an output pin (WD0) that emits reconfiguration signal to the component for controlling component reconfiguration and the selection unit for state modification, when inhibition signal is not received for a preset time period. Independent claims are also included for the following: (1) a programmable system comprising a programmable device (2) a method for configuring a programmable component.

Description

L'invention a pour domaine celui des composants programmables. Plus particulièrement, l'invention a pour domaine celui des composants programmables capables de gérer la mise à jour de leur propre configuration.The subject of the invention is that of programmable components. More particularly, the invention is in the field of programmable components capable of managing the updating of their own configuration.

Lors de la mise sous tension d'un système comportant un composant programmable devant être configuré, ce dernier initie une phase de configuration au cours de laquelle il lit un fichier de configuration (« bitstream ») contenu dans une mémoire morte à laquelle est directement connecté le composant programmable.When powering up a system comprising a programmable component to be configured, the latter initiates a configuration phase during which it reads a configuration file ("bitstream") contained in a read-only memory to which it is directly connected. the programmable component.

A l'issue de la phase de configuration, si le fichier de configuration ne comporte pas d'erreur, le composant programmable est configuré conformément au fichier de configuration.At the end of the configuration phase, if the configuration file contains no error, the programmable component is configured according to the configuration file.

Dans certaines configurations, un microprocesseur est ainsi « embarqué » dans le composant programmable. Ce microprocesseur est alors apte à exécuter les instructions d'un code applicatif stocké dans une autre mémoire morte, dite mémoire d'application, qui est également connectée directement au composant programmable. Le code applicatif est dédié au microprocesseur qui a été configuré et est donc associé à un fichier de configuration.In some configurations, a microprocessor is thus "embedded" in the programmable component. This microprocessor is then able to execute the instructions of an application code stored in another read-only memory, called application memory, which is also connected directly to the programmable component. The application code is dedicated to the microprocessor that has been configured and is therefore associated with a configuration file.

Avantageusement, le code applicatif permet, grâce au microprocesseur, de télécharger depuis l'extérieur du système et d'écrire dans les mémoires correspondantes, un nouveau fichier de configuration et le code applicatif associé. Ce nouveau fichier de configuration correspond par exemple à une version du microprocesseur intégrant des évolutions fonctionnelles, des corrections de « bogues », etc.Advantageously, the application code allows, thanks to the microprocessor, to download from outside the system and write in the corresponding memories, a new configuration file and the associated application code. This new configuration file corresponds, for example, to a version of the microprocessor integrating functional evolutions, "bug fixes", etc.

En revanche, si le fichier de configuration est corrompu, la phase de configuration du composant programmable échoue et le composant programmable se trouve dans un état qui ne permet pas l'exécution du code applicatif.On the other hand, if the configuration file is corrupted, the configuration phase of the programmable component fails and the programmable component is in a state that does not allow the execution of the application code.

Dans cette situation, le système n'est pas fonctionnel. En particulier, il est incapable de télécharger un nouveau fichier de configuration qui permettrait une reconfiguration correcte du composant programmable. Il est ainsi nécessaire de rapporter le système chez son fabriquant pour que celui-ci force la reconfiguration du composant programmable à partir d'un fichier de configuration stocké dans une mémoire externe au système, mémoire à laquelle le composant programmable accède au moyen d'un connecteur amovible du type « JTAG ».In this situation, the system is not functional. In particular, it is unable to download a new configuration file that would allow a correct reconfiguration of the programmable component. It is thus necessary to report the system to its manufacturer for it forces the reconfiguration of the programmable component from a configuration file stored in a memory external to the system, memory to which the programmable component accesses by means of a removable connector type "JTAG".

L'invention a donc pour but de répondre aux problèmes précités. En particulier, l'invention a pour but de fiabiliser le démarrage d'un composant programmable.The invention therefore aims to address the aforementioned problems. In particular, the invention aims to make reliable the startup of a programmable component.

A cette fin, l'invention a pour objet un dispositif comportant :

  • un composant programmable capable de gérer sa propre configuration, à partir de la donnée d'un fichier de configuration, ayant une sortie apte à émettre un signal d'inhibition lors d'une configuration réussie du composant programmable et une entrée (CONFIG) apte à recevoir un signal de reconfiguration ;
  • un circuit de fiabilisation automatique de la configuration du composant programmable, comportant :
  • un moyen de sélection à au moins deux états, dans un premier état, le moyen de sélection est propre à connecter le composant programmable à un premier espace mémoire de configuration comportant un premier fichier de configuration, au moins quand le composant programmable cherche à accéder en lecture à un fichier de configuration et, dans un second état, le moyen de sélection est propre à connecter le composant programmable à un second espace mémoire de configuration comportant un second fichier de configuration, au moins quand le composant programmable cherche à accéder en lecture à un fichier de configuration ; et,
  • un moyen de surveillance ayant une entrée (WDI1) apte à recevoir le signal d'inhibition émis par le composant programmable et une sortie (WD0) apte à émettre, lorsque aucun signal d'inhibition n'a été reçu pendant une durée prédéterminée, un signal de reconfiguration à destination du composant programmable pour en commander la reconfiguration et du moyen de sélection pour en modifier l'état.
For this purpose, the subject of the invention is a device comprising:
  • a programmable component capable of managing its own configuration, from the data of a configuration file, having an output capable of transmitting an inhibition signal during a successful configuration of the programmable component and an input (CONFIG) capable of receive a reconfiguration signal;
  • an automatic reliability circuit for configuring the programmable component, comprising:
  • a selection means with at least two states, in a first state the selection means is adapted to connect the programmable component to a first configuration memory space having a first configuration file, at least when the programmable component seeks to access reading to a configuration file and in a second state the selection means is adapted to connect the programmable component to a second configuration memory space having a second configuration file, at least when the programmable component seeks to read access to a configuration file and,
  • a monitoring means having an input (WDI1) adapted to receive the inhibition signal emitted by the programmable component and an output (WD0) capable of transmitting, when no inhibition signal has been received for a predetermined duration, a reconfiguration signal to the programmable component to control the reconfiguration and the selection means to change the state.

Suivant des modes particuliers de réalisation, le dispositif comporte une ou plusieurs des caractéristiques suivantes, prise(s) isolément ou suivant toutes les combinaisons techniquement possibles :

  • le composant programmable, une fois configuré en tant que microprocesseur, est propre à exécuter un code applicatif associé au fichier de configuration utilisé, et le moyen de sélection est propre à :
    • dans ledit premier état, connecter le composant programmable à un premier espace mémoire d'application (32) comportant un premier code d'application (33), au moins quand le composant programmable cherche à accéder en lecture à un code d'application ; et,
    • dans ledit second état, connecter le composant programmable à un second espace mémoire d'application (34) comportant un second code d'application (35), au moins quand le composant programmable cherche à accéder en lecture à un code d'application.
  • le moyen de sélection comporte :
    • une bascule à au moins deux états comportant une entrée (CLK) de commande d'une modification de l'état de la bascule et une sortie (Q) d'indication de l'état courrant de la bascule, ladite entrée étant connectée à ladite sortie (WD0) du moyen de surveillance apte à émettre un signal de reconfiguration ; et,
    • une pluralité de composants logiques propre à connecter le composant programmable au premier espace mémoire de configuration ou au second espace mémoire de configuration, en fonction de l'état courrant de la bascule.
  • la pluralité de composants logiques est propre à connecter le composant programmable au premier espace mémoire d'application ou au second espace mémoire d'application, en fonction de l'état courant de la bascule.
  • le composant programmable comporte une patte de sortie (CSO) sur laquelle il est propre à émettre un signal d'accès indiquant qu'il cherche à accéder à un fichier de configuration, et la pluralité de composants logiques est propre à connecter le composant programmable au premier espace mémoire de configuration ou au second espace mémoire de configuration, en fonction de l'état courrant dudit signal d'accès.
  • le composant programmable comporte une patte de sortie (ADRO[24]) sur laquelle il est propre à émettre un signal d'accès indiquant qu'il cherche à accéder à un code applicatif, et la pluralité de composants logiques est propre à connecter le composant programmable au premier espace mémoire d'application ou au second espace mémoire d'application, en fonction de l'état courrant dudit signal d'accès.
  • le premier espace mémoire de configuration est une mémoire non reconfigurable et comporte un fichier de configuration usine, en ce que ledit second espace mémoire de configuration est une mémoire reconfigurable et comporte un fichier de configuration de mise à jour, et le composant programmable étant configuré à partir du fichier de configuration usine ou du fichier de configuration de mise à jour, ledit moyen de sélection est propre à connecter le composant programmable au second espace mémoire de configuration, au moins quand le composant programmable cherche à accéder en écriture à une mémoire de configuration, pour y écrire un nouveau fichier de configuration de mise à jour.
  • le composant programmable comporte une sortie (WR) sur laquelle il est propre à émettre un signal de sélection en écriture d'un espace mémoire de configuration dans lequel écrire un nouveau fichier de configuration, et la pluralité de composants logiques est propre à connecter le composant programmable au premier espace mémoire de configuration ou au second espace mémoire de configuration, en fonction dudit signal de sélection en écriture.
  • le composant programmable comporte le circuit de fiabilisation de la configuration.
  • le composant programmable est du type FPGA.
According to particular embodiments, the device comprises one or more of the following characteristics, taken separately or in any technically possible combination:
  • the programmable component, once configured as a microprocessor, is able to execute an application code associated with the configuration file used, and the selection means is specific to:
    • in said first state, connecting the programmable component to a first application memory space (32) having a first application code (33), at least when the programmable component seeks to read access to an application code; and,
    • in said second state, connecting the programmable component to a second application memory space (34) having a second application code (35), at least when the programmable component seeks to read access to an application code.
  • the selection means comprises:
    • an at least two state latch having a control input (CLK) for a change in the state of the flip-flop and an output (Q) for indicating the current state of the flip-flop, said input being connected to said output (WD0) of the monitoring means adapted to emit a reconfiguration signal; and,
    • a plurality of logic components adapted to connect the programmable component to the first configuration memory space or the second configuration memory space, depending on the current state of the flip-flop.
  • the plurality of logic components is adapted to connect the programmable component to the first application memory space or the second application memory space, depending on the current state of the flip-flop.
  • the programmable component includes an output leg (CSO) on which it is adapted to issue an access signal indicating that it is seeking access to a configuration file, and the plurality of logic components is adapted to connect the programmable component to first configuration memory space or the second configuration memory space, depending on the current state of said access signal.
  • the programmable component comprises an output tab (ADRO [24]) on which it is adapted to emit an access signal indicating that it is seeking access to an application code, and the plurality of logical components is able to connect the component programmable to the first application memory space or the second application memory space, depending on the current state of said access signal.
  • the first configuration memory space is a non-reconfigurable memory and includes a factory configuration file, in that said second configuration memory space is a reconfigurable memory and includes an update configuration file, and the programmable component is configured to from the factory configuration file or the update configuration file, said selection means is adapted to connect the programmable component to the second configuration memory space, at least when the programmable component seeks to write access to a configuration memory , to write a new update configuration file.
  • the programmable component has an output (WR) on which it is adapted to transmit a write select signal of a configuration memory space in which to write a new configuration file, and the plurality of logical components is adapted to connect the component programmable to the first configuration memory space or the second configuration memory space, according to said write selection signal.
  • the programmable component comprises the reliability of the configuration circuit.
  • the programmable component is of the FPGA type.

L'invention a également pour objet un système programmable, caractérisé en ce qu'il comporte un dispositif conforme au dispositif présenté précédent, ainsi que des premier et second espace de mémoire de configuration comportant respectivement des premier et second fichiers de configuration, et des premier et second espaces mémoire d'application comportant respectivement des premier et second codes applicatifs, le premier code étant exécutable par le composant programmable dudit dispositif configuré à partir dudit premier fichier de configuration et le second code étant exécutable par le composant programmable dudit dispositif configuré à partir dudit second fichier de configuration, le circuit de fiabilisation de la configuration du composant programmable servant d'interface de connexion entre le composant programmable et lesdits espaces mémoire.The invention also relates to a programmable system, characterized in that it comprises a device according to the device presented above, as well as first and second configuration memory space respectively comprising first and second configuration files, and first and second application memory spaces respectively comprising first and second application codes, the first code being executable by the programmable component of said device configured from said first configuration file and the second code being executable by the programmable component of said device configured from said second configuration file, the reliability circuit configuration of the programmable component serving as a connection interface between the programmable component and said memory spaces.

De préférence, le système est fermé.Preferably, the system is closed.

L'invention a également pour objet un procédé configuration d'un composant programmable capable de gérer sa propre configuration, à partir de la donnée d'un fichier de configuration, comportant les étapes consistant à :

  • connecter le composant programmable à un premier espace mémoire de configuration comportant un premier fichier de configuration, au moins quand le composant programmable cherche à accéder en lecture à un fichier de configuration ; et, en cas d'échec de la configuration du composant programmable à partir du premier fichier de configuration,
  • commander une reconfiguration du composant programmable et connecter le composant programmable à un second espace mémoire de configuration comportant un second fichier de configuration au moins quand le composant programmable cherche à accéder en lecture à un fichier de configuration.
The invention also relates to a method of configuring a programmable component capable of managing its own configuration, from the data of a configuration file, comprising the steps of:
  • connect the programmable component to a first configuration memory space having a first configuration file, at least when the programmable component seeks to read access to a configuration file; and, in case of failure of configuring the programmable component from the first configuration file,
  • controlling a reconfiguration of the programmable component and connecting the programmable component to a second configuration memory space having a second configuration file at least when the programmable component seeks to read access to a configuration file.

Suivant des modes particuliers de réalisation, le procédé comporte une ou plusieurs des caractéristiques suivantes, prise(s) isolément ou suivant toutes les combinaisons techniquement possibles :

  • le composant programmable, une fois configuré en tant que microprocesseur, étant propre à exécuter un code applicatif associé au fichier de configuration utilisé, le procédé comporte les étapes consistant à :
    • connecter le composant programmable à un premier espace mémoire d'application comportant un premier code applicatif, au moins quand le composant programmable cherche à accéder en lecture à un code applicatif ; et, en cas d'échec de la configuration du composant programmable à partir du premier fichier de configuration,
    • connecter le composant programmable à un second espace mémoire d'application comportant un second code applicatif, au moins quand le composant programmable cherche à accéder en lecture à un code applicatif.
  • une fois le composant programmable configuré en utilisant le fichier de configuration contenu dans l'un parmi les premier et second espaces mémoire de configuration et exécutant le code applicatif associé, le procédé comporte les étapes de :
    • téléchargement par le composant programmable d'un nouveau fichier de configuration ;
    • connecter le composant programmable à l'autre espace mémoire de configuration quand le composant programmable cherche à accéder en écriture à l'espace mémoire de configuration.
According to particular embodiments, the method comprises one or more of the following characteristics, taken separately or in any technically possible combination:
  • the programmable component, once configured as a microprocessor, being able to execute an application code associated with the configuration file used, the method comprises the steps of:
    • connect the programmable component to a first application memory space comprising a first application code, at least when the programmable component seeks to read access to an application code; and, in case of failure of configuring the programmable component from the first configuration file,
    • connect the programmable component to a second application memory space comprising a second application code, at least when the programmable component seeks to read access to an application code.
  • once the programmable component is configured using the configuration file contained in one of the first and second configuration memory spaces and executing the associated application code, the method comprises the steps of:
    • download by the programmable component of a new configuration file;
    • connect the programmable component to the other configuration memory space when the programmable component seeks to write access to the configuration memory space.

L'invention et ses avantages seront mieux compris à la lecture de la description qui va suivre, donnée uniquement à titre d'exemple, et faite en se référant aux dessins annéxés sur lesquels :

  • la Figure 1 est une représentation schématique d'un mode de réalisation du système comportant un composant programmable et un circuit de fiabilisation de sa configuration ;
  • la Figure 2 est un organigramme représentant les étapes de la configuration du composant programmable de la Figure 1 ;
  • la Figure 3 est un organigramme représentant les étapes de l'écriture par le composant programmable de la Figure 1 d'un nouveau fichier de configuration à la place d'un fichier de configuration corrompu ; et,
  • la Figure 4 est un chronogramme représentant les états de différents composants du système de la Figure 1.
The invention and its advantages will be better understood on reading the description which will follow, given solely by way of example, and with reference to the appended drawings in which:
  • the Figure 1 is a schematic representation of an embodiment of the system comprising a programmable component and a reliability of its configuration circuit;
  • the Figure 2 is a flowchart representing the steps of configuring the programmable component of the Figure 1 ;
  • the Figure 3 is a flowchart representing the steps of writing by the programmable component of the Figure 1 a new configuration file instead of a corrupted configuration file; and,
  • the Figure 4 is a chronogram representing the states of different components of the system of the Figure 1 .

Le système 1 représenté sur la Figure 1 comporte :

  • un composant programmable 10 ;
  • une mémoire de configuration 20 ;
  • une mémoire d'application 30 ; et,
  • un circuit 40 de fiabilisation de la configuration du composant programmable regroupant l'ensemble des autres composants représentés sur la figure 1.
The system 1 represented on the Figure 1 has:
  • a programmable component 10;
  • a configuration memory 20;
  • an application memory 30; and,
  • a circuit 40 for reliability of the configuration of the programmable component comprising all the other components represented on the figure 1 .

Le composant programmable 10 est du type FPGA («Field Programmable Gate Array»). Il comporte un coeur programmable 12 comprenant une pluralité de pattes d'entrée/sortie et d'éléments logiques. Le coeur 12 comprend également une matrice de routage programmable pour connecter les éléments logiques entre eux et/ou avec les pattes d'entrée/sortie.The programmable component 10 is of the FPGA (Field Programmable Gate Array) type. It comprises a programmable core 12 comprising a plurality of input / output tabs and logic elements. The core 12 also includes a programmable routing matrix for connecting the logic elements to each other and / or to the input / output tabs.

Le composant programmable 10 comporte également un bloc logique de configuration 14 apte à réaliser la configuration du coeur 12 à partir d'un fichier de configuration que le bloc logique 14 lit dans une mémoire morte de configuration connectée au composant programmable.The programmable component 10 also comprises a logic configuration block 14 adapted to perform the configuration of the core 12 from a configuration file that the logic block 14 reads in a configuration read-only memory connected to the programmable component.

Une fois le composant programmable correctement configuré, le coeur 12 est apte à lire un code d'application à exécuter dans une mémoire morte d'application connectée au composant programmable.Once the programmable component is correctly configured, the core 12 is able to read an application code to be executed in an application read-only memory connected to the programmable component.

La mémoire de configuration 20 comporte une première mémoire morte 22 du type mémoire Flash et une seconde mémoire morte 24 du type mémoire Flash. La première mémoire stocke un premier fichier de configuration 23. La seconde mémoire stocke un second fichier de configuration 25.The configuration memory 20 comprises a first read-only memory 22 of the Flash memory type and a second read-only memory 24 of the Flash memory type. The first memory stores a first configuration file 23. The second memory stores a second configuration file 25.

La mémoire d'application 30 comporte une mémoire morte du type mémoire Flash comprenant une première zone mémoire 32 et une seconde zone mémoire 34. La première zone stocke un premier code applicatif 33. La seconde zone stocke un second code applicatif 35.The application memory 30 comprises a read-only memory of the Flash memory type comprising a first memory area 32 and a second memory area 34. The first area stores a first application code 33. The second area stores a second application code 35.

Le circuit de fiabilisation 40 comporte un moyen de surveillance et un moyen de sélection à au moins deux états. Le moyen de surveillance est un circuit de surveillance (« WatchDog Circuit » en anglais) 42, tandis que le moyen de sélection comporte les éléments suivants :

  • Une bascule 44 à deux états ;
  • Quatre éléments logiques « OU » 45 à 48 aptes à générer en sortie un signal binaire dont la valeur correspond à un « OU » entre les valeurs des deux signaux binaires qui lui sont appliqués en entrée ; et,
  • Un élément logique inverseur 49 apte à générer en sortie un signal binaire dont la valeur est opposée à la valeur du signal binaire qui lui est appliqué en entrée.
The reliability circuit 40 comprises a monitoring means and a selection means with at least two states. The monitoring means is a watchdog circuit 42, while the selection means comprises the following elements:
  • A latch 44 with two states;
  • Four logic elements "OR" 45 to 48 able to output a binary signal whose value corresponds to an "OR" between the values of the two binary signals applied to it at the input; and,
  • An inverter logic element 49 adapted to output a binary signal whose value is opposite to the value of the binary signal applied to it as input.

Le composant programmable 10 comporte les pattes de connexion suivantes :

  • CONFIG : patte d'entrée sur laquelle est reçu un signal de reconfiguration du composant programmable ;
  • WDI0 pour « WatchDog Input » : patte de sortie sur laquelle est émis un signal d'inhibition du circuit de surveillance ;
  • WR, pour « WRite select» : patte de sortie sur laquelle est émis un signal de sélection en écriture permettant de sélectionner l'espace mémoire dans lequel écrire un nouveau fichier de configuration : si le niveau de ce signal est bas, l'écriture s'effectue dans l'espace mémoire dont le fichier de configuration a été utilisé pour réaliser la configuration courante du composant programmable ; si le niveau de ce signal est haut, l'écriture s'effectue dans l'espace mémoire opposé à celui contenant le fichier de configuration qui a été utilisé pour réaliser la configuration courante du composant programmable ;
  • DATA0, DCLK0, ASD0 : trois pattes de lecture/écriture dans la mémoire de configuration connectée au composant programmable ;
  • CS0 : patte de sortie sur laquelle est émis un signal d'accès à la mémoire de configuration connectée au composant programmable ;
  • ADRO[24] : patte de sortie sur laquelle est émis un signal indiquant une phase d'écriture d'un nouveau code applicatif dans la mémoire d'application connectée au composant programmable.
The programmable component 10 comprises the following connection tabs:
  • CONFIG: input tab on which is received a signal for reconfiguration of the programmable component;
  • WDI0 for "WatchDog Input": output leg on which a signal of inhibition of the monitoring circuit is emitted;
  • WR, for "WRite select": output tab on which a write select signal is sent to select the memory space in which to write a new configuration file: if the level of this signal is low, write performs in the memory space whose configuration file was used to perform the current configuration of the programmable component; if the level of this signal is high, the writing is done in the memory space opposite to that containing the configuration file that was used to carry out the current configuration of the programmable component;
  • DATA0, DCLK0, ASD0: three read / write lugs in the configuration memory connected to the programmable component;
  • CS0: output tab on which an access signal is sent to the configuration memory connected to the programmable component;
  • ADRO [24]: output tab on which a signal is sent indicating a writing phase of a new application code in the application memory connected to the programmable component.

La première mémoire de configuration 22 comporte les pattes de connexion suivantes :

  • DATA1, DCLK1, ASD1 : trois pattes d'accès en lecture/écriture à la mémoire ;
  • CS1 : patte d'entrée de réception d'un signal d'accès indiquant la sélection de la mémoire.
The first configuration memory 22 comprises the following connection tabs:
  • DATA1, DCLK1, ASD1: three access lugs read / write to the memory;
  • CS1: input tab for receiving an access signal indicating the selection of the memory.

La seconde mémoire de configuration 24 comporte les pattes de connexion suivantes :

  • DATA2, DCLK2, ASD2 : trois pattes d'accès en lecture/écriture à la mémoire ;
  • CS2 : patte d'entrée de réception d'un signal d'accès indiquant la sélection de la mémoire.
The second configuration memory 24 includes the following connection tabs:
  • DATA2, DCLK2, ASD2: three read / write access lugs to the memory;
  • CS2: input tab for receiving an access signal indicating the selection of the memory.

La mémoire d'application 30 comporte une patte d'adressage correspondant au bit de poids le plus fort (ici le bit 24). Si l'état du signal appliqué sur cette patte est bas 0, l'adresse de la mémoire 30 qui sera accédée appartiendra à la première zone 32. Si l'état du signal appliqué sur cette patte est haut 1, l'adresse de la mémoire 30 qui sera accédée appartiendra à la seconde zone 34. La mémoire d'application comporte une pluralité d'autres pattes connectées à autant de pattes du composant programmable 10 pour sélectionner une adresse en mémoire et des pattes permettant la lecture et l'écriture du composant programmable à l'adresse sélectionnée. Ces différentes pattes n'ont pas été représentées sur la Figure 1 pour des raisons de clarté.The application memory 30 includes an addressing tab corresponding to the most significant bit (here bit 24). If the state of the signal applied to this tab is low 0, the address of the memory 30 to be accessed will belong to the first zone 32. If the state of the signal applied to this tab is high, the address of the The memory 30 to be accessed will belong to the second zone 34. The application memory includes a plurality of other tabs connected to as many tabs of the programmable component 10 to select an address in memory and tabs for reading and writing the programmable component at the selected address. These different legs were not represented on the Figure 1 for the sake of clarity.

Le circuit de surveillance 42 comporte une patte d'entrée WDI1 connectée à la patte de sortie WDI0 du composant programmable et une patte de sortie WDO (« WatchDog Input ») connectée, à travers une diode 43, à la patte d'entrée CONFIG du composant programmable. Le circuit de surveillance 42 est propre à émettre un signal de reconfiguration sur sa sortie WDO1 lorsque aucun signal d'inhibition n'a été appliqué sur son entrée WDI1 depuis une durée D prédéterminée. La durée D est ajustable en choisissant les valeurs du condensateur 41.The monitoring circuit 42 comprises an input tab WDI1 connected to the output tab WDI0 of the programmable component and a WDO ("WatchDog Input") output tab connected, via a diode 43, to the input tab CONFIG of FIG. programmable component. The monitoring circuit 42 is able to emit a reconfiguration signal on its output WDO1 when no inhibition signal has been applied to its input WDI1 from a predetermined duration D. The duration D is adjustable by choosing the values of the capacitor 41.

La bascule 44 est bistable. Elle peut être dans un état bas 0 ou dans un état haut 1. Cet état est maintenu même lorsque le système est hors tension.Flip-flop 44 is bistable. It can be in a low state 0 or a high state 1. This state is maintained even when the system is powered off.

Un signal d'état de la bascule est émis sur la patte de sortie Q de celle-ci.A status signal of the flip-flop is output on the output tab Q thereof.

La bascule 44 comporte également une patte d'entrée CLK de commande d'un changement d'état de la bascule. Cette entrée est connectée à la sortie WDO du circuit de surveillance 42. Ainsi, à chaque réception d'un signal de reconfiguration en provenance du circuit de surveillance 42, la bascule 44 change d'état et passe du niveau haut 1 vers le niveau bas 0 ou du niveau bas 0 au niveau haut 1.The flip-flop 44 also comprises a CLK input tab for controlling a change of state of the flip-flop. This input is connected to the output WDO of the monitoring circuit 42. Thus, each time a reconfiguration signal is received from the monitoring circuit 42, the flip-flop 44 changes state and goes from the high level 1 to the low level. 0 or from low level 0 to high level 1.

La patte de sortie Q de la bascule 44 et la patte WR du composant programmable 10 sont connectées en entrée du premier élément logique « OU » 45, dont la sortie est connectée au noeud P1.The output tab Q of the flip-flop 44 and the tab WR of the programmable component 10 are connected to the input of the first logic element "OR" 45, the output of which is connected to the node P1.

L'entrée de l'élément logique inverseur 49 est connectée au noeud P1, tandis que sa sortie est connectée au noeud P2. Ainsi, si le signal en P1 est haut 1, le signal en P2 sera bas 0 et si le signal en P1 est bas 0, le signal en P2 sera haut 1.The input of the inverter logic element 49 is connected to the node P1, while its output is connected to the node P2. Thus, if the signal at P1 is high 1, the signal at P2 will be low 0 and if the signal at P1 is low 0, the signal at P2 will be high 1.

Les trois pattes DATA1, DCLK1 et ASD1 de la première mémoire de configuration 22 sont connectées aux pattes correspondantes DATA0, DCLK0, ASD0 du composant programmable 10.The three tabs DATA1, DCLK1 and ASD1 of the first configuration memory 22 are connected to the corresponding tabs DATA0, DCLK0, ASD0 of the programmable component 10.

La patte CS1 de la première mémoire de configuration 22 est reliée à la sortie du second élément logique « OU » 46, dont les entrées sont respectivement connectées au noeud P1 et à la patte CS0 du composant programmable 10.The tab CS1 of the first configuration memory 22 is connected to the output of the second logic element "OR" 46, the inputs of which are respectively connected to the node P1 and to the tab CS0 of the programmable component 10.

Les trois pattes DATA2, DCLK2 et ASD2 de la seconde mémoire de configuration 24 sont également connectées aux pattes correspondantes DATA0, DCLK0, ASD0 du composant programmable 10, en dérivation des connexions correspondantes entre la première mémoire de configuration 22 et le composant programmable 10.The three tabs DATA2, DCLK2 and ASD2 of the second configuration memory 24 are also connected to the corresponding tabs DATA0, DCLK0, ASD0 of the programmable component 10, bypassing the corresponding connections between the first configuration memory 22 and the programmable component 10.

La patte CS2 de la seconde mémoire de configuration 24 est reliée à la sortie du troisième élément logique « OU » 48, dont les entrées sont respectivement connectées au noeud P2 et à la patte CS0 du composant programmable, en dérivation de la connexion correspondante entre la première mémoire de configuration 24 et le composant programmable 10.The tab CS2 of the second configuration memory 24 is connected to the output of the third logic element "OR" 48, the inputs of which are respectively connected to the node P2 and to the tab CS0 of the programmable component, as a by-pass of the corresponding connection between the first configuration memory 24 and the programmable component 10.

Enfin, les entrées du quatrième élément logique « OU » 47 sont respectivement connectées à la patte de sortie ADRO[24] du composant programmable 10 et au noeud P2, tandis que la sortie du quatrième élément logique « OU » 47 est reliée à la patte ADR[24] de la mémoire d'application 30.Finally, the inputs of the fourth logic element "OR" 47 are respectively connected to the output tab ADRO [24] of the programmable component 10 and to the node P2, while the output of the fourth logic element "OR" 47 is connected to the paw ADR [24] of the application memory 30.

Les éléments logiques effectuent une opération logique « OU Exclusif » (correspondant à une opération « NON ET ») dont le tableau de vérité est le suivant : ENTREE 1 ENTREE 2 SORTIE 0 0 0 0 1 1 1 0 1 1 1 0 The logical elements perform an "Exclusive OR" logical operation (corresponding to a "NAND" operation) whose truth table is as follows: ENTRY 1 ENTRY 2 EXIT 0 0 0 0 1 1 1 0 1 1 1 0

Sur cette base, le tableau de vérité suivant indique les différents états possibles du système, en indiquant le niveau du signal sur les pattes ou noeuds indiqués par leurs références (les références qui sont soulignées correspondent à des variables décisionnelles, tandis que les autres références correspondent à des variables calculées) Q WR P1 P2 CS0 CS1 CS2 ADR0[24] ADR[24] 0 0 0 1 0 0 1 0 1 1 1 0 1 0 0 1 1 0 0 1 0 0 0 1 0 1 1 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1 1 1 0 1 0 0 1 0 1 1 1 0 1 0 On this basis, the following truth table indicates the different possible states of the system, indicating the level of the signal on the legs or nodes indicated by their references (the references which are underlined correspond to decision variables, while the other references correspond to calculated variables) Q WR P1 P2 CS0 CS1 CS2 ADR0 [24] ADR [24] 0 0 0 1 0 0 1 0 1 1 1 0 1 0 0 1 1 0 0 1 0 0 0 1 0 1 1 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1 1 1 0 1 0 0 1 0 1 1 1 0 1 0

Le procédé mis en oeuvre par le système précédemment décrit va maintenant être présenté par référence à la Figure 2.The method implemented by the system described above will now be presented by reference to the Figure 2 .

A l'étape 100 le système est mis sous tension. Cela a pour effet d'initialiser l'horloge du circuit de surveillance 42 (étape 110). A cet instant la bascule 44 est, par exemple, dans l'état bas 0.In step 100 the system is powered up. This has the effect of initializing the clock of the monitoring circuit 42 (step 110). At this moment the flip-flop 44 is, for example, in the low state 0.

Cela a également pour effet que le bloc logique 14 du composant programmable 10 initie une phase de configuration 120. Celle-ci débute par une étape au cours de laquelle le composant programmable cherche à accéder à un fichier de configuration. Le signal CS0 passe alors dans l'état haut 1.This also has the effect that the logic block 14 of the programmable component 10 initiates a configuration phase 120. This begins with a step during which the programmable component seeks to access a configuration file. The signal CS0 then goes to the high state 1.

La bascule 44 étant dans l'état bas 0 et le signal WR étant, par exemple, dans l'état bas 0, le signal au noeud P1 est dans l'état bas 0, tandis que celui au noeud P2 est dans l'état haut.Since the latch 44 is in the low state 0 and the signal WR is, for example, in the low state 0, the signal at the node P1 is in the low state 0, while the signal at the node P2 is in the state high.

Il s'en suit que la sortie de l'élément logique 46 est dans l'état haut 1 et que la sortie de l'élément logique 48 est dans l'état bas 0.It follows that the output of the logic element 46 is in the high state 1 and that the output of the logic element 48 is in the low state 0.

En conséquence, le circuit de fiabilisation de la configuration permet au composant programmable 10 d'accéder (étape 130) à la première mémoire de configuration 22.As a result, the configuration reliability circuit allows the programmable component 10 to access (step 130) the first configuration memory 22.

Le composant programmable 10 lit alors le premier fichier de configuration 23.The programmable component 10 then reads the first configuration file 23.

Une fois cette lecture terminée, le signal CS0 repasse dans l'état bas 0.Once this reading is finished, the signal CS0 returns to the low state 0.

A l'étape 140, le bloc logique 14 configure le coeur 12 du composant programmable conformément au premier fichier de configuration.In step 140, the logic block 14 configures the heart 12 of the programmable component in accordance with the first configuration file.

Si la configuration du composant programmable s'achève avec succès (étape 150 = 1), le composant programmable 10 cherche ensuite à accéder à un code applicatif à exécuter. Pour cela il émet un signal ADRO[24] dans l'état haut 1.If the configuration of the programmable component is successfully completed (step 150 = 1), the programmable component 10 then seeks to access an application code to be executed. For this, it sends an ADRO signal [24] in the high state 1.

Compte tenu du fait que l'autre entrée de l'élément logique 47 est dans l'état haut 1, la sortie de l'élément logique 47 est dans l'état bas 0. En conséquence, le composant programmable 10 accède à une zone de la mémoire d'application regroupant les adresses dont le bit de poids fort vaut 0. Ainsi, le composant programmable accède à la première zone 32 de la mémoire d'application. A l'étape 160, le composant programmable lit le premier code applicatif 33. Il s'agit effectivement du code qui est exécutable par le premier microprocesseur résultant de la configuration du composant programmable selon le premier fichier 23.In view of the fact that the other input of the logic element 47 is in the high state 1, the output of the logic element 47 is in the low state 0. Consequently, the programmable component 10 accesses a zone the application memory grouping the addresses whose most significant bit is 0. Thus, the programmable component accesses the first zone 32 of the application memory. In step 160, the programmable component reads the first application code 33. This is actually the code that is executable by the first microprocessor resulting from the configuration of the programmable component according to the first file 23.

A l'étape 170, le composant programmable exécute ce premier code applicatif qui comporte, entre autre, des instructions relatives à l'émission d'un signal d'inhibition du circuit de fiabilisation 40.In step 170, the programmable component executes this first application code which includes, among other things, instructions relating to the transmission of an inhibition signal of the reliability circuit 40.

En conséquence, à l'étape 180, le composant programmable 10 émet un signal d'inhibition SI prenant la valeur haute 1.Consequently, in step 180, the programmable component 10 transmits an inhibition signal SI taking the high value 1.

Le signal d'inhibition SI étant reçu par le circuit de surveillance 42 avant la fin de la durée D (étape 190 = 1), le circuit de surveillance 42 réinitialise son horloge (retour à l'étape 110).The inhibition signal SI being received by the monitoring circuit 42 before the end of the duration D (step 190 = 1), the monitoring circuit 42 resets its clock (return to step 110).

Si, en revanche la phase de configuration du composant programmable à partir du premier fichier n'aboutit pas (étape 150 = 0), par exemple parce que ce premier fichier de configuration est corrompu, le circuit de surveillance 42 ne reçoit aucun signal d'inhibition SI au cours de la durée D (étape 190 = 0).If, on the other hand, the configuration phase of the programmable component from the first file does not succeed (step 150 = 0), for example because this first configuration file is corrupted, the monitoring circuit 42 receives no signal from SI inhibition during the duration D (step 190 = 0).

En conséquence, à l'étape 200, le circuit de surveillance 42 émet un signal de reconfiguration SCONFIG.Accordingly, in step 200, the monitoring circuit 42 outputs a SCONFIG reconfiguration signal.

Le signal de reconfiguration est appliqué sur l'entrée CONFIG du composant programmable 10 de manière à ce que le bloc logique 14 du composant programmable initie une nouvelle phase de configuration (étape 220).The reconfiguration signal is applied to the CONFIG input of the programmable component 10 so that the logic block 14 of the programmable component initiates a new configuration phase (step 220).

Simultanément, le signal de reconfiguration est appliqué en entrée de la bascule 44 pour en modifier l'état. L'état courrant de la bascule passe de la valeur 0 à la valeur 1 (étape 210).Simultaneously, the reconfiguration signal is applied to the input of flip-flop 44 to modify its state. The current state of the flip-flop changes from value 0 to value 1 (step 210).

Le signal Q étant dans l'état haut 1 et le signal WR étant dans l'état bas 0, le signal au noeud P1 est dans l'état haut 1, tandis que celui au noeud P2 est dans l'état bas 0.The signal Q being in the high state 1 and the signal WR being in the low state 0, the signal at the node P1 is in the high state 1, while the signal at the node P2 is in the low state 0.

Ainsi, lorsque la phase de configuration conduit à l'émission sur la patte CS0 d'un signal d'accès à la mémoire de configuration, le signal en sortie de l'élément logique 46 est dans l'état bas 0, alors que le signal en sortie du l'élément logique 48 est dans l'état haut 1. De ce fait, le composant programmable est maintenant connecté à la seconde mémoire de configuration 24 et y accède (étape 230).Thus, when the configuration phase leads to the transmission on the tab CS0 of a configuration memory access signal, the output signal of the logic element 46 is in the low state 0, while the signal at the output of the logic element 48 is in the high state 1. As a result, the programmable component is now connected to and accesses the second configuration memory 24 (step 230).

Le composant programmable 10 lit alors le second fichier de configuration 25.The programmable component 10 then reads the second configuration file 25.

Une fois cette lecture terminée, le signal CS0 repasse dans son état bas 0.Once this reading is finished, the signal CS0 returns to its low state 0.

A l'étape 240, le bloc logique 14 configure le coeur 12 du composant programmable conformément à ce second fichier de configuration dans le but de le configurer en tant que second microprocesseur.In step 240, the logic block 14 configures the heart 12 of the programmable component according to this second configuration file for the purpose of configuring it as a second microprocessor.

Si la configuration du composant programmable s'achève avec succès (étape 250 = 1), le composant programmable 10 cherche à accéder à un code applicatif à exécuter. Pour cela il émet un signal ADRO[24] dans l'état haut 1.If the configuration of the programmable component is successfully completed (step 250 = 1), the programmable component 10 seeks to access an application code to be executed. For this, it sends an ADRO signal [24] in the high state 1.

Puisque l'autre entrée de l'élément 47 est dans l'état bas 0, la sortie de l'élément 47 se trouve alors dans l'état haut 1. En conséquence, le composant programmable 10 accède à une zone de la mémoire d'application 30 caractérisée par des adresses dont le bit de poids fort vaut 1. Ainsi, le composant programmable 10 accède effectivement à la seconde zone 34 de la mémoire d'application. A l'étape 260, le composant programmable lit le second code applicatif 35, qui correspond effectivement au code exécutable par le second microprocesseur résultant de la configuration du composant programmable selon le second fichier 35.Since the other input of the element 47 is in the low state 0, the output of the element 47 is then in the high state 1. As a result, the programmable component 10 accesses an area of the memory. application 30 characterized by addresses whose most significant bit is 1. Thus, the programmable component 10 actually accesses the second area 34 of the application memory. In step 260, the programmable component reads the second application code 35, which effectively corresponds to the code executable by the second microprocessor resulting from the configuration of the programmable component according to the second file 35.

A l'étape 270, le composant programmable exécute le second code applicatif.In step 270, the programmable component executes the second application code.

Celui-ci comporte, entre autre, des instructions relatives à l'émission d'un signal d'inhibition SI du circuit de fiabilisation 42. En conséquence, à l'étape 280, le composant programmable émet sur sa patte WDI0 un signal d'inhibition SI prenant la valeur haute 1.This includes, among other things, instructions relating to the transmission of a muting signal SI of the reliability circuit 42. Consequently, in step 280, the programmable component transmits on its leg WDI0 a signal of SI inhibition taking the high value 1.

Le signal d'inhibition SI étant reçu par le circuit de surveillance 42 du circuit de fiabilisation 40 avant la fin de la durée D (étape 290 = 1), le circuit de surveillance réinitialise son horloge (retour à l'étape 110) et n'émet pas de signal de configuration.The muting signal SI being received by the monitoring circuit 42 of the reliability circuit 40 before the end of the duration D (step 290 = 1), the monitoring circuit resets its clock (return to step 110) and n 'emits no configuration signal.

Le procédé peut avantageusement se poursuivre, au cours de l'exécution normale du second code applicatif, par une phase d'écriture d'un nouveau fichier de configuration en remplacement du premier fichier de configuration ayant conduit à un échec de la phase de configuration. Cette phase d'écriture 320 va maintenant être décrite en référence à la figure 3.The method can advantageously continue, during the normal execution of the second application code, by a writing phase of a new configuration file instead of the first configuration file that has led to a failure of the configuration phase. This write phase 320 will now be described with reference to the figure 3 .

Le composant programmable 10 télécharge (étape 330) un nouveau fichier de configuration et un code applicatif associé depuis l'extérieur du système, au travers d'un ensemble de connexions adaptées.The programmable component 10 downloads (step 330) a new configuration file and associated application code from outside the system, through a set of adapted connections.

Le composant programmable 10 se charge d'écrire le nouveau fichier dans la mémoire de configuration et le code applicatif dans la mémoire d'application.The programmable component 10 is responsible for writing the new file in the configuration memory and the application code in the application memory.

Pour écrire dans la première mémoire de configuration, qui est la mémoire qui est opposée à celle contenant le fichier de configuration courante du composant programmable, à l'étape 340, le composant programmable 10 émet un signal sur sa patte WR prenant la valeur haute 1.To write to the first configuration memory, which is the memory that is opposed to that containing the current configuration file of the programmable component, in step 340, the programmable component 10 transmits a signal on its paw WR taking the high value 1 .

La bascule étant dans l'état haut 1, la sortie de l'élément 45 au noeud P1 est dans l'état bas 0, tandis que la sortie de l'élément logique 49 au noeud P2 est dans l'état haut 1.The flip-flop being in the high state 1, the output of the element 45 at the node P1 is in the low state 0, while the output of the logic element 49 at the node P2 is in the high state 1.

En conséquence, à l'étape 350, lorsque le composant programmable cherche à accéder à la mémoire de configuration en émettant un signal CS0 dans l'état haut 1, la sortie de l'élément logique 46 est dans l'état haut 1, tandis que la sortie de l'élément logique 48 est dans l'état bas 0.Accordingly, in step 350, when the programmable component seeks to access the configuration memory by transmitting a signal CS0 in the high state 1, the output of the logic element 46 is in the high state 1, while that the output of the logic element 48 is in the low state 0.

Dans ces conditions, les pattes d'entrée/sortie du composant programmable sont effectivement connectées à la première mémoire de configuration 22.Under these conditions, the input / output tabs of the programmable component are effectively connected to the first configuration memory 22.

Le composant programmable 10 écrit (étape 360) le nouveau fichier de configuration téléchargé, dans la première mémoire de configuration en remplacement du premier fichier de configuration corrompu.The programmable component 10 writes (step 360) the new downloaded configuration file to the first configuration memory instead of the first corrupted configuration file.

A la fin de l'écriture en mémoire de configuration, les signaux CS0 est placé dans l'état bas 0 (étape 370).At the end of the writing in configuration memory, the signals CS0 is placed in the low state 0 (step 370).

Le composant programmable ne modifie donc pas le second fichier de configuration, qui est stocké dans la seconde mémoire de configuration 24 et qui a permis la configuration actuelle du composant programmable.The programmable component therefore does not modify the second configuration file, which is stored in the second configuration memory 24 and which allowed the current configuration of the programmable component.

A l'étape 350', lorsque le composant programmable cherche à accéder à la mémoire d'application, il émet un signal ADRO[24] dans l'état haut 1. La sortie de l'élément logique 47 est dans l'état bas 0.In step 350 ', when the programmable component seeks to access the application memory, it transmits an ADRO signal [24] in the high state 1. The output of the logic element 47 is in the low state 0.

Dans ces conditions, les pattes d'entrée/sortie du composant programmable sont effectivement connectées avec la première mémoire d'application 32.Under these conditions, the input / output tabs of the programmable component are effectively connected with the first application memory 32.

Le composant programmable 10 écrit (étape 360') le nouveau code applicatif téléchargé, dans la première mémoire d'application en remplacement du premier code applicatif.The programmable component 10 writes (step 360 ') the new application code downloaded, in the first application memory instead of the first application code.

A la fin de l'écriture en mémoire d'application, le signal ADRO[24] est placé dans l'état bas 0 (étape 370).At the end of the writing in application memory, the signal ADRO [24] is placed in the low state 0 (step 370).

Le composant programmable ne modifie donc pas le second code applicatif stocké dans la seconde mémoire d'application et qui est actuellement exécuté par le composant programmable.The programmable component therefore does not modify the second application code stored in the second application memory and which is currently executed by the programmable component.

On a représenté à la figure 4, sous forme d'un chronogramme, les signaux sur les pattes WDO du circuit de surveillance, CS0 du composant programmable, CS1 de la première mémoire de configuration 22, CS2 de la seconde mémoire de configuration 24, et WDI1 du circuit de surveillance (correspondant à la patte WD0 du composant programmable).We have shown figure 4 , in the form of a timing diagram, the signals on the tabs WDO of the monitoring circuit, CS0 of the programmable component, CS1 of the first configuration memory 22, CS2 of the second configuration memory 24, and WDI1 of the monitoring circuit (corresponding to the WD0 tab of the programmable component).

A l'instant t1, le système est mis sous tension.At time t1, the system is powered up.

Débute alors une première phase de configuration du composant programmable 10.Then begins a first phase of configuring the programmable component 10.

Dans un premier temps, celui-ci accède à la mémoire de configuration en modifiant le niveau du signal CS0. Ceci a pour conséquence de sélectionner la première mémoire de configuration 22 : le signal CS1 passe dans l'état haut 1, tandis que le signal CS2 reste dans l'état bas 0.At first, it accesses the configuration memory by changing the signal level CS0. This has the consequence of selecting the first configuration memory 22: the signal CS1 goes to the high state 1, while the signal CS2 remains in the low state 0.

Dès que le premier fichier de configuration a été lu, le signal CS0 repasse dans l'état bas 0, tout comme le signal CS1.As soon as the first configuration file has been read, the signal CS0 returns to the low state 0, just like the signal CS1.

Le composant programmable tente alors de se configurer conformément au premier fichier de configuration 23. Ce premier fichier de configuration étant corrompu, la phase de configuration échoue et ne prend pas fin avant la durée D.The programmable component then attempts to configure itself in accordance with the first configuration file 23. This first configuration file being corrupted, the configuration phase fails and does not end before the duration D.

Aucun signal d'inhibition n'étant reçu sur la patte WDI1 du circuit de surveillance 42, celui-ci émet un signal de reconfiguration sur l'entrée CONFIG du composant programmable, à l'instant t2. Cela a également pour effet de modifier l'état de la bascule 44.No inhibition signal is received on the tab WDI1 of the monitoring circuit 42, it emits a reconfiguration signal on the CONFIG input of the programmable component, at time t2. This also has the effect of modifying the state of the flip-flop 44.

Le composant programmable initie alors une seconde phase de configuration.The programmable component then initiates a second configuration phase.

Le composant programmable cherche à accéder à un fichier de configuration. Pour cela il modifie le niveau du signal CS0 qui passe dans l'état haut 1.The programmable component seeks to access a configuration file. For this it modifies the level of the signal CS0 which passes in the state high 1.

Mais, compte tenu de l'état de la bascule 44, cela a pour effet de sélectionner la seconde mémoire de configuration 24 : le signal CS2 passe à la valeur haute 1, tandis que le signal CS1 reste au niveau bas 0.But, taking into account the state of the flip-flop 44, this has the effect of selecting the second configuration memory 24: the signal CS2 goes to the high value 1, while the signal CS1 remains at the low level 0.

Le composant programmable lit le second fichier de configuration 25.The programmable component reads the second configuration file 25.

A l'issue de cet accès à la mémoire de configuration, le composant programmable replace le signal CS0 dans l'état bas 0. C'est la raison pour laquelle, le signal CS2 revient également dans son niveau bas 0 à cet instant.At the end of this access to the configuration memory, the programmable component places the signal CS0 in the low state 0. This is the reason why the signal CS2 also returns to its low level 0 at this instant.

Le composant programmable utilise le second fichier pour se configurer. La phase de configuration s'achève correctement. Le composant programmable charge alors le second code applicatif 35 et l'exécute. Un signal d'inhibition SI est émis depuis le composant programmable 10 vers le circuit de surveillance 42, à l'instant t3. L'intervalle de temps entre les instants t2 et t3 étant inférieur à la durée D, l'horloge du circuit de surveillance 42 est remise à zéro avant qu'un signal de reconfiguration ne soit émis par le circuit de surveillance sur sa sortie WDO.The programmable component uses the second file to configure itself. The configuration phase ends successfully. The programmable component then loads the second application code 35 and executes it. A muting signal SI is sent from the programmable component 10 to the monitoring circuit 42 at time t3. The time interval between the instants t2 and t3 being less than the duration D, the clock of the monitoring circuit 42 is reset before a reconfiguration signal is emitted by the monitoring circuit on its output WDO.

On notera que, sur le schéma de la figure 1, la patte CONFIG du composant programmable et la patte WDO du circuit de surveillance sont reliées à travers une diode 43. Un signal de reconfiguration généré par le circuit de surveillance peut ainsi être appliqué sur la patte CONFIG tout en modifiant l'état de la bascule 44, tandis qu'un signal de reconfiguration appliqué sur la patte CONFIG depuis l'extérieur du système, par exemple au moyen d'un lien JTAG, ne peut pas être appliqué sur l'entrée de la bascule. La diode protège la bascule et évite des changements intempestifs de l'état de la bascule lors d'une configuration commandée depuis l'extérieur, par exemple lors du test d'un fichier de configuration et/ou d'un code applicatif.It will be noted that, on the diagram of the figure 1 , the CONFIG tab of the programmable component and the tab WDO of the monitoring circuit are connected through a diode 43. A reconfiguration signal generated by the monitoring circuit can thus be applied to the leg CONFIG while changing the state of the rocker 44, while a reconfiguration signal applied to the CONFIG tab from outside the system, for example by means of a JTAG link, can not be applied to the input of the flip-flop. The diode protects the flip-flop and prevents inadvertent changes in the state of the flip-flop during an externally controlled configuration, for example when testing a configuration file and / or application code.

Dans le mode de réalisation de la figure 1, les premier et second espaces mémoire de configuration prennent la forme de deux mémoires indépendantes l'une de l'autre, tandis que les premier et second espaces mémoire d'application prennent la forme d'une unique mémoire unique divisée en deux zones adressables séparément. L'homme du métier comprendra que, dans d'autres modes de réalisation, les premier et second espaces mémoire de configuration prennent la forme d'une unique mémoire subdivisée en deux zones, et/ou que les premier et second espaces mémoire d'application prennent la forme de deux mémoires indépendantes.In the embodiment of the figure 1 the first and second configuration memory spaces take the form of two memories independent of each other, while the first and second application memory spaces take the form of a single single memory divided into two separately addressable areas . Those skilled in the art will understand that in other embodiments, the first and second configuration memory spaces take the form of a single memory divided into two areas, and / or the first and second application memory spaces. take the form of two independent memories.

Le composant programmable doit émettre périodiquement un signal d'inhibition du circuit de surveillance. Il s'agit d'une fonction classique pour les microprocesseurs usuels, « non reconfigurables ». En effet, un tel microprocesseur est usuellement associé à un circuit de surveillance qui, s'il ne reçoit pas de signal d'inhibition de la part du microprocesseur (par exemple bloqué dans l'exécution d'une boucle d'instructions sans fin), émet un signal de réinitialisation (« reset ») du microprocesseur.The programmable component must periodically transmit an inhibition signal of the monitoring circuit. This is a classic function for the usual "non-reconfigurable" microprocessors. Indeed, such a microprocessor is usually associated with a monitoring circuit which, if it does not receive an inhibition signal from the microprocessor (for example blocked in the execution of an endless instruction loop) , emits a reset signal ("reset") of the microprocessor.

Dans une autre variante, indépendante des précédentes, le système comporte N fichiers de configuration, stockés dans N espaces mémoire de configuration, et N codes applicatifs, stockés dans N espaces mémoire d'application. Chaque code est associé à un unique fichier de configuration. Le circuit de fiabilisation est par conséquent à N niveaux.In another variant, independent of the previous ones, the system comprises N configuration files, stored in N configuration memory spaces, and N application codes, stored in N application memory spaces. Each code is associated with a single configuration file. The reliability circuit is therefore N levels.

En variante, le composant programmable intègre tout ou partie du circuit de fiabilisation de sa configuration. Un tel composant programmable avancé correspond avantageusement à la réunion au sein d'un même dispositif des éléments 10, 42, 43, 44, 45, 46, 47, 48, 49 de la figure 1. L'homme du métier constatera que les éléments précédemment mentionnés sont du même type que les éléments constitutifs des composants programmables : circuits de surveillance, bascules et éléments logiques... Il est aisé de les prévoir et de les intégrer lors de la fabrication du composant programmable amélioré. De plus, ces éléments sont simples et fiables.In a variant, the programmable component integrates all or part of the reliability circuit of its configuration. Such an advanced programmable component corresponds advantageously at the meeting within the same device elements 10, 42, 43, 44, 45, 46, 47, 48, 49 of the figure 1 . Those skilled in the art will find that the elements mentioned above are of the same type as the constituent elements of the programmable components: monitoring circuits, flip-flops and logic elements ... It is easy to predict and integrate them during the manufacture of the component Programmable enhanced. In addition, these elements are simple and reliable.

Dans encore une autre variante, dans le but d'augmenter la sûreté du fonctionnement du système, le premier espace mémoire de configuration est une mémoire non reconfigurable comportant un fichier de configuration usine et dans laquelle il est impossible d'écrire à nouveau ; tandis que le second espace mémoire de configuration est une mémoire reconfigurable comportant un fichier de configuration de mise à jour de la configuration et dans laquelle il est possible d'écrire un nouveau fichier de configuration en écrasant le précédent. L'utilisation du composant programmable est alors bridée au sens où il n'est alors plus possible de modifier, au cours de l'utilisation du composant programmable, que le second fichier de configuration correspondant à une mise à jour de la configuration. On est ainsi sûr qu'au cas où ce second fichier de configuration est corrompu, le composant programmable pourra être configuré à partir du fichier de configuration usine. Le circuit de fiabilisation décrit en détail précédemment doit être adapté pour ne pas proposer l'accès en écriture au premier espace mémoire de configuration. Ce qui vient d'être indiqué pour les espaces mémoire de configuration est applicable aux espaces mémoire d'application.In yet another variant, in order to increase the safety of the operation of the system, the first configuration memory space is a non-reconfigurable memory having a factory configuration file and in which it is impossible to write again; while the second configuration memory space is a reconfigurable memory comprising a configuration update configuration file and in which it is possible to write a new configuration file by overwriting the previous one. The use of the programmable component is then constrained in the sense that it is then possible to modify, during the use of the programmable component, only the second configuration file corresponding to an update of the configuration. This ensures that in case this second configuration file is corrupted, the programmable component can be configured from the factory configuration file. The reliability circuit described in detail above must be adapted to not offer write access to the first configuration memory space. What has just been indicated for the configuration memory spaces is applicable to the application memory spaces.

Claims (15)

Dispositif programmable, caractérisé en ce qu'il comporte : - un composant programmable (10) capable de gérer sa propre configuration, à partir de la donnée d'un fichier de configuration, ayant une sortie (WDI0 apte à émettre un signal d'inhibition lors d'une configuration réussie du composant programmable et une entrée (CONFIG) apte à recevoir un signal de reconfiguration ; - un circuit (40) de fiabilisation automatique de la configuration du composant programmable, comportant : - un moyen de sélection à au moins deux états (44, 45, 46, 47, 48, 49), dans un premier état, le moyen de sélection est propre à connecter le composant programmable à un premier espace mémoire de configuration (22) comportant un premier fichier de configuration (23), au moins quand le composant programmable cherche à accéder en lecture à un fichier de configuration et, dans un second état, le moyen de sélection est propre à connecter le composant programmable à un second espace mémoire de configuration (24) comportant un second fichier de configuration (25), au moins quand le composant programmable cherche à accéder en lecture à un fichier de configuration ; et, - un moyen de surveillance (42) ayant une entrée (WDI1) apte à recevoir le signal d'inhibition émis par le composant programmable et une sortie (WD0) apte à émettre, lorsque aucun signal d'inhibition n'a été reçu pendant une durée prédéterminée, un signal de reconfiguration à destination du composant programmable pour en commander la reconfiguration et du moyen de sélection pour en modifier l'état. Programmable device, characterized in that it comprises: a programmable component (10) capable of managing its own configuration, from the data of a configuration file, having an output (WDI0 capable of transmitting an inhibition signal during a successful configuration of the programmable component and a input (CONFIG) adapted to receive a reconfiguration signal; a circuit (40) for automatic reliability of the configuration of the programmable component, comprising: a selection means with at least two states (44, 45, 46, 47, 48, 49), in a first state, the selection means is able to connect the programmable component to a first configuration memory space (22) having a first configuration file (23), at least when the programmable component seeks to read access to a configuration file and, in a second state, the selection means is adapted to connect the programmable component to a second memory space of configuration (24) having a second configuration file (25), at least when the programmable component seeks to read access to a configuration file; and, a monitoring means (42) having an input (WDI1) adapted to receive the inhibition signal emitted by the programmable component and an output (WD0) capable of transmitting, when no inhibition signal has been received during a predetermined duration, a reconfiguration signal to the programmable component to control the reconfiguration and selection means to change the state. Dispositif selon la revendication 1, caractérisé en ce que ledit composant programmable (10), une fois configuré en tant que microprocesseur, est propre à exécuter un code applicatif associé au fichier de configuration utilisé, et en ce que ledit moyen de sélection (44, 45, 46, 47, 48, 49) est propre à : - dans ledit premier état, connecter le composant programmable à un premier espace mémoire d'application (32) comportant un premier code d'application (33), au moins quand le composant programmable cherche à accéder en lecture à un code d'application ; et, - dans ledit second état, connecter le composant programmable à un second espace mémoire d'application (34) comportant un second code d'application (35), au moins quand le composant programmable cherche à accéder en lecture à un code d'application, Device according to Claim 1, characterized in that the said programmable component (10), once configured as a microprocessor, is capable of executing an application code associated with the configuration file used, and in that the said selection means (44, 45, 46, 47, 48, 49) is suitable for: in said first state, connecting the programmable component to a first application memory space (32) having a first application code (33), at least when the programmable component seeks to read access to an application code; and, in said second state, connecting the programmable component to a second application memory space (34) comprising a second application code (35), at least when the programmable component seeks to read access to an application code, Dispositif selon la revendication 1 ou la revendication 2, caractérisé en ce que le moyen de sélection comporte : - une bascule (44) à au moins deux états comportant une entrée (CLK) de commande d'une modification de l'état de la bascule et une sortie (Q) d'indication de l'état courrant de la bascule, ladite entrée étant connectée à ladite sortie (WD0) du moyen de surveillance apte à émettre un signal de reconfiguration ; et, - une pluralité de composants logiques (45, 46, 47, 48, 49) propre à connecter le composant programmable au premier espace mémoire de configuration (22) ou au second espace mémoire de configuration (24), en fonction de l'état courrant de la bascule. Device according to claim 1 or claim 2, characterized in that the selection means comprises: a rocker (44) with at least two states comprising a control input (CLK) for a change in the state of the flip-flop and an output (Q) for indicating the current state of the flip-flop, said input being connected to said output (WD0) of the monitoring means adapted to transmit a reconfiguration signal; and, a plurality of logic components (45, 46, 47, 48, 49) adapted to connect the programmable component to the first configuration memory space (22) or the second configuration memory space (24), depending on the current state of the rocker. Dispositif selon la revendication 2 et la revendication 3 en combinaison, caractérisé en ce que ladite pluralité de composants logiques (45, 46, 47, 48, 49) est propre à connecter le composant programmable (10) au premier espace mémoire d'application (32) ou au second espace mémoire d'application (34), en fonction de l'état courant de la bascule.Device according to claim 2 and claim 3 in combination, characterized in that said plurality of logic components (45, 46, 47, 48, 49) is adapted to connect the programmable component (10) to the first application memory space ( 32) or the second application memory space (34), depending on the current state of the flip-flop. Dispositif selon la revendication 3 ou la revendication 4, caractérisé en ce que le composant programmable (10) comporte une patte de sortie (CSO) sur laquelle il est propre à émettre un signal d'accès indiquant qu'il cherche à accéder à un fichier de configuration, et en ce que ladite pluralité de composants logiques (45, 46, 47, 48, 49) est propre à connecter le composant programmable au premier espace mémoire de configuration ou au second espace mémoire de configuration, en fonction de l'état courrant dudit signal d'accès.Device according to Claim 3 or Claim 4, characterized in that the programmable component (10) comprises an output leg (CSO) on which it is able to emit an access signal indicating that it is seeking access to a file. configuration, and that said plurality of logic components (45, 46, 47, 48, 49) is adapted to connect the programmable component to the first configuration memory space or the second configuration memory space, depending on the state current of said access signal. Dispositif selon la revendication 4 ou la revendication 5, caractérisé en ce que le composant programmable (10) comporte une patte de sortie (ADRO[24]) sur laquelle il est propre à émettre un signal d'accès indiquant qu'il cherche à accéder à un code applicatif, et en ce que ladite pluralité de composants logiques (45, 46, 47, 48, 49) est propre à connecter le composant programmable au premier espace mémoire d'application ou au second espace mémoire d'application, en fonction de l'état courrant dudit signal d'accès.Device according to Claim 4 or Claim 5, characterized in that the programmable component (10) comprises an output tab (ADRO [24]) on which it is able to emit an access signal indicating that it is seeking access. to an application code, and in that said plurality of logic components (45, 46, 47, 48, 49) is adapted to connect the programmable component to the first application memory space or the second application memory space, depending on the current state of said access signal. Dispositif selon l'une quelconque des revendications 1 à 6, caractérisé en ce que ledit premier espace mémoire de configuration est une mémoire non reconfigurable et comporte un fichier de configuration usine, en ce que ledit second espace mémoire de configuration est une mémoire reconfigurable et comporte un fichier de configuration de mise à jour, et en ce que, le composant programmable étant configuré à partir du fichier de configuration usine ou du fichier de configuration de mise à jour, ledit moyen de sélection (44, 45, 46, 47, 48, 49) est propre à connecter le composant programmable au second espace mémoire de configuration (24, 22), au moins quand le composant programmable cherche à accéder en écriture à une mémoire de configuration, pour y écrire un nouveau fichier de configuration de mise à jour.Device according to any one of claims 1 to 6, characterized in that said first configuration memory space is a non-reconfigurable memory and comprises a factory configuration file, in that said second configuration memory space is a reconfigurable memory and comprises a configuration file of updated, and in that , the programmable component being configured from the factory configuration file or the update configuration file, said selection means (44, 45, 46, 47, 48, 49) is clean connecting the programmable component to the second configuration memory space (24, 22), at least when the programmable component seeks write access to a configuration memory, to write a new update configuration file thereon. Dispositif selon l'une quelconque des revendications 3 à 7, caractérisé en ce que le composant programmable (10) comporte une sortie (WR) sur laquelle il est propre à émettre un signal de sélection en écriture d'un espace mémoire de configuration dans lequel écrire un nouveau fichier de configuration, et en ce que ladite pluralité de composants logiques (44, 45, 46, 47, 48, 49) est propre à connecter le composant programmable au premier espace mémoire de configuration ou au second espace mémoire de configuration, en fonction dudit signal de sélection en écriture.Device according to any one of claims 3 to 7, characterized in that the programmable component (10) comprises an output (WR) on which it is adapted to transmit a write selection signal of a configuration memory space in which write a new configuration file, and in that said plurality of logic components (44, 45, 46, 47, 48, 49) is adapted to connect the programmable component to the first configuration memory space or second configuration memory space, according to said write select signal. Dispositif selon l'une quelconque des revendications 1 à 8, caractérisé en ce que ledit composant programmable (10) comporte ledit circuit de fiabilisation de la configuration (40).Device according to any one of claims 1 to 8, characterized in that said programmable component (10) comprises said configuration reliability circuit (40). Dispositif selon l'une quelconque des revendications 1 à 9, caractérisé en ce que ledit composant programmable (10) est du type FPGA.Device according to any one of claims 1 to 9, characterized in that said programmable component (10) is of the FPGA type. Système programmable (1), caractérisé en ce qu'il comporte un dispositif conforme à l'une quelconque des revendications 1 à 10, ainsi que des premier et second espace de mémoire de configuration comportant respectivement des premier et second fichiers de configuration, et des premier et second espaces mémoire d'application comportant respectivement des premier et second codes applicatifs, le premier code étant exécutable par le composant programmable dudit dispositif configuré à partir dudit premier fichier de configuration et le second code étant exécutable par le composant programmable dudit dispositif configuré à partir dudit second fichier de configuration, le circuit de fiabilisation de la configuration du composant programmable servant d'interface de connexion entre le composant programmable et lesdits espaces mémoire.Programmable system (1), characterized in that it comprises a device according to any one of claims 1 to 10, and first and second configuration memory spaces respectively comprising first and second configuration files, and first and second application memory spaces respectively comprising first and second application codes, the first code being executable by the programmable component of said device configured from said first configuration file and the second code being executable by the programmable component of said device configured to from said second configuration file, the reliability circuit of the configuration of the programmable component serving as a connection interface between the programmable component and said memory spaces. Système selon la revendication 11, caractérisé en ce qu'il est fermé.System according to Claim 11, characterized in that it is closed. Procédé de configuration d'un composant programmable (10) capable de gérer sa propre configuration, à partir de la donnée d'un fichier de configuration, comportant les étapes consistant à : - connecter le composant programmable à un premier espace mémoire de configuration (22) comportant un premier fichier de configuration (23), au moins quand le composant programmable cherche à accéder en lecture à un fichier de configuration ; et, en cas d'échec de la configuration du composant programmable à partir du premier fichier de configuration, - commander une reconfiguration du composant programmable et connecter le composant programmable à un second espace mémoire de configuration (24) comportant un second fichier de configuration (25) au moins quand le composant programmable cherche à accéder en lecture à un fichier de configuration. A method of configuring a programmable component (10) capable of managing its own configuration, from the data of a configuration file, comprising the steps of: - Connect the programmable component to a first configuration memory space (22) having a first configuration file (23), at least when the programmable component seeks to read access to a configuration file; and, in case of failure of configuring the programmable component from the first configuration file, - Control a reconfiguration of the programmable component and connect the programmable component to a second configuration memory space (24) having a second configuration file (25) at least when the programmable component seeks to read access to a configuration file. Procédé selon la revendication 13, caractérisé en ce que, ledit composant programmable (10) une fois configuré en tant que microprocesseur étant propre à exécuter un code applicatif associé au fichier de configuration utilisé, le procédé comporte les étapes consistant à : - connecter le composant programmable à un premier espace mémoire d'application (32) comportant un premier code applicatif (33), au moins quand le composant programmable cherche à accéder en lecture à un code applicatif ; et, en cas d'échec de la configuration du composant programmable à partir du premier fichier de configuration, - connecter le composant programmable à un second espace mémoire d'application (34) comportant un second code applicatif (35), au moins quand le composant programmable cherche à accéder en lecture à un code applicatif. Method according to claim 13, characterized in that , said programmable component (10) once configured as a microprocessor being able to execute an application code associated with the configuration file used, the method comprises the steps of: - Connect the programmable component to a first application memory space (32) having a first application code (33), at least when the programmable component seeks to read access to an application code; and, in case of failure of configuring the programmable component from the first configuration file, - Connect the programmable component to a second application memory space (34) having a second application code (35), at least when the programmable component seeks to read access to an application code. Procédé selon la revendication 13, caractérisé en ce qu'une fois le composant programmable configuré en utilisant le fichier de configuration contenu dans l'un parmi les premier et second espaces mémoire de configuration (22, 24) et exécutant le code applicatif associé, le procédé comporte les étapes de : - téléchargement par le composant programmable d'un nouveau fichier de configuration ; - connecter le composant programmable à l'autre espace mémoire de configuration (22, 24) quand le composant programmable cherche à accéder en écriture à l'espace mémoire de configuration. Method according to claim 13, characterized in that once the programmable component is configured using the configuration file contained in one of the first and second configuration memory spaces (22, 24) and executing the associated application code, the method comprises the steps of: - download by the programmable component of a new configuration file; - connect the programmable component to the other configuration memory space (22, 24) when the programmable component seeks to write access to the configuration memory space.
EP11306114.7A 2010-09-08 2011-09-07 Improved device for configuring a programmable component, system including said device and associated method Active EP2461484B1 (en)

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KR101920719B1 (en) * 2012-11-19 2019-02-13 삼성전자주식회사 Logic device, digital filter including the same, and method to control the same
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CN113312110A (en) * 2021-06-25 2021-08-27 北京东土军悦科技有限公司 FPGA (field programmable Gate array) configuration system and method

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US7631223B1 (en) * 2006-06-06 2009-12-08 Lattice Semiconductor Corporation Programmable logic device methods and system for providing multi-boot configuration data support

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US9015466B2 (en) 2015-04-21
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FR2964481A1 (en) 2012-03-09

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