EP1547141A4 - Semiconductor multi-package module having wire bond interconnection between stacked packages - Google Patents

Semiconductor multi-package module having wire bond interconnection between stacked packages

Info

Publication number
EP1547141A4
EP1547141A4 EP03754585A EP03754585A EP1547141A4 EP 1547141 A4 EP1547141 A4 EP 1547141A4 EP 03754585 A EP03754585 A EP 03754585A EP 03754585 A EP03754585 A EP 03754585A EP 1547141 A4 EP1547141 A4 EP 1547141A4
Authority
EP
European Patent Office
Prior art keywords
wire bond
package module
semiconductor multi
stacked packages
bond interconnection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP03754585A
Other languages
German (de)
French (fr)
Other versions
EP1547141A2 (en
Inventor
Marcos Karnezos
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ChipPac Inc
Original Assignee
ChipPac Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/632,552 external-priority patent/US20040061213A1/en
Priority claimed from US10/632,549 external-priority patent/US7064426B2/en
Priority claimed from US10/632,550 external-priority patent/US6972481B2/en
Priority claimed from US10/632,553 external-priority patent/US7053476B2/en
Priority claimed from US10/632,551 external-priority patent/US6838761B2/en
Priority claimed from US10/632,568 external-priority patent/US7205647B2/en
Application filed by ChipPac Inc filed Critical ChipPac Inc
Publication of EP1547141A2 publication Critical patent/EP1547141A2/en
Publication of EP1547141A4 publication Critical patent/EP1547141A4/en
Ceased legal-status Critical Current

Links

Classifications

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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
EP03754585A 2002-09-17 2003-09-15 Semiconductor multi-package module having wire bond interconnection between stacked packages Ceased EP1547141A4 (en)

Applications Claiming Priority (15)

Application Number Priority Date Filing Date Title
US632551 1990-12-21
US632553 1990-12-24
US632568 1996-04-15
US632549 2000-08-04
US41159002P 2002-09-17 2002-09-17
US411590P 2002-09-17
US632552 2003-08-02
US632550 2003-08-02
US10/632,552 US20040061213A1 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages
US10/632,549 US7064426B2 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module having wire bond interconnect between stacked packages
US10/632,550 US6972481B2 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages
US10/632,553 US7053476B2 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages
US10/632,551 US6838761B2 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield
US10/632,568 US7205647B2 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages
PCT/US2003/028919 WO2004027823A2 (en) 2002-09-17 2003-09-15 Semiconductor multi-package module having wire bond interconnection between stacked packages

Publications (2)

Publication Number Publication Date
EP1547141A2 EP1547141A2 (en) 2005-06-29
EP1547141A4 true EP1547141A4 (en) 2010-02-24

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EP (1) EP1547141A4 (en)
JP (3) JP4800625B2 (en)
KR (1) KR101166575B1 (en)
AU (1) AU2003272405A1 (en)
TW (3) TWI378548B (en)
WO (1) WO2004027823A2 (en)

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KR20050044925A (en) 2005-05-13
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TWI329918B (en) 2010-09-01
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TWI469301B (en) 2015-01-11
AU2003272405A1 (en) 2004-04-08
JP5602685B2 (en) 2014-10-08
JP2013211589A (en) 2013-10-10
KR101166575B1 (en) 2012-07-18
EP1547141A2 (en) 2005-06-29
WO2004027823A3 (en) 2004-05-21
JP4800625B2 (en) 2011-10-26
TW201017853A (en) 2010-05-01
JP2011181971A (en) 2011-09-15
JP5856103B2 (en) 2016-02-09
WO2004027823A2 (en) 2004-04-01

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