EP0793397A3 - A real-time hardware method and apparatus for reducing queue processing - Google Patents

A real-time hardware method and apparatus for reducing queue processing Download PDF

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Publication number
EP0793397A3
EP0793397A3 EP97301015A EP97301015A EP0793397A3 EP 0793397 A3 EP0793397 A3 EP 0793397A3 EP 97301015 A EP97301015 A EP 97301015A EP 97301015 A EP97301015 A EP 97301015A EP 0793397 A3 EP0793397 A3 EP 0793397A3
Authority
EP
European Patent Office
Prior art keywords
queue
packet
pointer
hold
processed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP97301015A
Other languages
German (de)
French (fr)
Other versions
EP0793397A2 (en
Inventor
G.N. Srinivasa Prasanna
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia of America Corp
Original Assignee
Lucent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lucent Technologies Inc filed Critical Lucent Technologies Inc
Publication of EP0793397A2 publication Critical patent/EP0793397A2/en
Publication of EP0793397A3 publication Critical patent/EP0793397A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5651—Priority, marking, classes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5679—Arbitration or scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management

Abstract

In a simple high speed Real-Time method and apparatus for processing a queue in a network queue server, long packets (20) at the beginning of the queue are processed while a pointer (80) chains down the queue to find shorter packets (40). When a shorter packet (40) is found the pointer (80) stops and waits for a timing threshold to be met. When the timing threshold is met the short packet is processed until completion and then work is resumed on the long packet. The method is implemented using a pointer (60) to identify the position in the queue that is currently being processed, a pointer (80) to search for the shorter packets, two registers (70,90) to hold values of the respective pointers and memory to hold the location of the discontinued packet (20). An additional register (20) is utilized to hold the incremented cycle processing time, and a final register (150) is used to hold a threshold value for processing a packet. Lastly, a previous pseudo head register (110) is also utilized when the queue is not doubly linked.
EP97301015A 1996-02-27 1997-02-18 A real-time hardware method and apparatus for reducing queue processing Withdrawn EP0793397A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/607,730 US6201807B1 (en) 1996-02-27 1996-02-27 Real-time hardware method and apparatus for reducing queue processing
US607730 1996-02-27

Publications (2)

Publication Number Publication Date
EP0793397A2 EP0793397A2 (en) 1997-09-03
EP0793397A3 true EP0793397A3 (en) 2000-07-19

Family

ID=24433486

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97301015A Withdrawn EP0793397A3 (en) 1996-02-27 1997-02-18 A real-time hardware method and apparatus for reducing queue processing

Country Status (3)

Country Link
US (1) US6201807B1 (en)
EP (1) EP0793397A3 (en)
JP (1) JPH09321797A (en)

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US6668317B1 (en) * 1999-08-31 2003-12-23 Intel Corporation Microengine for parallel processor architecture
US6983350B1 (en) 1999-08-31 2006-01-03 Intel Corporation SDRAM controller for parallel processor architecture
US6606704B1 (en) * 1999-08-31 2003-08-12 Intel Corporation Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode
WO2001016702A1 (en) 1999-09-01 2001-03-08 Intel Corporation Register set used in multithreaded parallel processor architecture
US6532509B1 (en) 1999-12-22 2003-03-11 Intel Corporation Arbitrating command requests in a parallel multi-threaded processing system
US6694380B1 (en) 1999-12-27 2004-02-17 Intel Corporation Mapping requests from a processing unit that uses memory-mapped input-output space
US6625654B1 (en) * 1999-12-28 2003-09-23 Intel Corporation Thread signaling in multi-threaded network processor
US6631430B1 (en) * 1999-12-28 2003-10-07 Intel Corporation Optimizations to receive packet status from fifo bus
US6560667B1 (en) * 1999-12-28 2003-05-06 Intel Corporation Handling contiguous memory references in a multi-queue system
US6307789B1 (en) * 1999-12-28 2001-10-23 Intel Corporation Scratchpad memory
US6661794B1 (en) * 1999-12-29 2003-12-09 Intel Corporation Method and apparatus for gigabit packet assignment for multithreaded packet processing
US6584522B1 (en) * 1999-12-30 2003-06-24 Intel Corporation Communication between processors
US6631462B1 (en) * 2000-01-05 2003-10-07 Intel Corporation Memory shared between processing threads
US7006515B1 (en) * 2000-04-07 2006-02-28 Omneon Video Networks Isochronous queue and buffer management
US7681018B2 (en) 2000-08-31 2010-03-16 Intel Corporation Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set
US6868476B2 (en) * 2001-08-27 2005-03-15 Intel Corporation Software controlled content addressable memory in a general purpose execution datapath
US7126952B2 (en) * 2001-09-28 2006-10-24 Intel Corporation Multiprotocol decapsulation/encapsulation control structure and packet protocol conversion method
US6772202B2 (en) 2001-11-28 2004-08-03 Gamespy Industries, Inc. Queuing system, method and computer program product for network data transfer
US7895239B2 (en) 2002-01-04 2011-02-22 Intel Corporation Queue arrays in network devices
US6934951B2 (en) * 2002-01-17 2005-08-23 Intel Corporation Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section
US7471688B2 (en) * 2002-06-18 2008-12-30 Intel Corporation Scheduling system for transmission of cells to ATM virtual circuits and DSL ports
US7433307B2 (en) * 2002-11-05 2008-10-07 Intel Corporation Flow control in a network environment
US7433364B2 (en) * 2003-12-24 2008-10-07 Intel Corporation Method for optimizing queuing performance
US20050198361A1 (en) * 2003-12-29 2005-09-08 Chandra Prashant R. Method and apparatus for meeting a given content throughput using at least one memory channel
US7213099B2 (en) * 2003-12-30 2007-05-01 Intel Corporation Method and apparatus utilizing non-uniformly distributed DRAM configurations and to detect in-range memory address matches
GB2458952B (en) * 2008-04-04 2012-06-13 Micron Technology Inc Queue processing method
JP5416168B2 (en) 2011-05-19 2014-02-12 富士通テレコムネットワークス株式会社 Communication device

Citations (4)

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Publication number Priority date Publication date Assignee Title
EP0372795A2 (en) * 1988-12-06 1990-06-13 AT&T Corp. Bandwidth allocation and congestion control scheme for an integrated voice and data network
EP0378195A2 (en) * 1989-01-10 1990-07-18 Kabushiki Kaisha Toshiba Buffer device suitable for asynchronous transfer mode communication
EP0473330A1 (en) * 1990-08-23 1992-03-04 AT&T Corp. Serving constant bit rate traffic in a broadband data switch
US5313579A (en) * 1992-06-04 1994-05-17 Bell Communications Research, Inc. B-ISDN sequencer chip device

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US5224099A (en) * 1991-05-17 1993-06-29 Stratacom, Inc. Circuitry and method for fair queuing and servicing cell traffic using hopcounts and traffic classes
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US5319753A (en) * 1992-09-29 1994-06-07 Zilog, Inc. Queued interrupt mechanism with supplementary command/status/message information
DE69305734T2 (en) * 1993-06-30 1997-05-15 Ibm Programmable high-performance data communication adaptation for high-speed packet transmission networks
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JPH0936912A (en) * 1995-07-14 1997-02-07 Fujitsu Ltd Buffer control system
US5956342A (en) * 1995-07-19 1999-09-21 Fujitsu Network Communications, Inc. Priority arbitration for point-to-point and multipoint transmission

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0372795A2 (en) * 1988-12-06 1990-06-13 AT&T Corp. Bandwidth allocation and congestion control scheme for an integrated voice and data network
EP0378195A2 (en) * 1989-01-10 1990-07-18 Kabushiki Kaisha Toshiba Buffer device suitable for asynchronous transfer mode communication
EP0473330A1 (en) * 1990-08-23 1992-03-04 AT&T Corp. Serving constant bit rate traffic in a broadband data switch
US5313579A (en) * 1992-06-04 1994-05-17 Bell Communications Research, Inc. B-ISDN sequencer chip device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
MARINO G ET AL: "A HARDWARE PLATFORM FOR B-ISDN SERVICES MULTIPLEXING: DESIGN AND PERFORMANCE OF AAL AND ATM LAYERS", PROCEEDINGS OF THE GLOBAL TELECOMMUNICATIONS CONFERENCE (GLOBECOM),US,NEW YORK, IEEE, vol. -, 1993, pages 1844 - 1848, XP000436128 *

Also Published As

Publication number Publication date
US6201807B1 (en) 2001-03-13
EP0793397A2 (en) 1997-09-03
JPH09321797A (en) 1997-12-12

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