EP0357485A1 - Method for the line-per-line control of an alternating-type plasma panel with a coplanar support - Google Patents

Abstract

The invention relates to a method for the line-per-line control of the pixels (PX1 to PX16) of a plasma panel (1) and applies in the case where a pixel (PX1 to PX16) is defined at the meeting point of a column electrode (X1 to X4) with a pair of service electrodes (P1 to P4). <??>The method of the invention permits, in particular, a reduced cycle time (T,T') with a small number of voltage levels applied to different electrodes (X1 to X4, Y1 to Y4, E1 to E4) to be obtained. For this purpose, according to a characteristic of the invention, the method consists in blanking out the pixels (PX1 to PX16) from one line (L1 to L4 completely) solely by blanking-out discharges generated between the electrodes (Y1 to Y4, E1 to E4) of the corresponding electrode pair (P1 to P4). <IMAGE>

Description

The present invention relates to a method of line-by-line control of a plasma panel of the alternative type with coplanar maintenance, and particularly of a plasma panel in which each elementary image point is defined substantially at the intersection of a first electrode. called "column electrode" with two other parallel electrodes called "maintenance electrodes".

Plasma panels are flat screen display devices, which allow the display of alphanumeric, graphic or other images, in color or not. These panels work on the principle of an emission of light produced by an electric discharge in a gas.

Generally plasma panels include two insulating tiles limiting a volume occupied by a gas (generally a mixture based on neon). These slabs support crossed conductive electrodes so as to define a matrix of elementary points of images or pixels. An electric discharge in the gas, causing an emission of light at the level of an image point or pixel, takes place when the electrodes of this pixel are suitably excited.

Although certain plasma panels operate continuously, it is most often preferred to use panels of the alternative type, the operation of which is based on an excitation in alternating mode of the electrodes. The electrodes are covered with a layer of dielectric material. They are therefore no longer in direct contact with the gas, nor with the discharge.

The operation of a plasma panel, of the alternative type with two crossed electrodes to define a pixel, is Known in particular by a French patent No. 78 04893 in the name of THOMSON-CSF, published under No. 2,417,848. This patent further describes a method of erasing the pixels of such a panel as well as various types of signals which are applied to the cells (gas space between two crossed electrodes, that is to say at the pixel level) of a plasma panel: in particular, recording, maintenance and erasing signals:
- The registration signal consists of a voltage pulse, of amplitude at least equal to the ignition voltage, of the cell gas. The cell emits a short pulse of light, because the electric charges created by ionization of the gas cannot reach the electrodes which are isolated by dielectric layers. These charges are deposited on the dielectric layers and create an internal electric field which opposes the electric field induced by the registration signal and which increases until the cell or pixel goes out. The cell keeps in memory the internal field previously acquired, and it is then called in state 1 or registered state, while a pixel having an internal field almost zero is said in state 0 or erased state. Thus, the registration signal enables cells or pixels in state 0 to be set to state 1.
- The maintenance signal stores the information of a cell in the "registered" state. This maintenance signal consists of an alternating voltage which re-ignites, twice per period, a cell already in the registered state. The internal field kept in memory by a cell or pixel in the registered state makes it possible to relight this pixel by a maintenance signal of amplitude lower than the ignition voltage; each time the cell or pixel gas is ionized, caused by a maintenance discharge, the internal field is canceled and an internal field of sign contrary to the previous one comes to charge the cell or pixel.
- The erase signal allows the setting to state 0 or erased state, of one or more or all of the cells or pixels of the panel. The erasure signal does not modify the state of the cells already in state 0. The erasure of a cell consists in causing an erasure initiation, that is to say an ionization of the gas. this cell with, for example, an intensity just sufficient to cancel the charges accumulated on the dielectric layers with regard to the electrodes. Thus, for example, it is known to erase a cell in state 1 by using a voltage pulse, calibrated in time and in amplitude, which ionizes the gas of the cell and cancels its internal field, without generating a new one, at the contrary to what is obtained with a maintenance signal. One can use for this purpose a voltage pulse in the form of rectangular slots, having either a high amplitude and a short duration, or a low amplitude and a long duration.

The aforementioned patent application also explains how to erase one or more cells, using an erasure signal, the rising edge of which is constituted by a ramp.

With a view in particular to improving the luminance of the plasma panels, and also to allow the display of several colors, it is preferred to use plasma panels of the type excited in alternating mode as described above, and which in addition are maintenance coplanar. In this latter type of so-called alternative panels with coplanar maintenance, each pixel of the matrix is constituted by three electrodes, more precisely at the crossing between an addressing electrode called column electrode with two parallel maintenance electrodes forming a pair of electrodes d 'interview. In this type of screen, the maintenance of the discharges is ensured between the two electrodes of the same pair, and the addressing is done by generation of discharge between two crossed electrodes; by addressing is meant discharges generated so selective and / or semi-selective with a view to carrying out a registration or deletion operation.

Thus the maintenance electrodes comprise two families: the electrodes of a first family are called "addressing-maintenance electrodes" and the electrodes of the second family "electrodes only of maintenance". The maintenance addressing electrodes have the function, in cooperation with the maintenance only electrodes (of the second family), of ensuring the maintenance discharges; but they also have to provide an addressing function, and therefore they must be individualized, that is to say that they must, for example, be connected to one or more pulse generating devices by the intermediary of means which make it possible to apply one or more particular pulses, to only one or more address-maintenance electrodes which are selected from the plurality of address-maintenance electrodes.

Of course, the column electrodes are also individualized.

As regards the maintenance only electrodes (second family), these are generally connected to one or more pulse generators in such a way that these maintenance electrodes of the second family are all, at the same times, brought to the same potentials so that it is not necessary to individualize them and that they can possibly be linked together.

Among the advantages provided by structures where a pixel is defined at the intersection of a column electrode with a pair of maintenance electrodes, one can cite a greater luminance, which is due in particular to the fact that the maintenance discharges between the two maintenance electrodes are carried out on a surface which projects beyond the surface of intersection with the column electrode; so that the useful light is not blocked by this column electrode which is generally mounted on the side of the panel through which the plasma panel is viewed. It should be noted that the addressing-maintenance and only maintenance electrodes may each include, at the level of each pixel, a protrusion or protruding surface; in the same pair of maintenance electrodes, the projecting surfaces of one electrode are oriented towards those of the other electrode, the maintenance discharges taking place between these projecting surfaces.

Such a plasma screen is known in particular from the European patent document EP-A-0 135 382 which also describes a method for controlling this screen; it should be noted that in the device described in this European patent, the column electrode crosses the pairs of maintenance electrodes on the side of the projecting surfaces where the maintenance discharges are produced.

Another structure of the type in which each pixel is defined at the intersection of a column electrode with a pair of maintenance electrodes and a suitable control method are described in the article by GW DICK published in PROCEEDINGS OF THE SID , flight. 27/3, 1986, pages 183-187. It should be noted that in the structure described in this document, the maintenance electrodes have a constant width, that is to say that they do not have a projecting surface facing one another in a pair of maintenance electrode, to define the maintenance discharge zone, this structure on the other hand comprises barriers made of insulating material, which serve to confine maintenance discharges in the zone of intersection with the column electrode.

Another type of plasma panel, to which the method of the invention applies in a particularly advantageous manner, is represented in FIG. 1. Such a panel is the subject in itself of a French patent application No. 88 03953 filed March 25, 1988 on behalf of THOMSON-CSF. As this French patent application has not been published to date, the new type of plasma panel to which it relates is described below.

The panel shown in FIG. 1 comprises a first glass slab 10 covered with a first family of electrodes denoted Xj, where j is an integer ranging from 1 to N (a single electrode Xj is shown; the slab assembly 10- electrode Xj is covered with a layer 12 of dielectric material, possibly covered with an oxide layer such as MgO (not shown) facilitating electronic emission. On the dielectric layer 12 is a wafer 14 of a phosphor material , that is to say capable of emitting colored radiation, under the effect of ultraviolet radiation.

The panel also includes a second glass slab 20 covered with a second family of electrodes made up of pairs of electrodes called respectively, of maintenance-addressing (Yae) i and of maintenance (Ye), where i is an integer between 1 and P. The maintenance-addressing and maintenance electrodes include protrusions or protruding surfaces 22 and 24, arranged opposite one another. The 20-electrode slab assembly is covered with a dielectric layer 26.

In normal operation, the two slabs 10 and 20 and their networks of electrodes are brought closer together and kept apart by a thickness spacer (not shown), and a gas is present in the volume comprised between the slabs and the spacer. Once mounted, the panel thus has two arrays of orthogonal electrodes, in the sense that the electrodes Xj are orthogonal to the electrodes (Yae) i and (Ye). The electrodes Xj can overlap the protrusions 22 and 24 or be slightly offset on the side thereof. A pixel Pij is then defined by an electrode Xj (column electrode and a pair of maintenance electrodes (Yae) i and (Ye).

If the plasma panel described above is controlled where the other plasma panels mentioned above, by a known control method, the operation of these plasma panels may include one or more of the defects mentioned below:
- The pulses applied to the different electrodes can have many voltage levels, which results in a complication of the pulse generators and the number of selective addressing means;
- long duration of the total cycle, from which there may result an incompatibility in operation in fast systems, of the video type for example (by analogy to the images produced by cathode ray tubes where an image is defined line by line) and d where low luminance may result due to the low frequency of maintenance discharges;
- the recording and / or the erasing of the pixels requires several discharges with the column electrode, from where it can result a strongly accelerated degradation of the phosphors (used in the most recent technologies to modify the coloration of the emitted light) .

The control method according to the invention makes it possible to eliminate or considerably reduce the drawbacks mentioned above. The proposed control method is of the video compatible type, that is to say which allows addressing by complete line so as to reduce the scanning time; on the other hand, it allows a reduced cycle time which results in a high maintenance frequency and a high luminance. The proposed control method also makes it possible to reduce the number of voltage levels applied to the different electrodes and thus to simplify the control electronics; it should be noted that the method of the invention also makes it possible to apply to the column electrode only relatively low power and amplitude pulses which allows the use of integrated circuits of low cost technology .

According to the invention, a method of controlling, line by line, a plasma panel of the alternative type with coplanar maintenance, said panel comprising crossed column electrodes with two families of parallel electrodes, the first family of electrodes being constituted by addressing-maintenance electrodes and the second family consisting of maintenance-only electrodes, each addressing-maintenance electrode forming with a maintenance-only electrode adjoins a pair of maintenance electrodes, each pair of electrodes corresponding to a line of pixels perpendicular to the column electrodes, the pixels being formed substantially at each crossing of a column electrode with a pair of electrodes, said method consisting in applying between the two electrodes of each pair of electrodes a cyclic voltage set of period T during which there is a phase of registration of pixels and a pixel erasing phase and during which maintenance discharges are generated, said cyclic voltage set being constituted by a first set of cyclic pulses applied to all the address-maintenance electrodes and by a second set cyclic pulses applied to all electrodes for maintenance only, said method being characterized in that for the erasing of the pixels it consists in simultaneously erasing all the pixels of at least one given line of pixels by causing erasure discharges between the two electrodes of the corresponding pair of electrodes.

• - la figure 1 déjà décrite montre un nouveau type de panneau à plasma auquel l'invention peut s'appliquer ;
• - la figure 2 montre de manière schématique un panneau à plasma auquel le procédé de l'invention peut s'appliquer ;
• - les figures 3a à 3h montrent des signaux qui expliquent le fonctionnement du panneau à plasma montré à la figure 2 et commandé par le procédé conforme à l'invention ;

The invention will be better understood with the aid of the description which follows, given by way of nonlimiting example, with reference to the appended drawings in which:

• - Figure 1 already described shows a new type of plasma panel to which the invention can be applied;
• - Figure 2 shows schematically a plasma panel to which the method of the invention can be applied;
• - Figures 3a to 3h show signals which explain the operation of the plasma panel shown in Figure 2 and controlled by the method according to the invention;

FIG. 2 is a general block diagram of a plasma panel 1 to which the control method of the invention can be applied. For clarity of the figure the plasma panel 1 is mainly represented by conductors or electrodes arranged in column X1, X2, X3, X4, and by two families of maintenance conductors or electrodes arranged in line, on the one hand Y1, Y2, Y3, Y4 for the first family, and on the other hand , E1, E2, E3, E4 for the second family.

The maintenance electrodes Y1 to Y4 and E1 to E4 are arranged in pairs, that is to say that a first electrode Y1 of the first family is associated with an adjacent electrode E1 belonging to the second family, to constitute a pair P1 of maintenance electrodes; a second electrode Y2 of the first family is associated with a second electrode E2 of the second family to constitute a second pair P2 of maintenance electrodes; and likewise for the electrodes Y3 and E3 then Y4 and E4 which respectively constitute a third and a fourth pair P3, P4 of maintenance electrodes. At each crossing of a column electrode X1 to X4 with a pair of electrodes P1 to P4, an elementary image point or pixel PX1 to PX16 is formed which is symbolized in FIG. 2 by a circle in dotted lines; each pixel which can be formed for example according to the structure represented in FIG. 1 and the two electrodes of each pair of electrodes P1 to P4 may or may not have protuberances or projecting parts (not shown in FIG. 2) shown in FIG. 1 with the marks 22, 24.

In the nonlimiting example described, and for clarity of the figure, only 4 electrodes of each type have been represented so that only 16 pixels PX1 to PX16 are formed, but of course the matrix arrangement of pixels can be much more important, constituted for example by the crossings of 1024 column electrodes with 1024 pairs of maintenance electrodes, each pair comprising an electrode of the first family Y with an electrode of the second family E.

The electrodes Y1 to Y4 of the first family are address-maintenance type electrodes, so these address-maintenance electrodes Y1 to Y4 are individualized, that is to say that they are each connected to a different output SY1 to SY4 of a first addressing device G1; the first addressing device G1 is of a conventional type in itself capable of supplying voltage pulses which will be further explained with reference to FIG. 3a. The electrodes E1 to E4 of the second family E are of the maintenance only type: in the non-limiting example described, they are connected together and connected to the output SE of a pulse generator device G2 which delivers voltage pulses which will be explained more clearly with reference to FIG. 3b.

Column electrodes X1 to X4 conventionally perform only an addressing role. They are each connected to a different output SX1 to SX4 of a second addressing device G3; the second addressing device G3 delivers voltage pulses which will also be explained in a continuation of the description relating to Figures 3d to 3g.

The devices G1, G2, G3 are themselves controlled and synchronized, in a conventional manner, by a central control unit (not shown) which manages in a known manner itself the switching on or off or the maintenance pixels PX1 to PX16 on or off.

The control method according to the invention makes it possible to carry out a control line by line: a line L1 to L4 is a line of pixels formed by the pixels PX1 to PX16 defined by each pair P1 to P4 of maintenance electrodes: thus the first line L1 contains the 4 pixels PX1 to PX4, and corresponds to the pair P1 of maintenance electrodes; the second line L2 contains 4 pixels PX5 to PX8 and corresponds to the second pair P2 of electrodes; the third line L3 contains the pixels PX9 to PX12 and corresponds to the third pair P3 of electrodes; the fourth line L4 contains the pixels PX13 to PX16 and corresponds to the fourth pair P4.

FIGS. 3a to 3h show diagrams of signals explaining the operation of the plasma panel 1 controlled according to the method of the invention.

To illustrate the operation which is obtained, we show by way of nonlimiting example the signals which are applied when we want to successively turn off one pixel and turn on another: thus for example, on the second line L2, turn off (this is i.e. erase) the sixth PX6 pixel, and turn on (i.e.) write the seventh PX7 pixel. Note that the sixth pixel PX6 is located at the intersection between the second pair of PE2 electrodes and the second column electrode X2; and that the seventh pixel PX7 is located at the intersection between the second pair of electrodes PE2 and the third column electrode X3.

FIGS. 3a and 3b respectively show a first and a second set of cyclic voltages VY, VE which are applied respectively simultaneously to all the addressing-maintenance electrodes Y1 to Y4 and simultaneously to all the maintenance-only electrodes E1 to E4. FIG. 3c illustrates maintenance discharges produced between the electrodes Y2 and E2 of the second pair P2 of electrodes. Figures 3d, 3e, 3f, 3g, respectively show voltage pulses forming masking pulses applied to the column electrodes X1 to X4.

FIG. 3 h illustrates a DI registration discharge between the third column electrode X3 and the second electrode Y2.

The first and second sets of voltages VY, VE, vary on either side of the same reference voltage VR which is at zero volts for example.

The first and second sets of voltage VY, VE, are constituted respectively by a first and a second set of voltage pulses having a cyclic character and a same period T. During this period T, the combination of the applied voltage pulses of on the one hand to the address-maintenance electrodes Y1 to Y4, and, on the other hand, to the electrodes only maintenance E1 to E4, develops between the 2 electrodes of each pair P1 to P4 voltages (not shown) which determine an erasing phase T1 and a writing phase T2. In the nonlimiting example described, the cycles T also include a maintenance phase T3 which is optional, as is explained further in the description below.

In the maintenance phase T3, the voltages VY and VE have opposite polarities. Thus, for example, in FIG. 3b at time t0, a maintenance window CEe begins which is applied to the maintenance only electrodes E1 to E4, and the transition of which represents a voltage variation Δ VE which in example s 'performs substantially symmetrically with respect to the reference voltage VR; this first maintenance interval CEe applied to the maintenance only electrodes E1 to E4 passing for example to a negative polarity, from a voltage + VE1 to a voltage -VE1.

At the same time, at time t0, begins a CEY maintenance slot applied to the addressing-maintenance electrodes Y1 to Y4, this CEY maintenance slot having a positive polarity, that is to say opposite to that which at the same time is applied to the electrodes only of maintenance E1 to E4, the transition having been carried out at time t0 from a negative voltage -VY1 to a positive voltage + VY1; in the nonlimiting example described, this transition represents a voltage variation Δ VY1 which is carried out in a manner substantially symmetrical with respect to the reference voltage VR.

Assuming that before time t0, the sixth pixel PX6 was in the written state: charges (not shown) were stored on the dielectric of the second electrodes Y2, E2 of the second pair P2, at the level of the sixth pixel PX6, and the transitions at time t0 of the CEY and CEe maintenance slots develop at the level of the sixth pixel PX6 an electric field whose effect is added to that of the charges already stored to cause a maintenance discharge De1 (Figure 3c); this maintenance discharge lasts substantially up to an instant t1 where charges of polarities contrary to the preceding ones are generated in a manner known per se.

The maintenance slots CEY and CEe applied respectively to all the addressing-maintenance electrodes Y1 to Y4 and all the maintenance electrodes E1 to E4 are maintained until an instant t2. At this instant t2, the polarities of the voltages VY and VE are reversed and remain opposite until an instant t4 which marks the start of the erasure phase T1. It is noted that at time t2 the transition of the maintenance slots CEY and CEe causes a new maintenance discharge De2 at the level of the sixth pixel PX6; as for the previous maintenance discharge, this discharge ends at an instant t3 where charges accumulated on the maintenance electrodes YE, E2, with a polarity opposite to that which they had at the instant t2, are in quantity sufficient to cause extinction.

At the instant t4 when the erasing phase T1 begins, the polarities of the voltages VE and VY applied respectively to the maintenance electrodes E1 to E4 and to the address-maintenance electrodes Y1 to Y4 reverse again and remain opposite . Note that the slots applied to the electrodes only for maintenance E1 to E4 always have the same amplitude Δ VE, that is to say that only 2 voltage levels (+ VE1 and -VE1) are necessary to control these electrodes d interview E1 to E4.

At time t4, the voltage VE is formed by a voltage slot of positive polarity which is applied to the maintenance only electrodes E1 to E4, while at the same time, a slot CBe of opposite polarity, that is to say ie negative, is applied to the addressing-maintenance electrodes Y1 to Y4; but this slot Cbe reaches a value VY2 lower than the value VY1, and it retains this value VY2 until an instant t7 when the polarity of the voltage VY reverses again.

Under these conditions, at time t4, the transition of the slot CBe applied to the addressing-maintenance electrodes Y1 to Y4 has a value Δ VY2 lower than the value ΔVY1 of a maintenance slot CEY, so that the potential developed between the maintenance electrodes Y1 to Y4 and E1 to E4 is insufficient to cause a maintenance discharge, even when it is added to the effect of charges already stored on these maintenance electrodes. The slots applied to the addressing-maintenance electrodes Y1 to Y4 at time t4, are intended to form a voltage base or step called the erasing base slot CBe which is superimposed, only on the slot applied to the electrode addressing-maintenance of the pair P1 to P4 addressed (namely in this case only the slot applied to the second addressing-maintenance electrode Y2), a voltage pulse called erase pulse IE, IE ′.

The erasure pulse may have the form of a rectangular slot having either a high amplitude and a short duration, or a low amplitude and a long duration, or even be formed of a pulse whose rising edge is established relatively slowly and constitutes a ramp, as explained in the patent application No. 78 04893 previously cited, filed in the name of THOMSON-CSF and published under No. 2,417,848, and which should be considered as part of this description.

In the nonlimiting example described, the erasing pulse IE (shown in dashed lines) which is superimposed on the erasing base slot CBe, is a pulse whose rising edge R is established relatively slowly as described in the aforementioned patent, until substantially reaching the first value VY1; but the erasure pulse could also be constituted by an IE ′ pulse (shown in dashed lines) of relatively short duration, and which would be superimposed on the erasure base slot CBE starting for example from time t4. Of course, the niche erasing IE, IE ′ is only superimposed on a basic erasing slot CBe for the pair of electrodes P1 to P4 addressed; taking into account the example described, it is only to the second addressing electrode Y2 that an erasing base slot CBe is applied to which an erasing pulse IE, IE ′ is superimposed. Assuming that the erase pulse is the one whose rising edge constitutes a ramp R, the superposition of this erase pulse IE with the basic slot CBe will cause substantially at time t5 when the ramp R reaches substantially the first value VY1, an erasure discharge DEF between the second addressing-maintenance electrode Y2 and the second solely maintenance electrode E2, at the level of each pixel. This erasure discharge is of lower intensity than the maintenance discharges DE1, DE2, and substantially ceases at an instant t6 without causing the accumulation of charges as in the case of the maintenance discharges DE1, DE2. In this configuration, all the pixels PX5 to PX8 of the second pair P2 are erased.

Thus, it is noted that an important characteristic of the process of the invention consists in generating an erasure discharge only between the two maintenance electrodes Y2, E2 of the same given pair P2, this erasure discharge DEF having the effect to erase all the pixels which correspond to this pair P2 of electrodes.

It should be noted that for plxel lines L1, L3, L4 or pairs P1, P3 and P4 of electrodes of which the addressing-maintenance electrode Y1, Y3, Y4 does not receive an erase pulse IE, IE ′, the presence of the basic erasing slot CBe has no effect: all the pixels which are erased remain erased, and all the pixels which are inscribed remain inscribed, that is to say that the charges which existed on the two electrodes of a pair of maintenance electrodes, at time t3 for example, subsist until time t8 which marks the start of the T2 registration phase and at which can maintenance discharges occur at the pixels recorded.

According to another characteristic of the invention, after the erasure of all the pixels of a pair P1 to P4 of given maintenance electrodes, the second pair P2 in the example, the desired pixels belonging to the registration are carried out to this pair P2 of electrodes, by causing a writing discharge between the second addressing-maintenance electrode Y2 and each of the column electrodes X1 to X4 whose intersection with the second addressing-maintenance electrode Y2 represents a pixel that we want to register. Thus in the case which has been provided, namely the writing of the seventh pixel PX7, a writing discharge is carried out only between the second addressing-maintenance electrode Y2 and the third column electrode X3. This is done during the registration phase T2 which begins at time t8.

It is noted that at the instant t7, which corresponds to the end of the basic erasing slot CBe, the polarities of the voltages VY, VE applied respectively to the address-maintenance electrodes Y1 to Y4 AND E1 to E4 are reversed : the polarity of the voltage VE becomes positive and remains so until time t8, and the polarity of the voltage VY becomes negative and remains so until time t8. The time interval Δ t1 between instant t7 and instant t8 optionally makes it possible to stabilize the erasure that has been carried out. This stabilization depends on characteristics specific to the plasma panel used, so that the time interval Δ t1 can possibly be reduced or even eliminated, which makes it possible to reduce the duration of the period T (which represents the basic cycle). This basic cycle can have an even shorter duration, as represented for example by the duration T ′, by eliminating the slots which belong to the maintenance phase T3; this is made possible by the fact that even by eliminating the maintenance phase T3, it is possible with the method of control in accordance with the invention obtain maintenance discharges by the T2 registration phase.

At time t8: the voltage Ve becomes negative; the voltage VY becomes positive by a voltage pulse CBi applied to the addressing-maintenance electrodes Y1 to Y4; the voltage VY then passes to the value VY1, that is to say a variation Δ VY1 by which it is possible to obtain maintenance discharges for all the pixels entered. So for example if we had not erased the sixth pixel P6 (at the same time as the other pixels of the second line L2), we would have kept charges on the electrodes Y2 and E2 which would have allowed to produce a discharge of 'interview De3 (shown in dotted lines) at time t8.

To register the pixel or pixels of a given line or pair of electrodes, a registration window CI is superimposed on the voltage window CBi which, between time t8 and time t12, is applied to all the electrodes d addressing-interview. Of course, a registration slot CI is only superimposed on the basic registration slot CBi which is applied to the desired address, that is to say to the address-maintenance electrode of the pair of electrodes in question, namely in the example the second addressing-maintenance electrode Y2 of the second pair 2. The voltage slot CBi thus constitutes a basic recording slot forming a voltage step at which s adds the voltage of the CI registration window; but it also constitutes a maintenance window for the pairs P1, P3, P4 of the other addressing-maintenance electrodes Y1, Y3, Y4, not addressed.

The registration window CI superimposed on the basic registration window CBI reaches a voltage value VY3 such that the potential difference which is then generated between the column electrodes X1 to X4 and the second addressing-maintenance electrode Y2 can cause a discharge, called registration discharge, at the intersection between the latter and the column electrodes X1 to X4. Also, we only enter the or the desired pixels by applying to the column electrodes X1 to X4 which correspond to the pixels which must not be written, a voltage pulse called the masking pulse MX1 to MX4, of the same polarity as the writing slot CI; so that the potential necessary to produce a discharge between a column electrode X1 to X4 and the electrode Y2, is reached only with the column electrode to which a so-called masking pulse is not applied. Of course, if a masking pulse is applied to all of the column electrodes X1 to X4, none of the pixels are registered. In the nonlimiting example described, and as illustrated in FIGS. 3d, 3e, 3f, 3g, the column electrodes X1 to X4 are brought to the potential of the reference voltage VR, except during the writing phase T2 where a pulse of masking can be applied to them, which brings their voltage to a VX value.

In the example described, where it is the seventh pixel PX7 that one seeks to register, a masking pulse MX1, MX2, MX4 is applied to the first, the second and the fourth column electrode X1, X2, X4 , for at least and a masking pulse is not applied to the third column electrode X3. This results substantially at a time t10 in a registration discharge DI (illustrated in FIG. 3h) between the second addressing-maintenance electrode Y2 and the third column electrode X3, at the crossing of the latter, that is to say at the level of the seventh pixel PX7. The end of the registration slot CI occurs substantially at the same time as the end of the registration base slot CBi, at a time t11 which for example slightly precedes the time t12 at the end of the registration base slot CBi.

It should be noted that to avoid an undesirable discharge between the second addressing-maintenance electrode Y2 and the second maintenance electrode E2, the potential difference between these two electrodes is reduced by reversing the polarity of the voltage VE applied to the electrodes E1 to E4 before the CI registration window is superimposed on the basic registration window CBi: from time t8, the voltage VE goes from positive to negative and constitutes a window CNE of negative polarity; then the polarity of the voltage VE (applied to the maintenance only electrodes E1 to E4) is again inverted at an instant t9 and comprises a positive polarity, this substantially at the same time or a little before the registration window begins. Ci, or in any case before an instant t10 when the CI registration window reaches the value V3Y; the voltage VE then has the same polarity as the voltage VY applied to the address-maintenance electrodes and, between the second maintenance electrode E2 and the second address-maintenance electrode Y2, then there is an insufficient potential difference to cause a parasitic discharge during the superimposition of the CI registration window.

It should be noted that an advantage brought by this arrangement resides in the fact that, the masking pulses MX1 to MX4 are produced with a relatively low power (because it is with the maintenance discharges that one seeks to produce the light emitted by the pixels, and with a relatively low voltage amplitude), so that standard and low-cost components can be used for controlling the column electrodes X1 to X4. It is further noted that another important advantage provided by the method according to the invention, resides in that the discharge which is created occurs only for the points to be entered and not for all the points of the line, which tends to significantly increase the longevity of the phosphors which are used for the emission of color light.

The following are given by way of non-limiting example only, voltage values which can be applied for implementing the method of the invention, with a plasma panel of conventional type:
- the variations Δ VE of the voltage VE can be of the order of 100 volts;
- for the voltage VY, the variations Δ VY1 can be of the order of 150 volts, the variations Δ VY2 can be of the order of 80 volts;
- the masking pulses applied to the column X electrodes can have an amplitude of the order of 40 volts;
- the registration slots Ci can have an amplitude of the order of 80 volts. Of course these values are given only by way of example and can be easily modified as a function of the characteristics of the plasma panel used.

At time t12, the end of the basic registration window CBi corresponds to the end of the registration phase T2, and corresponds to an inversion of the polarity of the voltage VY applied to the addressing-maintenance electrodes Y1 to Y4, polarity which becomes negative. The voltage VE applied to the maintenance electrodes E1 to E4 has been positive since substantially the instant t9 and, in the nonlimiting example described, it retains this positive polarity until an instant t0 ′ which marks the start of a new cycle. It should be noted that the DI registration discharge caused the accumulation of negative charges (not shown) on the dielectric of the second addressing-maintenance electrode Y2 at the level of the seventh pixel PX7: also at the transition from positive to negative of the voltage VY, due to the end of the registration window CI and the basic registration window CBi, the effect of the presence of negative charges accumulated on the electrode Y2 is added so that, substantially when the voltage VY reaches the value -V1, there is a maintenance resumption discharge DRE (FIG. 3c) at the seventh pixel PX7, between the second addressing-maintenance electrode Y2 and the second maintenance electrode E2. As a result of this recovery in maintenance discharge, charges can be accumulated again at the same time on the two electrodes of the second pair P2.

The voltages VY and VE keep their negative and positive polarity respectively until time t0 ′ where begins a new cycle. It should be noted that, depending on the characteristics specific to the plasma panel used, it is possible that a discharge (shown in dotted lines in FIG. 3h) occurs substantially at time t12 between the column electrode X3 and the electrode addressing-interview Y2; in such a case, a maintenance resumption discharge DRE ′ (shown in dotted lines in FIG. 3c) occurs at the instant t0 ′ of the start of a new cycle.

It should be noted that the basic cycle is applied to all the maintenance electrodes with a frequency which depends on the duration of the period T, T ′. Given incompressible times, in particular the times necessary for the control of auxiliary circuits (not shown), the duration of a period T, T ′ can hardly fall below 22 microseconds or 20 microseconds. This nevertheless makes it possible to obtain very interesting performances even with a plasma panel comprising a large number of lines. Taking for example a plasma panel comprising 1000 lines, it takes 20 milliseconds to explore an entire image, that is to say it is possible to obtain 50 images per second.

It is indicated below, solely by way of nonlimiting example of the possible durations of the different signals represented in FIGS. 3:
- the CEY and CEe maintenance slots have a conventional duration of the order of a few microseconds; the basic erasing slot CBe can have a duration of the order of 5 microseconds; the time interval Δ t1 can be of the order of 3 to 4 microseconds. The basic CBi registration slot can have a duration of the order of 7 microseconds; and the registration window Ci which is superimposed on it may have a duration of approximately 4 microseconds, and / or possibly have the same shape as the erasure pulse IE whose rising edge constitutes a ramp R, and whose duration at the top can be of the order of zero to a few microseconds; the niche negative marked CNE on the voltage VE can have a duration of the order of 3 microseconds.

On the voltage VE, it is observed that the negative slot CNE is followed by a positive slot (from time t9), this positive slot being formed, for its part formed between the end of the negative slot CNE and the time t12 at the end of the basic registration window, by a CME masking window which fulfills a function of inhibiting the registration window CI vis-à-vis the second maintenance-only electrode E2, in order to avoid a parasitic discharge between this second electrode E2 and the second addressing-maintenance electrode Y2.

It should be noted that the variations in the voltages VY and VE applied respectively to the addressing-maintenance electrodes Y1 to Y4 and to the so-called maintenance-only electrodes E1 to E4, Δ VE and Δ VY1 for example, are of different amplitudes, unlike to what is generally practiced in the prior art. But of course these voltage variations can be adapted to have similar amplitudes. However, it is advantageous with the control method according to the invention, to have an asymmetry between the values of the voltage slots applied on the one hand to the addressing-maintenance electrodes Y1 to Y4, and on the other hand to the so-called electrodes only maintenance E1 to E4, to more easily generate a registration discharge which generates enough charges to facilitate the resumption in maintenance discharges between the addressing-maintenance electrode Y1 to Y4 concerned and the so-called electrode only maintenance E1 to E4 corresponding, without having to bring charges on this electrode E1 to E4.

Claims (11)

1 - Method for line-by-line control of an alternative type plasma panel with coplanar maintenance, said panel comprising column electrodes (X1 to X4) crossed with two families of maintenance electrodes (Y1 to Y4, E1 to E4 ) parallel, the first family of electrodes (Y1 to Y4) being constituted by address-maintenance electrodes and the second family being constituted by electrodes (E1 to E4) called maintenance only, each address electrode- maintenance (Y1 to Y4) forming with a maintenance-only electrode (E1 to E4) adjoins a pair of maintenance electrodes (P1 to P4), each pair of electrodes (P1 to P4) corresponding to a line of pixels (L1 to L4) perpendicular to the column electrodes (X1 to X4), the pixels (PX1 to PX16) being formed substantially at each crossing of a column electrode (X1 to X4) with a pair of electrodes (P1 to P4), said method consisting in applying a first set of cyclic pulses ues to all addressing-maintenance electrodes (Y1 to Y4) and a second set of cyclic pulses to all so-called maintenance-only electrodes (E1 to E4), the two sets of pulses having the same period (T , T ′), during which said pulses develop between the two electrodes of each pair (PE1 to PE4) of electrodes voltages which constitute an erasing phase (T1) and a writing phase (T2) and which generate maintenance discharges (DE1, DE2, DE3), said method being characterized in that it consists in erasing a complete line (L1 to L4) given of pixels during the erasing phase (T1) by causing discharges of erasure (DEF) only between the addressing-maintenance electrode (Y1 to Y4) and the so-called maintenance-only electrode (E1 to E4) of the corresponding pair (P1 to P4). 2 - control method according to claim 1, consisting in causing the maintenance discharges (DE1, DE2, DE3) by applying to all the addressing-maintenance electrodes (Y1 to Y4) at least one slot (CEY, CBI) having a first polarity and by applying to all the so-called only maintenance electrodes (E1 to E4) at least a second slot having a second polarity, said first and second slots respectively having a first and a second amplitude (ΔVY1, ΔVE), characterized in that during the erasing phase (T1) it consists in applying to all of the electrodes addressing-maintenance (Y1 to Y4) a basic erasure slot (CBe) having a third amplitude (Δ VY2) lower than the first amplitude (Δ VY1), and to be applied at the same time (t4, t6) to all the electrodes called maintenance only (E1 to E4) a niche similar to the second niche and having a polarity opposite to that of said erasing base niche (CBe), and in that an erasure pulse (IE, IE ′) Is superimposed only on the base slot of erasure (CBe) which is applied to the addressing-maintenance electrode (Y1 to Y4) corresponding to said given line (L1 to L4) of pixels. 3 - A control method according to claim 2, characterized in that the erasing pulse (IE) is formed of a pulse whose rising edge constitutes a ramp (R) which is established relatively slowly. 4 - A control method according to claim 2, characterized in that the erase pulse is a relatively short pulse (IE ′). 5 - Control method according to one of the preceding claims, characterized in that for the recording of at least one pixel (PX1 to PX16) of a given line (L1 to L4) whose pixels have been previously erased, it consists in applying to all the addressing-maintenance electrodes (Y1 to Y4) a registration base slot (CBi) having the first polarity and having substantially the first amplitude (Δ VY1), and in superposing a slot inscription (CI) having the same first polarity only at basic registration window (CBI) which is applied to the addressing-maintenance electrode (Y1 to Y4) corresponding to said given line (L1 to L4), and substantially at the same time (t7, t9) to be applied voltage pulses (IMX) having the same first polarity at all the column electrodes (X1 to X4) except those used to define a pixel (PX1 to PX16) to be written, and in that it consists of besides substantially during the time (t7, t9) where the writing window (CI) is superimposed, to apply to all the so-called only maintenance electrodes (E1 to E4) a voltage window having said first polarity and constituting a second masking pulse (CME). 6 - Control method according to one of the preceding claims, characterized in that during said period (T) there is a maintenance phase (T3) during which all the addressing-maintenance electrodes (Y1 to Y4) receive at minus a maintenance window (CEY), and at the same time (t0, t2), a voltage window (CEe) of opposite polarity is applied to all electrodes called maintenance only (E1 to E4). 7 - control method according to one of claims 5 or 6, characterized in that substantially at the instant (t8) when the basic registration slot begins (CBi), a slot (CNE) having said second polarity is applied to all the so-called maintenance only electrodes (E1 to E4) so as to generate maintenance discharges for the non-erased pixels (PX1 to PX16). 8 - control method according to claim 7, characterized in that said slot (CNE) having the second polarity and which begins at the same time as the basic registration slot (CBi) ends before or substantially at the same time ( t9) than the instant (t10) when the erasure pulse begins (IE, IE ′). 9 - Control method according to one of claims 5 or 6 or 7 or 8, characterized in that it consists in applying to all the so-called maintenance only electrodes (E1 to E4) a voltage (VE) having the first polarity at the instant (t12) at which the basic registration window ends (CBi) and where the voltage (VY) applied to all the addressing-maintenance electrodes (Y1 to Y4) reverses to reach the second polarity, so as to generate a recovery discharge (DRE) between the two electrodes (Y2, E2) of the pair (P1 to P4) concerned with electrodes at the level of each of the pixels (PX1 to PX16) which have just been entered. 10 - control method according to one of the preceding claims, characterized in that the pulses (CEe, CNE, CME) applied to the electrodes only maintenance (E1 to E4) have an amplitude (Δ VE) less than the amplitude (Δ VY1, Δ VY2) of the pulses (CEY, CBe, CBi) applied to the addressing-maintenance electrodes (Y1 to Y4). 11 - Control method according to one of the preceding claims, characterized in that the pulses (CNE, CEe) applied to the electrodes only maintenance (E1 to E4) always have the same amplitude.

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