EP0236525A1 - Integrated field-effect transistor delay line for digital signals - Google Patents

Integrated field-effect transistor delay line for digital signals Download PDF

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Publication number
EP0236525A1
EP0236525A1 EP86103301A EP86103301A EP0236525A1 EP 0236525 A1 EP0236525 A1 EP 0236525A1 EP 86103301 A EP86103301 A EP 86103301A EP 86103301 A EP86103301 A EP 86103301A EP 0236525 A1 EP0236525 A1 EP 0236525A1
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Prior art keywords
channel
current
transistor
cmos inverter
constant current
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EP86103301A
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German (de)
French (fr)
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EP0236525B1 (en
Inventor
Paul O'leary
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TDK Micronas GmbH
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Deutsche ITT Industries GmbH
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Priority to EP86103301A priority Critical patent/EP0236525B1/en
Priority to DE8686103301T priority patent/DE3676297D1/en
Priority to US07/023,211 priority patent/US4806804A/en
Priority to JP62054314A priority patent/JPS62219813A/en
Publication of EP0236525A1 publication Critical patent/EP0236525A1/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00323—Delay compensation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's

Definitions

  • the invention relates to an integrated insulating layer field effect transistor delay line for digital signals with inverters connected in series in terms of signal flow.
  • the principle of such a delay line is described in the published patent application EP-A-59 802 (ITT-case W.Gollinger et al 14-13-12-9-3-2).
  • the delay time can be made equidistant step by step by tapping the output of every second inverter via a one-of-n selection switch.
  • the object of the invention is to create a delay line for digital signals, the delay time of which can be set electrically continuously.
  • the inverters are those with a load transistor connected as a resistor, that is to say the two inverter transistors are of the same line type
  • the invention results from the choice of the inverters as CMOS inverters in connection with their connection to the two poles of the operating voltage source the desired continuous, electrical setting option of the delay time via a respective constant current transistor, which is done in that the constant current transistors are dimensioned to carry the same currents, the size of which this currents can be adjusted together via a reference current.
  • the first stage 1 and the last stage n of the delay line are shown.
  • the individual stages are identical to one another and are constructed as follows: to the series circuit which forms the usual CMOS inverter c, the controlled current paths of the N-channel transistor nt and the P-channel transistor pt, the gates of which are connected to one another and the digital signal input eg and whose current path junction is the digital signal output ag, on the side of the N-channel transistor nt is the N-channel constant current transistor nc and on the side of the P-channel transistor pt is the P-channel constant current -Transistor pc connected in series to the respective pole of the operating voltage source u.
  • all N-channel constant current transistors are part of the N-channel multiple current mirror nm and all P-channel constant current transistors are part of the P-channel multiple current mirror pm. All transistors of the two current mirrors are dimensioned such that they are the same in amount and adjustable Reference current i can carry the same currents.
  • the adjustability of the reference current i is symbolized by the adjustable resistor r, which is connected to the operating voltage source u and to the input transistor en of the N current mirror mn.
  • the current i impressed on the input transistor can also be generated in a different manner than by means of a resistor. For example, it can be the control variable in a phase-locked loop.
  • the input transistor ep of the P current mirror pm receives its own reference current i impressed by the additional P channel constant current transistor na of the N current mirror.
  • the invention makes use of the property of the CMOS inverter that, depending on the binary signal level H or L at the input, either the P-channel transistor pt is conductive and the N-channel transistor nt is blocked or the P-channel transistor pt is blocked and the N-channel transistor nt are leading.
  • H / L or L / H signal change the input capacitance of the next stage connected to the output is charged or discharged by the current i after the gate threshold voltage of the transistor which is still blocked and is now conducting is exceeded. As is known, this charging takes place linearly and with a steepness which is directly proportional to the current i. The input signal change is thus switched through depending on the current i per stage to the output of each stage.
  • each stage has the two inputs eg1 (belonging to the CMOS inverter c) and eg2 (belonging to the further CMOS inverter c ⁇ ) and two corresponding outputs. Similar inputs and outputs are connected to each other within the delay line. As a result, both the inverted and the non-inverted input signal are available in one stage, which, in the arrangement according to FIG. 1, can only ever be tapped at one next but one stage.
  • the rising and falling edges of pulses are well matched to one another. Furthermore, the control characteristic of the delay line is independent of manufacturing process parameters.
  • the pair delay time of the two inverters of one stage can be set very low, in particular less than one nanosecond, so that the delay line can also be used at very high signal frequencies. This is especially true if 1.5 micron technology is used for the implementation. If the layout of the delay line is carefully designed, the fluctuation in the delay time of the individual stages can be kept below 1%.
  • the current mirror used in the invention results in a large range of variation in the delay time, e.g. by a factor of 10.
  • the noise behavior is also very good, which is due to the property of the current mirror.
  • the arrangement of the invention is much less noisy than the arrangement described above.

Abstract

Zur kontinuierlichen Einstellung der Verzögerungs­zeit dieser Verzögerungsleitung besteht sie aus gleich­artigen Stufen (1,n) und enthält pro Stufe einen übli­chen CMOS-Inverter (c), dem auf der P-Kanal-Transistor-­Seite ein P-Kanal-Konstantstrom-Transistor (pc) und auf der N-Kanal-Transistor-Seite ein N-Kanal-Konstantstrom-­Transistor (nc) in Serie geschaltet ist. Die N-Kanal-­Konstantstrom-Transistoren sind Bestandteil eines N-Ka­nal-Mehrfach-Stromspiegels (nm) und ebenso die P-Kanal-­Konstantstrom-Transistoren eines P-Kanal-Mehrfach-Strom­spiegels (pm). Sämtliche Transistoren der beiden Strom­spiegel können untereinander gleiche und einem einstell­baren Referenzstrom (i) gleiche Ströme führen.

Figure imgaf001
For the continuous setting of the delay time of this delay line, it consists of stages of the same type (1, n) and contains a conventional CMOS inverter (c) per stage, on the P-channel transistor side of which a P-channel constant current transistor (pc ) and an N-channel constant current transistor (nc) is connected in series on the N-channel transistor side. The N-channel constant current transistors are part of an N-channel multiple current mirror (nm) and also the P-channel constant current transistors of a P-channel multiple current mirror (pm). All transistors of the two current mirrors can carry the same currents and the same as an adjustable reference current (i).
Figure imgaf001

Description

Die Erfinding betrifft eine integrierte Isolier­schicht-Feldeffekttransistor-Verzögerungsleitung für Di­gitalsignale mit signalflußmäßig in Serie geschalteten Invertern. Das Prinzip einer derartigen Verzöogerungslei­tung ist in der veröffentlichten Patentanmeldung EP-A-59 802 (ITT-case W.Gollinger et al 14-13-12-9-3-2) beschrieben. Die Verzögerungszeit ist dadurch äquidi­stant stufenweise einstellbar gemacht, daß der Ausgang jedes zweiten Inverters über einen Eins-aus-n-Auswahl­schalter abgegriffen werden kann.The invention relates to an integrated insulating layer field effect transistor delay line for digital signals with inverters connected in series in terms of signal flow. The principle of such a delay line is described in the published patent application EP-A-59 802 (ITT-case W.Gollinger et al 14-13-12-9-3-2). The delay time can be made equidistant step by step by tapping the output of every second inverter via a one-of-n selection switch.

Demgegenüber liegt der in den Ansprüchen gekennzeichne­ten Erfindung die Aufgabe zugrunde, eine Verzögerungs­leitung für Digitalsignale zu schaffen, deren Verzöge­rungszeit elektrisch kontinuierlich einstellbar ist.In contrast, the object of the invention is to create a delay line for digital signals, the delay time of which can be set electrically continuously.

Während bei der vorbeschriebenen Anordnung die Inverter solche mit einem als Widerstand geschalteten Lasttransi­stor sind, d.h. die beiden Invertertransistoren sind vom selben Leitungstyp, ergibt sich bei der Erfindung durch die Wahl der Inverter als CMOS-Inverter in Verbindung mit deren Anschluß an die beiden Pole der Betriebsspan­nungsquelle über jeweils einen Konstantstromtransistor die gewünschte kontinuierliche, elektrische Einstellmög­lichkeit der Verzögerungszeit, was dadurch geschieht, daß die Konstantstromtransistoren auf das Führen glei­cher Ströme hin dimensioniert sind, wobei die Größe die­ ser Ströme gemeinsam über einen Referenzstrom einstell­bar ist.While in the arrangement described above, the inverters are those with a load transistor connected as a resistor, that is to say the two inverter transistors are of the same line type, the invention results from the choice of the inverters as CMOS inverters in connection with their connection to the two poles of the operating voltage source the desired continuous, electrical setting option of the delay time via a respective constant current transistor, which is done in that the constant current transistors are dimensioned to carry the same currents, the size of which this currents can be adjusted together via a reference current.

Die Erfindung wird nun anhand der Figuren der Zeichnun­gen näher erläutert.

  • Fig.1 zeigt die erste und die letzte Stufe eines Ausfüh­rungsbeispiels der Verzögerungsleitung zusammen mit den erforderlichen Stromspiegeln, und
  • Fig.2 zeigt eine Weiterbildung der Anordnung nach Fig.1.
The invention will now be explained in more detail with reference to the figures in the drawings.
  • 1 shows the first and the last stage of an embodiment of the delay line together with the required current mirrors, and
  • 2 shows a development of the arrangement according to FIG. 1.

Im Ausführungsbeispiel der Fig.1 sind die erste Stufe 1 und die letzte Stufe n der Verzögerungsleitung gezeigt. Dabei sind die einzelnen Stufen untereinander gleich und sind wie folgt aufgebaut: Zu der den üblichen CMOS-In­verter c bildenden Serienschaltung der gesteuerten Strompfade des N-Kanal-Transistors nt und des P-Kanal-­Transistors pt, deren miteinander verbundene Gates den Digitalsignal-Eingang eg und deren Strompfad-Verbin­dungspunkt der Digitalsignal-Ausgang ag ist, ist auf der Seite des N-Kanal-Transistors nt der N-Kanal-Konstant­strom-Transistor nc und auf der Seite des P-Kanal-Tran­sistors pt der P-Kanal-Konstantstrom-Transistor pc zum jeweiligen Pol der Betriebsspannungsquelle u hin in Rei­he geschaltet.In the exemplary embodiment in FIG. 1, the first stage 1 and the last stage n of the delay line are shown. The individual stages are identical to one another and are constructed as follows: to the series circuit which forms the usual CMOS inverter c, the controlled current paths of the N-channel transistor nt and the P-channel transistor pt, the gates of which are connected to one another and the digital signal input eg and whose current path junction is the digital signal output ag, on the side of the N-channel transistor nt is the N-channel constant current transistor nc and on the side of the P-channel transistor pt is the P-channel constant current -Transistor pc connected in series to the respective pole of the operating voltage source u.

Ferner sind sämtliche N-Kanal-Konstantstrom-Transistoren Bestandteil des N-Kanal-Mehrfach-Stromspiegels nm und sämtliche P-Kanal-Konstantstrom-Transistoren Bestandteil des P-Kanal-Mehrfach-Stromspiegels pm. Sämtliche Transi­storen der beiden Stromspiegel sind so dimensioniert, daß sie dem Betrag nach gleiche und zum einstellbaren Referenzstrom i gleiche Ströme führen können. Die Ein­stellbarkeit des Referenzstroms i ist im Ausführungsbei­spiel der Fig.1 durch den einstellbaren Widerstand r symbolisiert, der an der Betriebsspannungsquelle u und am Eingangstransistor en des N-Stromspiegels mn ange­schlossen ist. Der dem Eingangstransistor en eingepräg­ten Strom i kann jedoch auch auf andere Art und Weise als mittels eines Widerstandes erzeugt sein. So kann er beispielsweise die Steuergröße in einer phasenverriegel­ten Schleife sein. Der Eingangstransistor ep des P-­Stromspiegels pm erhält seinen eigenen Referenzstrom i vom zusätzlichen P-Kanal-Konstantstrom- Transistor na des N-Stromspiegels eingeprägt.Furthermore, all N-channel constant current transistors are part of the N-channel multiple current mirror nm and all P-channel constant current transistors are part of the P-channel multiple current mirror pm. All transistors of the two current mirrors are dimensioned such that they are the same in amount and adjustable Reference current i can carry the same currents. In the exemplary embodiment in FIG. 1, the adjustability of the reference current i is symbolized by the adjustable resistor r, which is connected to the operating voltage source u and to the input transistor en of the N current mirror mn. However, the current i impressed on the input transistor can also be generated in a different manner than by means of a resistor. For example, it can be the control variable in a phase-locked loop. The input transistor ep of the P current mirror pm receives its own reference current i impressed by the additional P channel constant current transistor na of the N current mirror.

Die Erfindung nützt die Eigenschaft des CMOS-Inverters aus, daß in Abhängigkeit vom am Eingang liegenden Binär­signalpegel H bzw. L entweder der P-Kanaltransistor pt leitend und der N-Kanaltransistor nt gesperrt bzw. der P-Kanaltransistor pt gesperrt und der N-Kanaltransistor nt leitend sind. Bei einem H/L- bzw. L/H-Signalwechsel wird nach Überschreiten der Gateschwellspannung des noch gesperrten und nunmehr gerade leitend werdenden Transi­stors die Eingangskapazität der am Ausgang angeschlosse­nen nächsten Stufe vom Strom i aufgeladen bzw. entladen. Diese Aufladung geschieht bekanntlich linear und mit ei­ner Steilheit, die dem Strom i direkt proportional ist. Der Eingangssignalwechsel wird somit in Abhängigkeit vom Strom i pro Stufe verzögert an den Ausgang jeder Stufe durchgeschaltet.The invention makes use of the property of the CMOS inverter that, depending on the binary signal level H or L at the input, either the P-channel transistor pt is conductive and the N-channel transistor nt is blocked or the P-channel transistor pt is blocked and the N-channel transistor nt are leading. In the event of an H / L or L / H signal change, the input capacitance of the next stage connected to the output is charged or discharged by the current i after the gate threshold voltage of the transistor which is still blocked and is now conducting is exceeded. As is known, this charging takes place linearly and with a steepness which is directly proportional to the current i. The input signal change is thus switched through depending on the current i per stage to the output of each stage.

Die Fig.2 zeigt eine Weiterbildung der Anordnung nach Fig.1. In jeder Stufe ist dem Strompfad des CMOS-Inver­ters c der Strompfad des weiteren CMOS-Inverters cʹ par­ allelgeschaltet. Dadurch hat jede Stufe die beiden Ein­gänge eg1 (zum CMOS-Inverter c gehörend) und eg2 (zum weiteren CMOS-Inverter cʹ gehörend) sowie zwei entspre­chende Ausgänge. Innerhalb der Verzögerungsleitung sind gleichartige Eingänge und Ausgänge miteinander verbun­den. Dadurch steht in einer Stufe sowohl das invertierte als auch das nichtinvertierte Eingangssignal zur Verfü­gung, das bei der Anordnung nach Fig.1 immer nur an ei­ner übernächsten Stufe abgreifbar ist.2 shows a further development of the arrangement according to FIG. In each stage, the current path of the CMOS inverter c is the current path of the further CMOS inverter cʹ par allele switched. This means that each stage has the two inputs eg1 (belonging to the CMOS inverter c) and eg2 (belonging to the further CMOS inverter cʹ) and two corresponding outputs. Similar inputs and outputs are connected to each other within the delay line. As a result, both the inverted and the non-inverted input signal are available in one stage, which, in the arrangement according to FIG. 1, can only ever be tapped at one next but one stage.

Bei der Verzögerungsleitung nach der Erfindung sind die Anstiegs- und Abfallflanken von Impulsen gut aneinander angepaßt.Ferner ist die Steuercharakteristik der Verzö­gerungsleitung unabhängig von Herstellprozeß-Parametern. Mittels der Weiterbildung nach Fig.2 läßt sich die Paar-­Verzögerungszeit der beiden Inverter einer Stufe sehr niedrig, insbesondere kleiner als eine Nanosekunde ein­stellen, so daß die Verzögerungsleitung auch bei sehr hohen Signalfrequenzen angewendet werden kann. Dies gilt insbesondere, wenn zur Realisierung eine 1,5-Mikrometer-­Technologie verwendet wird. Bei sorgfältiger Auslegung des Layouts der Verzögerungsleitung läßt sich die Schwankung der Verzögerunsgzeit der einzelnen Stufen kleiner als 1% halten.In the delay line according to the invention, the rising and falling edges of pulses are well matched to one another. Furthermore, the control characteristic of the delay line is independent of manufacturing process parameters. By means of the development according to FIG. 2, the pair delay time of the two inverters of one stage can be set very low, in particular less than one nanosecond, so that the delay line can also be used at very high signal frequencies. This is especially true if 1.5 micron technology is used for the implementation. If the layout of the delay line is carefully designed, the fluctuation in the delay time of the individual stages can be kept below 1%.

Durch die bei der Erfindung verwendeten Stromspiegel er­gibt sich ein großer Variationsbereich der Verzögerungs­zeit, z.B. um den Faktor 10. Auch das Rauschverhalten ist sehr gut, was durch die Eigenschaft der Stromspiegel bedingt ist. Die Anordnung der Erfindung rauscht wesent­lich weniger als die eingangs erwähnte, vorbeschriebene Anordnung.The current mirror used in the invention results in a large range of variation in the delay time, e.g. by a factor of 10. The noise behavior is also very good, which is due to the property of the current mirror. The arrangement of the invention is much less noisy than the arrangement described above.

Claims (2)

1. Integrierte Isolierschicht-Feldeffekttransistor-­Verzögerungsleitung für Digitalsignale mit signalflußmä­ßig in Serie geschalteten Invertern,
gekennzeichnet durch folgende Merkmale:
- die Inverter sind übliche, von der Serienschaltung der gesteuerten Strompfade eines N-Kanal-Transistors (nt) und eines P-Kanal-Transistors (pt) gebildete CMOS-Inver­ter (c),
- zu jedem CMOS-Inverter (c) ist auf der Seite des N-Ka­nal-Transistors (nt) ein N-Kanal-Konstantstrom-Transi­stor (nc) und auf der Seite des P-Kanal-Transistors (pt) ein P-Kanal-Konstantstrom-Transistor (pc) zum jeweiligen Pol der Betriebsspannungsquelle (u) hin in Reihe ge­schaltet,
- sämtliche N-Kanal-Konstantstrom-Transistoren sind Be­standteil eines N-Kanal-Mehrfach-Stromspiegels (nm),
- sämtliche P-Kanal-Konstantstrom-Transistoren sind Be­standteil eines P-Kanal-Mehrfach-Stromspiegels (pm), und
- sämtliche Transistoren der beiden Stromspiegel sind so dimensioniert, daß sie dem Betrag nach gleiche und zu einem einstellbaren Referenzstrom (i) gleiche Ströme führen können.1. Integrated insulating layer field-effect transistor delay line for digital signals with inverters connected in series in terms of signal flow,
characterized by the following features:
the inverters are conventional CMOS inverters (c) formed by the series connection of the controlled current paths of an N-channel transistor (nt) and a P-channel transistor (pt),
- For each CMOS inverter (c) on the side of the N-channel transistor (nt) is an N-channel constant current transistor (nc) and on the side of the P-channel transistor (pt) is a P-channel -Constant current transistor (pc) connected in series to the respective pole of the operating voltage source (u),
- All N-channel constant current transistors are part of an N-channel multiple current mirror (nm),
- All P-channel constant current transistors are part of a P-channel multiple current mirror (pm), and
- All the transistors of the two current mirrors are dimensioned such that they can lead to the same currents in terms of amount and to an adjustable reference current (i). 2. CMOS-Verzögerungsleitung nach Anspruch 1, dadurch ge­kennzeichnet, daß in jeder Stufe (1,n) dem Strompfad des CMOS-Inverters (c) der Strompfad eines weiteren CMOS-In­verters (cʹ) parallelgeschaltet ist und daß in jeder Stufe (1,n) der Ausgang des CMOS-Inverters bzw. des wei­teren CMOS-Inverters mit dem Eingang des CMOS-Inverters bzw. des weiteren CMOS-Inverters der in Signalflußrich­tung liegenden nächsten Stufe verbunden ist.2. CMOS delay line according to claim 1, characterized in that in each stage (1, n) the current path of the CMOS inverter (c), the current path of a further CMOS inverter (cʹ) is connected in parallel and that in each stage (1, n) the output of the CMOS inverter or of the further CMOS inverter is connected to the input of the CMOS inverter or of the further CMOS inverter of the next stage lying in the signal flow direction.
EP86103301A 1986-03-12 1986-03-12 Integrated field-effect transistor delay line for digital signals Expired - Lifetime EP0236525B1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP86103301A EP0236525B1 (en) 1986-03-12 1986-03-12 Integrated field-effect transistor delay line for digital signals
DE8686103301T DE3676297D1 (en) 1986-03-12 1986-03-12 INTEGRATED INSULATION LAYER FIELD EFFECT TRANSISTOR DELAY LINE FOR DIGITAL SIGNALS.
US07/023,211 US4806804A (en) 1986-03-12 1987-03-09 Mosfet integrated delay line for digital signals
JP62054314A JPS62219813A (en) 1986-03-12 1987-03-11 Mosfet integrated delay circuit for digital signal

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Application Number Priority Date Filing Date Title
EP86103301A EP0236525B1 (en) 1986-03-12 1986-03-12 Integrated field-effect transistor delay line for digital signals

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EP0236525A1 true EP0236525A1 (en) 1987-09-16
EP0236525B1 EP0236525B1 (en) 1990-12-19

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US5221910A (en) * 1990-10-09 1993-06-22 Sgs-Thomson Microelectronics S.A. Single-pin amplifier in integrated circuit form
EP0566375A1 (en) * 1992-04-15 1993-10-20 Nokia Mobile Phones Ltd. Controlled oscillator
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EP0598260B1 (en) * 1992-11-19 1997-06-25 Codex Corporation High frequency voltage controlled oscillator
US5994755A (en) * 1991-10-30 1999-11-30 Intersil Corporation Analog-to-digital converter and method of fabrication
WO2010052066A1 (en) * 2008-11-10 2010-05-14 Robert Bosch Gmbh Circuit arrangement for amplifying a digital signal, and transceiver circuit for a bus system

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JPH01161913A (en) * 1987-12-18 1989-06-26 Toshiba Corp Clock driver circuit
KR910005794B1 (en) * 1988-06-09 1991-08-03 삼성전자 주식회사 Semiconductor time-delay element
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US4806804A (en) 1989-02-21
EP0236525B1 (en) 1990-12-19
JPS62219813A (en) 1987-09-28
DE3676297D1 (en) 1991-01-31

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