DE8911326U1 - - Google Patents

Info

Publication number
DE8911326U1
DE8911326U1 DE8911326U DE8911326U DE8911326U1 DE 8911326 U1 DE8911326 U1 DE 8911326U1 DE 8911326 U DE8911326 U DE 8911326U DE 8911326 U DE8911326 U DE 8911326U DE 8911326 U1 DE8911326 U1 DE 8911326U1
Authority
DE
Germany
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8911326U
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of DE8911326U1 publication Critical patent/DE8911326U1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
DE8911326U 1989-05-22 1989-09-22 Expired - Lifetime DE8911326U1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/355,266 US5109503A (en) 1989-05-22 1989-05-22 Apparatus with reconfigurable counter includes memory for storing plurality of counter configuration files which respectively define plurality of predetermined counters

Publications (1)

Publication Number Publication Date
DE8911326U1 true DE8911326U1 (de) 1990-06-21

Family

ID=23396843

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8911326U Expired - Lifetime DE8911326U1 (de) 1989-05-22 1989-09-22

Country Status (4)

Country Link
US (1) US5109503A (de)
JP (1) JPH0673083B2 (de)
CA (1) CA1327081C (de)
DE (1) DE8911326U1 (de)

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US5535406A (en) * 1993-12-29 1996-07-09 Kolchinsky; Alexander Virtual processor module including a reconfigurable programmable matrix
US5737631A (en) * 1995-04-05 1998-04-07 Xilinx Inc Reprogrammable instruction set accelerator
US5748979A (en) * 1995-04-05 1998-05-05 Xilinx Inc Reprogrammable instruction set accelerator using a plurality of programmable execution units and an instruction page table
US5574895A (en) * 1995-04-18 1996-11-12 Lee; Chang S. Multi-memory function programmable counter and timer
US5615135A (en) * 1995-06-01 1997-03-25 International Business Machines Corporation Event driven interface having a dynamically reconfigurable counter for monitoring a high speed data network according to changing traffic events
US5943242A (en) 1995-11-17 1999-08-24 Pact Gmbh Dynamically reconfigurable data processing system
US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
DE19647181A1 (de) * 1996-11-14 1998-05-20 Siemens Ag Zur Abarbeitung von Softwareprogrammen ausgelegte integrierte Schaltung
DE19651075A1 (de) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Einheit zur Verarbeitung von numerischen und logischen Operationen, zum Einsatz in Prozessoren (CPU's), Mehrrechnersystemen, Datenflußprozessoren (DFP's), digitalen Signal Prozessoren (DSP's) oder dergleichen
DE19654595A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
DE19654593A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh Umkonfigurierungs-Verfahren für programmierbare Bausteine zur Laufzeit
US6338106B1 (en) 1996-12-20 2002-01-08 Pact Gmbh I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures
DE19654846A1 (de) 1996-12-27 1998-07-09 Pact Inf Tech Gmbh Verfahren zum selbständigen dynamischen Umladen von Datenflußprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o. dgl.)
EP1329816B1 (de) 1996-12-27 2011-06-22 Richter, Thomas Verfahren zum selbständigen dynamischen Umladen von Datenflussprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o.dgl.)
DE19704044A1 (de) * 1997-02-04 1998-08-13 Pact Inf Tech Gmbh Verfahren zur automatischen Adressgenerierung von Bausteinen innerhalb Clustern aus einer Vielzahl dieser Bausteine
DE19704728A1 (de) * 1997-02-08 1998-08-13 Pact Inf Tech Gmbh Verfahren zur Selbstsynchronisation von konfigurierbaren Elementen eines programmierbaren Bausteines
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
DE19704742A1 (de) 1997-02-11 1998-09-24 Pact Inf Tech Gmbh Internes Bussystem für DFPs, sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen, zur Bewältigung großer Datenmengen mit hohem Vernetzungsaufwand
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
DE19861088A1 (de) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
DE19807872A1 (de) 1998-02-25 1999-08-26 Pact Inf Tech Gmbh Verfahren zur Verwaltung von Konfigurationsdaten in Datenflußprozessoren sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstruktur (FPGAs, DPGAs, o. dgl.
KR100513793B1 (ko) * 1998-03-30 2005-12-08 삼성전자주식회사 모니터제조장치
US6145020A (en) * 1998-05-14 2000-11-07 Advanced Technology Materials, Inc. Microcontroller incorporating an enhanced peripheral controller for automatic updating the configuration date of multiple peripherals by using a ferroelectric memory array
EP1228440B1 (de) 1999-06-10 2017-04-05 PACT XPP Technologies AG Sequenz-partitionierung auf zellstrukturen
US6297109B1 (en) * 1999-08-19 2001-10-02 Chartered Semiconductor Manufacturing Ltd. Method to form shallow junction transistors while eliminating shorts due to junction spiking
US6496971B1 (en) * 2000-02-07 2002-12-17 Xilinx, Inc. Supporting multiple FPGA configuration modes using dedicated on-chip processor
ATE476700T1 (de) 2000-06-13 2010-08-15 Richter Thomas Pipeline ct-protokolle und -kommunikation
US7595659B2 (en) 2000-10-09 2009-09-29 Pact Xpp Technologies Ag Logic cell array and bus system
US20040015899A1 (en) * 2000-10-06 2004-01-22 Frank May Method for processing data
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US6990555B2 (en) * 2001-01-09 2006-01-24 Pact Xpp Technologies Ag Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
US7581076B2 (en) 2001-03-05 2009-08-25 Pact Xpp Technologies Ag Methods and devices for treating and/or processing data
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
WO2005045692A2 (en) * 2003-08-28 2005-05-19 Pact Xpp Technologies Ag Data processing device and method
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7210129B2 (en) 2001-08-16 2007-04-24 Pact Xpp Technologies Ag Method for translating programs for reconfigurable architectures
US7076595B1 (en) * 2001-05-18 2006-07-11 Xilinx, Inc. Programmable logic device including programmable interface core and central processing unit
JP2004533691A (ja) 2001-06-20 2004-11-04 ペーアーツェーテー　イクスペーペー　テクノロジーズ　アクチエンゲゼルシャフト データを処理するための方法
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US6970809B2 (en) 2001-08-29 2005-11-29 International Business Machines Corporation Automated configuration of on-circuit facilities
US7434191B2 (en) * 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US7577822B2 (en) 2001-12-14 2009-08-18 Pact Xpp Technologies Ag Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization
WO2003060747A2 (de) 2002-01-19 2003-07-24 Pact Xpp Technologies Ag Reconfigurierbarer prozessor
AU2003214003A1 (en) 2002-02-18 2003-09-09 Pact Xpp Technologies Ag Bus systems and method for reconfiguration
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
AU2003286131A1 (en) 2002-08-07 2004-03-19 Pact Xpp Technologies Ag Method and device for processing data
WO2005010632A2 (en) * 2003-06-17 2005-02-03 Pact Xpp Technologies Ag Data processing device and method
JP4388895B2 (ja) 2002-09-06 2009-12-24 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト リコンフィギュアラブルなシーケンサ構造
WO2007062327A2 (en) * 2005-11-18 2007-05-31 Ideal Industries, Inc. Releasable wire connector
EP1974265A1 (de) 2006-01-18 2008-10-01 PACT XPP Technologies AG Hardwaredefinitionsverfahren
WO2010011813A1 (en) * 2008-07-23 2010-01-28 Alkermes, Inc. Complex of trospium and pharmaceutical compositions thereof
CN102298343B (zh) * 2011-04-29 2013-07-03 浙江工业大学 自动袜机的伺服电机近似匀加速度控制方法
US9037840B2 (en) 2012-06-29 2015-05-19 Intel Corporation Mechanism to provide workload and configuration-aware deterministic performance for microprocessors
US9494996B2 (en) 2013-03-15 2016-11-15 Intel Corporation Processor having frequency of operation information for guaranteed operation under high temperature events
US9311106B1 (en) * 2013-10-03 2016-04-12 Altera Corporation Multiple reconfiguration profiles for dynamically reconfigurable intellectual property cores
US9633158B1 (en) 2014-11-11 2017-04-25 Altera Corporation Selectable reconfiguration for dynamically reconfigurable IP cores
CN106054758A (zh) * 2016-08-19 2016-10-26 上海鲍麦克斯电子科技有限公司 一种实现多输入多输出的控制系统及方法

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US4674089A (en) * 1985-04-16 1987-06-16 Intel Corporation In-circuit emulator
JPS6258722A (ja) * 1985-09-06 1987-03-14 Ricoh Co Ltd プログラマブル・ロジツク・デバイス
US4791603A (en) * 1986-07-18 1988-12-13 Honeywell Inc. Dynamically reconfigurable array logic
JPS63229916A (ja) * 1987-03-18 1988-09-26 Nec Corp メモリ付集積回路装置
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JPH0193837A (ja) * 1987-10-05 1989-04-12 Nec Corp デバッグ用マイクロプロセッサ

Also Published As

Publication number Publication date
CA1327081C (en) 1994-02-15
JPH0673083B2 (ja) 1994-09-14
JPH02310705A (ja) 1990-12-26
US5109503A (en) 1992-04-28

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