DE69817539D1 - Pc-chipanordnungverbindungsbus - Google Patents

Pc-chipanordnungverbindungsbus

Info

Publication number
DE69817539D1
DE69817539D1 DE69817539T DE69817539T DE69817539D1 DE 69817539 D1 DE69817539 D1 DE 69817539D1 DE 69817539 T DE69817539 T DE 69817539T DE 69817539 T DE69817539 T DE 69817539T DE 69817539 D1 DE69817539 D1 DE 69817539D1
Authority
DE
Germany
Prior art keywords
chipanordnungverbindungsbus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69817539T
Other languages
English (en)
Other versions
DE69817539T2 (de
Inventor
E Gulick
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/802,323 external-priority patent/US5926629A/en
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE69817539D1 publication Critical patent/DE69817539D1/de
Publication of DE69817539T2 publication Critical patent/DE69817539T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
DE69817539T 1997-02-18 1998-02-14 Pc-chipanordnungverbindungsbus Expired - Lifetime DE69817539T2 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US955326 1992-10-01
US08/802,323 US5926629A (en) 1997-02-18 1997-02-18 Continuously operating interconnection bus
US08/955,326 US5974492A (en) 1997-02-18 1997-10-20 Method for input/output port replication using an interconnection bus
PCT/US1998/003070 WO1998036363A1 (en) 1997-02-18 1998-02-14 Pc chipset interconnection bus
US802323 2004-03-16

Publications (2)

Publication Number Publication Date
DE69817539D1 true DE69817539D1 (de) 2003-10-02
DE69817539T2 DE69817539T2 (de) 2004-06-09

Family

ID=27122432

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69817539T Expired - Lifetime DE69817539T2 (de) 1997-02-18 1998-02-14 Pc-chipanordnungverbindungsbus

Country Status (4)

Country Link
US (1) US5974492A (de)
EP (1) EP0961978B1 (de)
DE (1) DE69817539T2 (de)
WO (1) WO1998036363A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6357003B1 (en) * 1998-10-21 2002-03-12 Silicon Graphics, Inc. Advanced firmware boot sequence x86 computer system that maintains legacy hardware and software compatibility
AUPP702498A0 (en) * 1998-11-09 1998-12-03 Silverbrook Research Pty Ltd Image creation method and apparatus (ART77)
US6697892B1 (en) 1999-07-08 2004-02-24 Intel Corporation Port expansion system
US7185212B2 (en) * 2003-07-21 2007-02-27 Silicon Integrated Systems Corp. Method for PCI express power management using a PCI PM mechanism in a computer system
US7185213B2 (en) * 2003-07-21 2007-02-27 Silicon Integrated Systems Corp. Method for PCI Express power management using a PCI PM mechanism in a computer system
US9569375B2 (en) * 2014-05-19 2017-02-14 Microchip Technology Incorporated Unifying class device interface with one host interface by using embedded controller

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4156291A (en) * 1977-07-08 1979-05-22 Xerox Corporation Circuitry for eliminating double ram row addressing
FR2455838B1 (fr) * 1979-05-04 1986-02-28 Cit Alcatel Systeme d'echange de messages codes entre stations
US4519034A (en) * 1982-06-30 1985-05-21 Elxsi I/O Bus clock
US4777591A (en) * 1984-01-03 1988-10-11 Texas Instruments Incorporated Microprocessor with integrated CPU, RAM, timer, and bus arbiter for data communications systems
US4683530A (en) * 1984-04-10 1987-07-28 Telemecanique Electrique Serial information transfer protocol
US4726040A (en) * 1984-10-09 1988-02-16 American Telephone And Telegraph Company, At&T Bell Laboratories Burst demodulator
EP0545581B1 (de) * 1991-12-06 1999-04-21 National Semiconductor Corporation Integriertes Datenverarbeitungssystem mit CPU-Kern und unabhängigem parallelen, digitalen Signalprozessormodul
US5390191A (en) * 1992-01-31 1995-02-14 Sony Corporation Apparatus and method for testing the interconnection between integrated circuits
US5392300A (en) * 1992-11-10 1995-02-21 Motorola, Inc. Dual mode radio communication unit
GB2273584B (en) * 1992-12-16 1997-04-16 Quantel Ltd A data storage apparatus
US5410542A (en) * 1993-03-01 1995-04-25 Diaogic Corporation Signal computing bus
US5455740A (en) * 1994-03-07 1995-10-03 Staktek Corporation Bus communication system for stacked high density integrated circuit packages
CA2100700C (en) * 1993-07-16 2000-01-11 Robert P. Bicevskis Multi-media computer architecture
US5553220A (en) * 1993-09-07 1996-09-03 Cirrus Logic, Inc. Managing audio data using a graphics display controller
US5557757A (en) * 1994-02-02 1996-09-17 Advanced Micro Devices High performance integrated processor architecture including a sub-bus control unit for generating signals to control a secondary, non-multiplexed external bus
US5784291A (en) * 1994-12-22 1998-07-21 Texas Instruments, Incorporated CPU, memory controller, bus bridge integrated circuits, layout structures, system and methods
US5734840A (en) * 1995-08-18 1998-03-31 International Business Machines Corporation PCI and expansion bus riser card
US5812800A (en) * 1995-09-11 1998-09-22 Advanced Micro Devices, Inc. Computer system which includes a local expansion bus and a dedicated real-time bus and including a multimedia memory for increased multi-media performance
US5727171A (en) * 1995-11-16 1998-03-10 International Business Machines Corporation Method and apparatus for allowing multi-speed synchronous communications between a processor and both slow and fast computing devices
US5754807A (en) * 1995-11-20 1998-05-19 Advanced Micro Devices, Inc. Computer system including a multimedia bus which utilizes a separate local expansion bus for addressing and control cycles

Also Published As

Publication number Publication date
DE69817539T2 (de) 2004-06-09
US5974492A (en) 1999-10-26
EP0961978A1 (de) 1999-12-08
WO1998036363A1 (en) 1998-08-20
EP0961978B1 (de) 2003-08-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition