DE69705837D1 - Anordnung und verfahren zum speichern und lesen von mehrpegelladung - Google Patents

Anordnung und verfahren zum speichern und lesen von mehrpegelladung

Info

Publication number
DE69705837D1
DE69705837D1 DE69705837T DE69705837T DE69705837D1 DE 69705837 D1 DE69705837 D1 DE 69705837D1 DE 69705837 T DE69705837 T DE 69705837T DE 69705837 T DE69705837 T DE 69705837T DE 69705837 D1 DE69705837 D1 DE 69705837D1
Authority
DE
Germany
Prior art keywords
storing
arrangement
level charge
reading multi
reading
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69705837T
Other languages
English (en)
Other versions
DE69705837T2 (de
Inventor
Donato Montanari
Houdt Jan Van
Guido Groeseneken
Herman Maes
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of DE69705837D1 publication Critical patent/DE69705837D1/de
Application granted granted Critical
Publication of DE69705837T2 publication Critical patent/DE69705837T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G11C11/5635—Erasing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563—Multilevel memory reading aspects
    • G11C2211/5631—Concurrent multilevel reading of more than one cell
DE69705837T 1996-06-14 1997-02-07 Anordnung und verfahren zum speichern und lesen von mehrpegelladung Expired - Lifetime DE69705837T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US1981296P 1996-06-14 1996-06-14
US2003796P 1996-06-21 1996-06-21
PCT/EP1997/000561 WO1997048099A1 (en) 1996-06-14 1997-02-07 A device and method for multi-level charge/storage and reading out

Publications (2)

Publication Number Publication Date
DE69705837D1 true DE69705837D1 (de) 2001-08-30
DE69705837T2 DE69705837T2 (de) 2001-11-08

Family

ID=26692634

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69705837T Expired - Lifetime DE69705837T2 (de) 1996-06-14 1997-02-07 Anordnung und verfahren zum speichern und lesen von mehrpegelladung

Country Status (5)

Country Link
US (1) US6115285A (de)
EP (1) EP0904588B1 (de)
JP (1) JP2001508910A (de)
DE (1) DE69705837T2 (de)
WO (1) WO1997048099A1 (de)

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DE69927967T2 (de) 1999-08-03 2006-07-27 Stmicroelectronics S.R.L., Agrate Brianza Programmierungverfahren eines nichtflüchtigen Multibit Speichers durch Regelung der Gatespannung
KR100387267B1 (ko) 1999-12-22 2003-06-11 주식회사 하이닉스반도체 멀티 레벨 플래쉬 이이피롬 셀 및 그 제조 방법
US7057935B2 (en) * 2001-08-30 2006-06-06 Micron Technology, Inc. Erase verify for non-volatile memory
US6639852B2 (en) * 2002-01-07 2003-10-28 Faraday Technology Corp. Sensing apparatus for a ROM memory device
TWI244165B (en) 2002-10-07 2005-11-21 Infineon Technologies Ag Single bit nonvolatile memory cell and methods for programming and erasing thereof
TW578271B (en) * 2002-12-18 2004-03-01 Ememory Technology Inc Fabrication method for flash memory having single poly and two same channel type transistors
US6956768B2 (en) * 2003-04-15 2005-10-18 Advanced Micro Devices, Inc. Method of programming dual cell memory device to store multiple data states per cell
JP2005222625A (ja) * 2004-02-06 2005-08-18 Sharp Corp 不揮発性半導体記憶装置
US20060134862A1 (en) * 2004-12-17 2006-06-22 Patrice Parris CMOS NVM bitcell and integrated circuit
TWI297983B (en) * 2005-09-16 2008-06-11 Novatek Microelectronics Corp Digital-to-analog conversion device
US7515474B2 (en) * 2005-09-30 2009-04-07 Intel Corporation Step voltage generator
US8645793B2 (en) * 2008-06-03 2014-02-04 Marvell International Ltd. Statistical tracking for flash memory
US8725929B1 (en) 2006-11-06 2014-05-13 Marvell World Trade Ltd. Adaptive read and write systems and methods for memory cells
WO2008007174A1 (en) * 2006-07-10 2008-01-17 Freescale Semiconductor, Inc. Memory circuit with sense amplifier
US7941590B2 (en) * 2006-11-06 2011-05-10 Marvell World Trade Ltd. Adaptive read and write systems and methods for memory cells
US20080168215A1 (en) * 2007-01-05 2008-07-10 Anxiao Jiang Storing Information in a Memory
US7808834B1 (en) 2007-04-13 2010-10-05 Marvell International Ltd. Incremental memory refresh
US8031526B1 (en) 2007-08-23 2011-10-04 Marvell International Ltd. Write pre-compensation for nonvolatile memory
US8189381B1 (en) 2007-08-28 2012-05-29 Marvell International Ltd. System and method for reading flash memory cells
US8085605B2 (en) 2007-08-29 2011-12-27 Marvell World Trade Ltd. Sequence detection for flash memory with inter-cell interference
US8832408B2 (en) * 2007-10-30 2014-09-09 Spansion Llc Non-volatile memory array partitioning architecture and method to utilize single level cells and multi-level cells within the same memory
US8441848B2 (en) 2011-06-08 2013-05-14 Micron Technology, Inc. Set pulse for phase change memory programming
US8787095B2 (en) 2012-02-28 2014-07-22 Micron Technology, Inc. Systems, and devices, and methods for programming a resistive memory cell
KR20140117893A (ko) * 2013-03-27 2014-10-08 인텔렉추얼디스커버리 주식회사 상변화 메모리 소자 및 상변화 메모리 소자의 멀티 레벨 프로그램 방법
CN111199767B (zh) * 2018-11-16 2022-08-16 力旺电子股份有限公司 非易失性存储器良率提升的设计及测试方法
TWI708253B (zh) * 2018-11-16 2020-10-21 力旺電子股份有限公司 非揮發性記憶體良率提升的設計暨測試方法
JP2020149759A (ja) * 2019-03-15 2020-09-17 キオクシア株式会社 半導体記憶装置

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CH631287A5 (fr) * 1979-03-14 1982-07-30 Centre Electron Horloger Element de memoire non-volatile, electriquement reprogrammable.
US4415992A (en) * 1981-02-25 1983-11-15 Motorola, Inc. Memory system having memory cells capable of storing more than two states
US4558344A (en) * 1982-01-29 1985-12-10 Seeq Technology, Inc. Electrically-programmable and electrically-erasable MOS memory device
US4771404A (en) * 1984-09-05 1988-09-13 Nippon Telegraph And Telephone Corporation Memory device employing multilevel storage circuits
US4616245A (en) * 1984-10-29 1986-10-07 Ncr Corporation Direct-write silicon nitride EEPROM cell
US4649520A (en) * 1984-11-07 1987-03-10 Waferscale Integration Inc. Single layer polycrystalline floating gate
US4670675A (en) * 1986-02-07 1987-06-02 Advanced Micro Devices, Inc. High gain sense amplifier for small current differential
US5043940A (en) * 1988-06-08 1991-08-27 Eliyahou Harari Flash EEPROM memory systems having multistate storage cells
US5172338B1 (en) * 1989-04-13 1997-07-08 Sandisk Corp Multi-state eeprom read and write circuits and techniques
US5163021A (en) * 1989-04-13 1992-11-10 Sundisk Corporation Multi-state EEprom read and write circuits and techniques
KR940006094B1 (ko) * 1989-08-17 1994-07-06 삼성전자 주식회사 불휘발성 반도체 기억장치 및 그 제조방법
BE1004424A3 (nl) * 1991-01-31 1992-11-17 Imec Inter Uni Micro Electr Transistorstruktuur voor uitwisbare en programmeerbare geheugens.
US5583810A (en) * 1991-01-31 1996-12-10 Interuniversitair Micro-Elektronica Centrum Vzw Method for programming a semiconductor memory device
US5291439A (en) * 1991-09-12 1994-03-01 International Business Machines Corporation Semiconductor memory cell and memory array with inversion layer
US5298808A (en) * 1992-01-23 1994-03-29 Vitesse Semiconductor Corporation Digital logic protocol interface for different semiconductor technologies
AU4375393A (en) * 1992-05-22 1993-12-30 Indiana University Foundation Area-efficient implication circuits for very dense lukasiewicz logic arrays
US5418743A (en) * 1992-12-07 1995-05-23 Nippon Steel Corporation Method of writing into non-volatile semiconductor memory
US5422845A (en) * 1993-09-30 1995-06-06 Intel Corporation Method and device for improved programming threshold voltage distribution in electrically programmable read only memory array
DE69523304T2 (de) * 1994-06-02 2002-07-11 Intel Corp Dynamischer speicher mit einem bis mehreren bits pro zelle
DE69521705D1 (de) * 1994-06-02 2001-08-16 Intel Corp Abtastverfahren für einen flash-speicher mit mehrstufigen zellen
JP2937805B2 (ja) * 1995-05-19 1999-08-23 モトローラ株式会社 ２層フローティングゲート構造のマルチビット対応セルを有する不揮発性メモリ及びそのプログラム／消去／読出方法

Also Published As

Publication number Publication date
JP2001508910A (ja) 2001-07-03
EP0904588B1 (de) 2001-07-25
WO1997048099A1 (en) 1997-12-18
EP0904588A1 (de) 1999-03-31
US6115285A (en) 2000-09-05
DE69705837T2 (de) 2001-11-08

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Legal Events

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8364 No opposition during term of opposition