DE69634778D1 - Vorrichtung zum parallelen prüfen von halbleiterschaltkreisen - Google Patents

Vorrichtung zum parallelen prüfen von halbleiterschaltkreisen

Info

Publication number
DE69634778D1
DE69634778D1 DE69634778T DE69634778T DE69634778D1 DE 69634778 D1 DE69634778 D1 DE 69634778D1 DE 69634778 T DE69634778 T DE 69634778T DE 69634778 T DE69634778 T DE 69634778T DE 69634778 D1 DE69634778 D1 DE 69634778D1
Authority
DE
Germany
Prior art keywords
test
semiconductor devices
mtx
device under
pattern generator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69634778T
Other languages
English (en)
Other versions
DE69634778T2 (de
Inventor
A Brehm
M Shepard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aehr Test Systems Inc
Original Assignee
Aehr Test Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aehr Test Systems Inc filed Critical Aehr Test Systems Inc
Publication of DE69634778D1 publication Critical patent/DE69634778D1/de
Application granted granted Critical
Publication of DE69634778T2 publication Critical patent/DE69634778T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G01R31/3191—Calibration
DE69634778T 1995-03-17 1996-03-08 Vorrichtung zum parallelen prüfen von halbleiterschaltkreisen Expired - Fee Related DE69634778T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US407103 1995-03-17
US08/407,103 US5682472A (en) 1995-03-17 1995-03-17 Method and system for testing memory programming devices
PCT/US1996/003124 WO1996029649A1 (en) 1995-03-17 1996-03-08 Method and system for testing memory programming devices

Publications (2)

Publication Number Publication Date
DE69634778D1 true DE69634778D1 (de) 2005-06-30
DE69634778T2 DE69634778T2 (de) 2006-02-02

Family

ID=23610604

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69634778T Expired - Fee Related DE69634778T2 (de) 1995-03-17 1996-03-08 Vorrichtung zum parallelen prüfen von halbleiterschaltkreisen

Country Status (8)

Country Link
US (1) US5682472A (de)
EP (1) EP0819275B1 (de)
JP (1) JP3881017B2 (de)
KR (1) KR100395032B1 (de)
AT (1) ATE296463T1 (de)
AU (1) AU5185996A (de)
DE (1) DE69634778T2 (de)
WO (1) WO1996029649A1 (de)

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US6580283B1 (en) 1999-07-14 2003-06-17 Aehr Test Systems Wafer level burn-in and test methods
US6562636B1 (en) 1999-07-14 2003-05-13 Aehr Test Systems Wafer level burn-in and electrical test system and method
US6413113B2 (en) 1999-07-14 2002-07-02 Aehr Test Systems Kinematic coupling
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US7065723B2 (en) * 2002-09-25 2006-06-20 Sun Microsystems, Inc. Defect tracking by utilizing real-time counters in network computing environments
US20040163076A1 (en) * 2003-02-11 2004-08-19 Zayas Fernando A. Self-identifying self-test output system
KR100543449B1 (ko) * 2003-04-11 2006-01-23 삼성전자주식회사 상대 어드레스 방식으로 모든 메모리 셀들의 액세스가가능하게 하는 반도체 메모리 장치
KR100505686B1 (ko) * 2003-05-26 2005-08-03 삼성전자주식회사 다수의 피시험 소자들을 병렬로 검사하는 테스트 시스템및 테스트 방법
US6961674B2 (en) * 2003-08-11 2005-11-01 Hewlett-Packard Development Company, L.P. System and method for analysis of cache array test data
US7376917B1 (en) * 2003-08-25 2008-05-20 Xilinx, Inc. Client-server semiconductor verification system
US20050240834A1 (en) * 2004-03-30 2005-10-27 Aviation Communication & Surveillance Systems Llc Systems and methods for controlling extended functions
DE102007016622A1 (de) * 2007-04-05 2008-10-09 Qimonda Ag Halbleiter-Bauelement-Test-Verfahren und -Test-System mit reduzierter Anzahl an Test-Kanälen
KR100927119B1 (ko) * 2007-05-10 2009-11-18 삼성전자주식회사 불 휘발성 반도체 메모리 장치 및 그것의 프로그램 방법
US9092570B2 (en) * 2007-07-28 2015-07-28 Sam Michael Memory management for remote software debuggers and methods
DE102009010886B4 (de) * 2009-02-27 2013-06-20 Advanced Micro Devices, Inc. Erkennung der Verzögerungszeit in einem eingebauten Speicherselbsttest unter Anwendung eines Ping-Signals
TWI451428B (zh) 2010-06-03 2014-09-01 Sunplus Technology Co Ltd 於完整記憶體系統中具有先進特徵的記憶體測試系統
EP2587489A1 (de) * 2011-10-27 2013-05-01 Maishi Electronic (Shanghai) Ltd. Systeme und Verfahren zum Testen von Speichern
CN103093829A (zh) * 2011-10-27 2013-05-08 迈实电子(上海)有限公司 存储器测试系统及存储器测试方法
CN103107693A (zh) * 2011-11-14 2013-05-15 鸿富锦精密工业（深圳）有限公司 测试电源装置
US9069719B2 (en) * 2012-02-11 2015-06-30 Samsung Electronics Co., Ltd. Method and system for providing a smart memory architecture
CN103809102B (zh) * 2012-11-06 2017-08-22 比亚迪股份有限公司 一种在编程时对芯片进行测试的方法及测试系统
CN103870366A (zh) * 2012-12-13 2014-06-18 鸿富锦精密工业（深圳）有限公司 时间记录装置及方法
KR101522292B1 (ko) * 2013-07-31 2015-05-21 주식회사 유니테스트 메모리 테스트 동시 판정 시스템
CN104679085B (zh) * 2013-11-30 2017-02-15 上海德朗能新能源有限公司 电源调节装置
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Also Published As

Publication number Publication date
US5682472A (en) 1997-10-28
JP3881017B2 (ja) 2007-02-14
DE69634778T2 (de) 2006-02-02
EP0819275A1 (de) 1998-01-21
WO1996029649A1 (en) 1996-09-26
AU5185996A (en) 1996-10-08
EP0819275A4 (de) 1998-10-14
ATE296463T1 (de) 2005-06-15
KR19980703077A (ko) 1998-09-05
EP0819275B1 (de) 2005-05-25
JPH11502353A (ja) 1999-02-23
KR100395032B1 (ko) 2003-10-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee