DE69607887T2 - Hauptspeichersegmentierung, um Datenpfade in einem Rechnersystem leistungsfähiger zu machen - Google Patents

Hauptspeichersegmentierung, um Datenpfade in einem Rechnersystem leistungsfähiger zu machen

Info

Publication number
DE69607887T2
DE69607887T2 DE69607887T DE69607887T DE69607887T2 DE 69607887 T2 DE69607887 T2 DE 69607887T2 DE 69607887 T DE69607887 T DE 69607887T DE 69607887 T DE69607887 T DE 69607887T DE 69607887 T2 DE69607887 T2 DE 69607887T2
Authority
DE
Germany
Prior art keywords
efficient
computer system
main memory
data paths
make data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69607887T
Other languages
English (en)
Other versions
DE69607887D1 (de
Inventor
Ali Ezzet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of DE69607887D1 publication Critical patent/DE69607887D1/de
Application granted granted Critical
Publication of DE69607887T2 publication Critical patent/DE69607887T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/404—Coupling between buses using bus bridges with address mapping
DE69607887T 1995-06-06 1996-06-05 Hauptspeichersegmentierung, um Datenpfade in einem Rechnersystem leistungsfähiger zu machen Expired - Fee Related DE69607887T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/480,429 US5664152A (en) 1995-06-06 1995-06-06 Multiple segmenting of main memory to streamline data paths in a computing system

Publications (2)

Publication Number Publication Date
DE69607887D1 DE69607887D1 (de) 2000-05-31
DE69607887T2 true DE69607887T2 (de) 2000-11-16

Family

ID=23907933

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69607887T Expired - Fee Related DE69607887T2 (de) 1995-06-06 1996-06-05 Hauptspeichersegmentierung, um Datenpfade in einem Rechnersystem leistungsfähiger zu machen

Country Status (4)

Country Link
US (2) US5664152A (de)
EP (1) EP0747830B1 (de)
JP (1) JP3701076B2 (de)
DE (1) DE69607887T2 (de)

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US5664152A (en) * 1995-06-06 1997-09-02 Hewlett-Packard Company Multiple segmenting of main memory to streamline data paths in a computing system
US5812800A (en) * 1995-09-11 1998-09-22 Advanced Micro Devices, Inc. Computer system which includes a local expansion bus and a dedicated real-time bus and including a multimedia memory for increased multi-media performance
US5911149A (en) * 1996-11-01 1999-06-08 Nec Electronics Inc. Apparatus and method for implementing a programmable shared memory with dual bus architecture
US6061754A (en) * 1997-06-25 2000-05-09 Compaq Computer Corporation Data bus having switch for selectively connecting and disconnecting devices to or from the bus
FR2770008B1 (fr) * 1997-10-16 2001-10-12 Alsthom Cge Alkatel Dispositif de communication entre plusieurs processeurs
GB2332344A (en) 1997-12-09 1999-06-16 Sony Uk Ltd Set top box integrated circuit
US6094710A (en) * 1997-12-17 2000-07-25 International Business Machines Corporation Method and system for increasing system memory bandwidth within a symmetric multiprocessor data-processing system
US5860101A (en) * 1997-12-17 1999-01-12 International Business Machines Corporation Scalable symmetric multiprocessor data-processing system with data allocation among private caches and segments of system memory
US5893163A (en) * 1997-12-17 1999-04-06 International Business Machines Corporation Method and system for allocating data among cache memories within a symmetric multiprocessor data-processing system
US6101563A (en) * 1998-05-15 2000-08-08 International Business Machines Corporation Configuration access system
US6170023B1 (en) 1998-10-07 2001-01-02 International Business Machines Corporation System for accessing an input/output device using multiple addresses
US6202095B1 (en) 1998-10-07 2001-03-13 International Business Machines Corporation Defining characteristics between processing systems
US6167459A (en) * 1998-10-07 2000-12-26 International Business Machines Corporation System for reassigning alias addresses to an input/output device
US6185638B1 (en) 1998-10-07 2001-02-06 International Business Machines Corporation Method and system for dynamically assigning addresses to an input/output device
US6226704B1 (en) * 1998-12-01 2001-05-01 Silicon Integrated Systems Corporation Method and apparatus for performing bus transactions orderly and concurrently in a bus bridge
US6141710A (en) * 1998-12-15 2000-10-31 Daimlerchrysler Corporation Interfacing vehicle data bus to intelligent transportation system (ITS) data bus via a gateway module
US6330646B1 (en) * 1999-01-08 2001-12-11 Intel Corporation Arbitration mechanism for a computer system having a unified memory architecture
US6295571B1 (en) * 1999-03-19 2001-09-25 Times N Systems, Inc. Shared memory apparatus and method for multiprocessor systems
US6820161B1 (en) * 2000-09-28 2004-11-16 International Business Machines Corporation Mechanism for allowing PCI-PCI bridges to cache data without any coherency side effects
KR100449806B1 (ko) * 2002-12-23 2004-09-22 한국전자통신연구원 네트워크를 통해 스트리밍 데이터를 고속으로 송수신하기위한 네트워크-스토리지 연결 장치

Family Cites Families (20)

* Cited by examiner, † Cited by third party
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IT1151351B (it) * 1982-01-19 1986-12-17 Italtel Spa Disposizione circuitale atta a realizzare lo scambio di dati tra una coppia di elaboratori operanti secondo il principio master-slave
US4646237A (en) * 1983-12-05 1987-02-24 Ncr Corporation Data handling system for handling data transfers between a cache memory and a main memory
NO173305C (no) * 1985-07-01 1993-11-24 Honeywell Inc Datasystem
US4855902A (en) * 1985-07-01 1989-08-08 Honeywell, Inc. Microprocessor assisted data block transfer apparatus
US4764896A (en) * 1985-07-01 1988-08-16 Honeywell Inc. Microprocessor assisted memory to memory move apparatus
US5287485A (en) * 1988-12-22 1994-02-15 Digital Equipment Corporation Digital processing system including plural memory devices and data transfer circuitry
US5274795A (en) * 1989-08-18 1993-12-28 Schlumberger Technology Corporation Peripheral I/O bus and programmable bus interface for computer data acquisition
JP2910303B2 (ja) * 1990-06-04 1999-06-23 株式会社日立製作所 情報処理装置
US5416907A (en) * 1990-06-15 1995-05-16 Digital Equipment Corporation Method and apparatus for transferring data processing data transfer sizes
JPH05108473A (ja) * 1991-03-20 1993-04-30 Hitachi Ltd デ−タ処理システム
US5269005A (en) * 1991-09-17 1993-12-07 Ncr Corporation Method and apparatus for transferring data within a computer system
US5379384A (en) * 1992-06-05 1995-01-03 Intel Corporation Configuration data loopback in a bus bridge circuit
US5355452A (en) * 1992-07-02 1994-10-11 Hewlett-Packard Company Dual bus local area network interfacing system
US5367701A (en) * 1992-12-21 1994-11-22 Amdahl Corporation Partitionable data processing system maintaining access to all main storage units after being partitioned
JPH07121474A (ja) * 1993-10-21 1995-05-12 Ricoh Co Ltd 情報処理装置
US5680556A (en) * 1993-11-12 1997-10-21 International Business Machines Corporation Computer system and method of operation thereof wherein a BIOS ROM can be selectively locatable on diffeent buses
US5548730A (en) * 1994-09-20 1996-08-20 Intel Corporation Intelligent bus bridge for input/output subsystems in a computer system
US5603051A (en) * 1995-06-06 1997-02-11 Hewlett-Packard Company Input/output processor with a local memory providing shared resources for a plurality of input/output interfaces on an I/O bus
US5664152A (en) * 1995-06-06 1997-09-02 Hewlett-Packard Company Multiple segmenting of main memory to streamline data paths in a computing system
US5673399A (en) * 1995-11-02 1997-09-30 International Business Machines, Corporation System and method for enhancement of system bus to mezzanine bus transactions

Also Published As

Publication number Publication date
JPH096711A (ja) 1997-01-10
EP0747830B1 (de) 2000-04-26
US5664152A (en) 1997-09-02
US5768547A (en) 1998-06-16
EP0747830A1 (de) 1996-12-11
JP3701076B2 (ja) 2005-09-28
DE69607887D1 (de) 2000-05-31

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD CO. (N.D.GES.D.STAATES DELAWARE),

8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE

8339 Ceased/non-payment of the annual fee