DE69605727D1 - Auswahleinheit für externe Geräte in einem Datenprozessor - Google Patents

Auswahleinheit für externe Geräte in einem Datenprozessor

Info

Publication number
DE69605727D1
DE69605727D1 DE69605727T DE69605727T DE69605727D1 DE 69605727 D1 DE69605727 D1 DE 69605727D1 DE 69605727 T DE69605727 T DE 69605727T DE 69605727 T DE69605727 T DE 69605727T DE 69605727 D1 DE69605727 D1 DE 69605727D1
Authority
DE
Germany
Prior art keywords
selection unit
data processor
external devices
external
devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69605727T
Other languages
English (en)
Inventor
William C Moyer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of DE69605727D1 publication Critical patent/DE69605727D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0653—Configuration or reconfiguration with centralised address assignment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
DE69605727T 1995-08-02 1996-07-25 Auswahleinheit für externe Geräte in einem Datenprozessor Expired - Lifetime DE69605727D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/510,510 US5724604A (en) 1995-08-02 1995-08-02 Data processing system for accessing an external device and method therefor

Publications (1)

Publication Number Publication Date
DE69605727D1 true DE69605727D1 (de) 2000-01-27

Family

ID=24031047

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69605727T Expired - Lifetime DE69605727D1 (de) 1995-08-02 1996-07-25 Auswahleinheit für externe Geräte in einem Datenprozessor

Country Status (5)

Country Link
US (1) US5724604A (de)
EP (1) EP0757316B1 (de)
JP (1) JP3576325B2 (de)
KR (1) KR100394166B1 (de)
DE (1) DE69605727D1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19705507C1 (de) * 1997-02-13 1998-06-18 Siemens Ag Steuergerät
US6324592B1 (en) * 1997-02-25 2001-11-27 Keystone Aerospace Apparatus and method for a mobile computer architecture and input/output management system
US6327640B1 (en) * 1997-03-07 2001-12-04 Advanced Micro Devices, Inc. Overlapping peripheral chip select space with DRAM on a microcontroller with an integrated DRAM controller
GB9805488D0 (en) * 1998-03-13 1998-05-13 Sgs Thomson Microelectronics Microcomputer
DE10036637B4 (de) * 2000-07-26 2006-07-27 Robert Bosch Gmbh Vorrichtung zur Ansteuerung von Peripherieelementen mit einem Prozessorbaustein
US7003638B2 (en) * 2002-12-11 2006-02-21 Standard Microsystems Corporation Memory bus interface for use in a peripheral device
US8250295B2 (en) 2004-01-05 2012-08-21 Smart Modular Technologies, Inc. Multi-rank memory module that emulates a memory module having a different number of ranks
US7916574B1 (en) 2004-03-05 2011-03-29 Netlist, Inc. Circuit providing load isolation and memory domain translation for memory module
US7289386B2 (en) 2004-03-05 2007-10-30 Netlist, Inc. Memory module decoder
US8787060B2 (en) 2010-11-03 2014-07-22 Netlist, Inc. Method and apparatus for optimizing driver load in a memory package
US8516185B2 (en) 2009-07-16 2013-08-20 Netlist, Inc. System and method utilizing distributed byte-wise buffers on a memory module
US8154901B1 (en) 2008-04-14 2012-04-10 Netlist, Inc. Circuit providing load isolation and noise reduction
US9128632B2 (en) 2009-07-16 2015-09-08 Netlist, Inc. Memory module with distributed data buffers and method of operation
CN116594922B (zh) * 2023-07-14 2023-10-31 深圳砺驰半导体科技有限公司 一种数据访问电路、方法及系统级芯片

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4747041A (en) * 1983-06-27 1988-05-24 Unisys Corporation Automatic power control system which automatically activates and deactivates power to selected peripheral devices based upon system requirement
US4763244A (en) * 1986-01-15 1988-08-09 Motorola, Inc. Paged memory management unit capable of selectively supporting multiple address spaces
US5151986A (en) * 1987-08-27 1992-09-29 Motorola, Inc. Microcomputer with on-board chip selects and programmable bus stretching
US5243701A (en) * 1987-09-17 1993-09-07 Mitsubishi Denki Kabushiki Kaisha Method of and system for processing data having bit length variable with modes of operation
US5263141A (en) * 1989-01-31 1993-11-16 Brother Kogyo Kabushiki Kaisha Microprocessor with an exclusive address terminal for selecting at least one part of a peripheral device
US5448744A (en) * 1989-11-06 1995-09-05 Motorola, Inc. Integrated circuit microprocessor with programmable chip select logic
JPH0484253A (ja) * 1990-07-26 1992-03-17 Mitsubishi Electric Corp バス幅制御回路
US5483660A (en) * 1993-11-29 1996-01-09 Motorola Inc. Method and apparatus for performing multiplexed and non-multiplexed bus cycles in a data processing system
JP3670041B2 (ja) * 1993-12-10 2005-07-13 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 不揮発性メモリチップイネーブル符号化方法、コンピュータシステム、およびメモリコントローラ
US5617559A (en) * 1994-08-31 1997-04-01 Motorola Inc. Modular chip select control circuit and method for performing pipelined memory accesses
US5619471A (en) * 1995-06-06 1997-04-08 Apple Computer, Inc. Memory controller for both interleaved and non-interleaved memory
US5606715A (en) * 1995-06-26 1997-02-25 Motorola Inc. Flexible reset configuration of a data processing system and method therefor
US5623687A (en) * 1995-06-26 1997-04-22 Motorola Reset configuration in a data processing system and method therefor

Also Published As

Publication number Publication date
JP3576325B2 (ja) 2004-10-13
EP0757316B1 (de) 1999-12-22
KR100394166B1 (ko) 2003-10-17
JPH0944448A (ja) 1997-02-14
KR970012168A (ko) 1997-03-29
US5724604A (en) 1998-03-03
EP0757316A1 (de) 1997-02-05

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Legal Events

Date Code Title Description
8332 No legal effect for de