DE69431848D1 - Konfigurierbares logisches Feld - Google Patents
Konfigurierbares logisches FeldInfo
- Publication number
- DE69431848D1 DE69431848D1 DE69431848T DE69431848T DE69431848D1 DE 69431848 D1 DE69431848 D1 DE 69431848D1 DE 69431848 T DE69431848 T DE 69431848T DE 69431848 T DE69431848 T DE 69431848T DE 69431848 D1 DE69431848 D1 DE 69431848D1
- Authority
- DE
- Germany
- Prior art keywords
- cells
- function
- array
- subsidiary
- core cells
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
- H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
- H03K19/1774—Structural details of routing resources for global signals, e.g. clock, reset
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
- H03K19/17744—Structural details of routing resources for input/output signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/1778—Structural details for adapting physical parameters
- H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB939312674A GB9312674D0 (en) | 1993-06-18 | 1993-06-18 | Configurabel logic array |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69431848D1 true DE69431848D1 (de) | 2003-01-16 |
DE69431848T2 DE69431848T2 (de) | 2003-05-28 |
Family
ID=10737437
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69431848T Expired - Fee Related DE69431848T2 (de) | 1993-06-18 | 1994-06-01 | Konfigurierbares logisches Feld |
DE69426546T Expired - Fee Related DE69426546T2 (de) | 1993-06-18 | 1994-06-01 | Konfigurierbares logisches Feld |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69426546T Expired - Fee Related DE69426546T2 (de) | 1993-06-18 | 1994-06-01 | Konfigurierbares logisches Feld |
Country Status (12)
Country | Link |
---|---|
US (1) | US5903165A (de) |
EP (2) | EP0630115B1 (de) |
JP (1) | JP3547168B2 (de) |
KR (1) | KR100340310B1 (de) |
AT (2) | ATE198685T1 (de) |
AU (1) | AU685100B2 (de) |
CA (1) | CA2125307A1 (de) |
DE (2) | DE69431848T2 (de) |
GB (2) | GB9312674D0 (de) |
RU (1) | RU94021641A (de) |
SG (2) | SG88743A1 (de) |
TW (1) | TW242192B (de) |
Families Citing this family (68)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6051991A (en) * | 1993-08-03 | 2000-04-18 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
US5457410A (en) | 1993-08-03 | 1995-10-10 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
US6462578B2 (en) | 1993-08-03 | 2002-10-08 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
GB9403030D0 (en) * | 1994-02-17 | 1994-04-06 | Austin Kenneth | Re-configurable application specific device |
EP0755588B1 (de) * | 1994-04-14 | 2002-03-06 | Btr, Inc. | Architektur und verbindungsschema für programmierbare logische schaltungen |
KR19990008270A (ko) | 1995-05-03 | 1999-01-25 | 팅 벤자민 에스. | 스케일가능한 복수 레벨 상호연결 아키텍춰 |
US5850564A (en) * | 1995-05-03 | 1998-12-15 | Btr, Inc, | Scalable multiple level tab oriented interconnect architecture |
US5909126A (en) * | 1995-05-17 | 1999-06-01 | Altera Corporation | Programmable logic array integrated circuit devices with interleaved logic array blocks |
US5900743A (en) * | 1995-05-17 | 1999-05-04 | Altera Corporation | Programmable logic array devices with interconnect lines of various lengths |
US5543732A (en) * | 1995-05-17 | 1996-08-06 | Altera Corporation | Programmable logic array devices with interconnect lines of various lengths |
US5631578A (en) * | 1995-06-02 | 1997-05-20 | International Business Machines Corporation | Programmable array interconnect network |
US5671432A (en) * | 1995-06-02 | 1997-09-23 | International Business Machines Corporation | Programmable array I/O-routing resource |
US5652529A (en) * | 1995-06-02 | 1997-07-29 | International Business Machines Corporation | Programmable array clock/reset resource |
GB2305759A (en) * | 1995-09-30 | 1997-04-16 | Pilkington Micro Electronics | Semi-conductor integrated circuit |
US5835998A (en) * | 1996-04-04 | 1998-11-10 | Altera Corporation | Logic cell for programmable logic devices |
US5872463A (en) * | 1996-04-04 | 1999-02-16 | Altera Corporation | Routing in programmable logic devices using shared distributed programmable logic connectors |
US6094066A (en) * | 1996-08-03 | 2000-07-25 | Mission Research Corporation | Tiered routing architecture for field programmable gate arrays |
US6624658B2 (en) | 1999-02-04 | 2003-09-23 | Advantage Logic, Inc. | Method and apparatus for universal program controlled bus architecture |
US6034547A (en) | 1996-09-04 | 2000-03-07 | Advantage Logic, Inc. | Method and apparatus for universal program controlled bus |
US5880597A (en) * | 1996-09-18 | 1999-03-09 | Altera Corporation | Interleaved interconnect for programmable logic array devices |
US5999016A (en) * | 1996-10-10 | 1999-12-07 | Altera Corporation | Architectures for programmable logic devices |
US5977793A (en) * | 1996-10-10 | 1999-11-02 | Altera Corporation | Programmable logic device with hierarchical interconnection resources |
US6300794B1 (en) | 1996-10-10 | 2001-10-09 | Altera Corporation | Programmable logic device with hierarchical interconnection resources |
US6427156B1 (en) * | 1997-01-21 | 2002-07-30 | Xilinx, Inc. | Configurable logic block with AND gate for efficient multiplication in FPGAS |
US5982195A (en) * | 1997-02-20 | 1999-11-09 | Altera Corporation | Programmable logic device architectures |
US7148722B1 (en) | 1997-02-20 | 2006-12-12 | Altera Corporation | PCI-compatible programmable logic devices |
US5999015A (en) * | 1997-02-20 | 1999-12-07 | Altera Corporation | Logic region resources for programmable logic devices |
US6127844A (en) | 1997-02-20 | 2000-10-03 | Altera Corporation | PCI-compatible programmable logic devices |
US5914616A (en) * | 1997-02-26 | 1999-06-22 | Xilinx, Inc. | FPGA repeatable interconnect structure with hierarchical interconnect lines |
US5963050A (en) | 1997-02-26 | 1999-10-05 | Xilinx, Inc. | Configurable logic element with fast feedback paths |
US5942913A (en) * | 1997-03-20 | 1999-08-24 | Xilinx, Inc. | FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines |
US6201410B1 (en) | 1997-02-26 | 2001-03-13 | Xilinx, Inc. | Wide logic gate implemented in an FPGA configurable logic element |
US5889411A (en) * | 1997-02-26 | 1999-03-30 | Xilinx, Inc. | FPGA having logic element carry chains capable of generating wide XOR functions |
US5920202A (en) * | 1997-02-26 | 1999-07-06 | Xilinx, Inc. | Configurable logic element with ability to evaluate five and six input functions |
US6204689B1 (en) | 1997-02-26 | 2001-03-20 | Xilinx, Inc. | Input/output interconnect circuit for FPGAs |
US6184710B1 (en) | 1997-03-20 | 2001-02-06 | Altera Corporation | Programmable logic array devices with enhanced interconnectivity between adjacent logic regions |
US6084427A (en) * | 1998-05-19 | 2000-07-04 | Altera Corporation | Programmable logic devices with enhanced multiplexing capabilities |
US6107825A (en) * | 1997-10-16 | 2000-08-22 | Altera Corporation | Input/output circuitry for programmable logic devices |
US6121790A (en) | 1997-10-16 | 2000-09-19 | Altera Corporation | Programmable logic device with enhanced multiplexing capabilities in interconnect resources |
US6107824A (en) | 1997-10-16 | 2000-08-22 | Altera Corporation | Circuitry and methods for internal interconnection of programmable logic devices |
US6218859B1 (en) * | 1998-05-26 | 2001-04-17 | Altera Corporation | Programmable logic device having quadrant layout |
CN1180667C (zh) * | 1998-07-20 | 2004-12-15 | 三星电子株式会社 | 无线电-电子部件 |
US6353920B1 (en) * | 1998-11-17 | 2002-03-05 | Xilinx, Inc. | Method for implementing wide gates and tristate buffers using FPGA carry logic |
US6215326B1 (en) | 1998-11-18 | 2001-04-10 | Altera Corporation | Programmable logic device architecture with super-regions having logic regions and a memory region |
US6507216B1 (en) | 1998-11-18 | 2003-01-14 | Altera Corporation | Efficient arrangement of interconnection resources on programmable logic devices |
US6191612B1 (en) * | 1998-11-19 | 2001-02-20 | Vantis Corporation | Enhanced I/O control flexibility for generating control signals |
JP3616518B2 (ja) * | 1999-02-10 | 2005-02-02 | 日本電気株式会社 | プログラマブルデバイス |
US6407576B1 (en) | 1999-03-04 | 2002-06-18 | Altera Corporation | Interconnection and input/output resources for programmable logic integrated circuit devices |
US6333641B1 (en) | 1999-05-07 | 2001-12-25 | Morphics Technology, Inc. | Apparatus and methods for dynamically defining variably sized autonomous sub-arrays within a programmable gate array |
US6320412B1 (en) | 1999-12-20 | 2001-11-20 | Btr, Inc. C/O Corporate Trust Co. | Architecture and interconnect for programmable logic circuits |
US6657457B1 (en) * | 2000-03-15 | 2003-12-02 | Intel Corporation | Data transfer on reconfigurable chip |
JP2001319976A (ja) * | 2000-05-11 | 2001-11-16 | Nec Corp | 半導体装置 |
US6724810B1 (en) | 2000-11-17 | 2004-04-20 | Xilinx, Inc. | Method and apparatus for de-spreading spread spectrum signals |
US6605962B2 (en) * | 2001-05-06 | 2003-08-12 | Altera Corporation | PLD architecture for flexible placement of IP function blocks |
US6653862B2 (en) * | 2001-05-06 | 2003-11-25 | Altera Corporation | Use of dangling partial lines for interfacing in a PLD |
JP2003297932A (ja) * | 2002-03-29 | 2003-10-17 | Toshiba Corp | 半導体装置 |
US6876227B2 (en) * | 2002-03-29 | 2005-04-05 | Parama Networks, Inc. | Simplifying the layout of printed circuit boards |
JP2003338750A (ja) | 2002-05-20 | 2003-11-28 | Nec Electronics Corp | 汎用ロジックセル、これを用いた汎用ロジックセルアレイ、及びこの汎用ロジックセルアレイを用いたasic |
US6975139B2 (en) | 2004-03-30 | 2005-12-13 | Advantage Logic, Inc. | Scalable non-blocking switching network for programmable logic |
WO2011061099A1 (en) * | 2004-04-02 | 2011-05-26 | Panasonic Corporation | Reset/load and signal distribution network |
US7460529B2 (en) | 2004-07-29 | 2008-12-02 | Advantage Logic, Inc. | Interconnection fabric using switching networks in hierarchy |
US7423453B1 (en) | 2006-01-20 | 2008-09-09 | Advantage Logic, Inc. | Efficient integrated circuit layout scheme to implement a scalable switching network used in interconnection fabric |
US7737751B1 (en) * | 2006-08-25 | 2010-06-15 | Altera Corporation | Periphery clock distribution network for a programmable logic device |
JP2008159608A (ja) * | 2006-12-20 | 2008-07-10 | Fujitsu Ltd | 半導体装置、半導体装置の製造方法および半導体装置の設計装置 |
FR2933826B1 (fr) * | 2008-07-09 | 2011-11-18 | Univ Paris Curie | Reseau logique programmable, commutateur d'interconnexion et unite logique pour un tel reseau |
US7999570B2 (en) | 2009-06-24 | 2011-08-16 | Advantage Logic, Inc. | Enhanced permutable switching network with multicasting signals for interconnection fabric |
US11614770B2 (en) | 2020-09-16 | 2023-03-28 | Gowin Semiconductor Corporation | Methods and apparatus for organizing a programmable semiconductor device into multiple clock regions |
US11216022B1 (en) * | 2020-09-16 | 2022-01-04 | Gowin Semiconductor Corporation | Methods and apparatus for providing a clock fabric for an FPGA organized in multiple clock regions |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4642487A (en) * | 1984-09-26 | 1987-02-10 | Xilinx, Inc. | Special interconnect for configurable logic array |
ES2002307A6 (es) | 1985-09-11 | 1988-08-01 | Pilkington Micro Electronics | Un circuito integrado semiconductor configurable |
US4864381A (en) * | 1986-06-23 | 1989-09-05 | Harris Corporation | Hierarchical variable die size gate array architecture |
US4918440A (en) * | 1986-11-07 | 1990-04-17 | Furtek Frederick C | Programmable logic cell and array |
US4969121A (en) * | 1987-03-02 | 1990-11-06 | Altera Corporation | Programmable integrated circuit logic array device having improved microprocessor connectability |
US5109353A (en) * | 1988-12-02 | 1992-04-28 | Quickturn Systems, Incorporated | Apparatus for emulation of electronic hardware system |
GB8828828D0 (en) | 1988-12-09 | 1989-01-18 | Pilkington Micro Electronics | Semiconductor integrated circuit |
GB8906145D0 (en) * | 1989-03-17 | 1989-05-04 | Algotronix Ltd | Configurable cellular array |
US5255203A (en) * | 1989-08-15 | 1993-10-19 | Advanced Micro Devices, Inc. | Interconnect structure for programmable logic device |
JP2756325B2 (ja) * | 1989-12-07 | 1998-05-25 | 株式会社日立製作所 | クロック供給回路 |
US5144166A (en) * | 1990-11-02 | 1992-09-01 | Concurrent Logic, Inc. | Programmable logic cell and array |
US5218240A (en) * | 1990-11-02 | 1993-06-08 | Concurrent Logic, Inc. | Programmable logic cell and array with bus repeaters |
JP3179800B2 (ja) * | 1991-07-22 | 2001-06-25 | 株式会社日立製作所 | 半導体集積回路装置 |
US5208491A (en) * | 1992-01-07 | 1993-05-04 | Washington Research Foundation | Field programmable gate array |
GB9223226D0 (en) * | 1992-11-05 | 1992-12-16 | Algotronix Ltd | Improved configurable cellular array (cal ii) |
GB2280293B (en) * | 1993-07-19 | 1997-12-10 | Hewlett Packard Co | Architecture for programmable logic |
US5457410A (en) * | 1993-08-03 | 1995-10-10 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
US5455525A (en) * | 1993-12-06 | 1995-10-03 | Intelligent Logic Systems, Inc. | Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array |
-
1993
- 1993-06-18 GB GB939312674A patent/GB9312674D0/en active Pending
-
1994
- 1994-06-01 AT AT94303952T patent/ATE198685T1/de active
- 1994-06-01 SG SG9804165A patent/SG88743A1/en unknown
- 1994-06-01 DE DE69431848T patent/DE69431848T2/de not_active Expired - Fee Related
- 1994-06-01 SG SG1996001812A patent/SG64300A1/en unknown
- 1994-06-01 AT AT97101407T patent/ATE229245T1/de not_active IP Right Cessation
- 1994-06-01 GB GB9410980A patent/GB2279168B/en not_active Expired - Fee Related
- 1994-06-01 EP EP94303952A patent/EP0630115B1/de not_active Expired - Lifetime
- 1994-06-01 EP EP97101407A patent/EP0776093B1/de not_active Expired - Lifetime
- 1994-06-01 DE DE69426546T patent/DE69426546T2/de not_active Expired - Fee Related
- 1994-06-02 US US08/253,041 patent/US5903165A/en not_active Expired - Fee Related
- 1994-06-07 CA CA002125307A patent/CA2125307A1/en not_active Abandoned
- 1994-06-09 AU AU64654/94A patent/AU685100B2/en not_active Ceased
- 1994-06-15 TW TW083105389A patent/TW242192B/zh not_active IP Right Cessation
- 1994-06-17 KR KR1019940013723A patent/KR100340310B1/ko not_active IP Right Cessation
- 1994-06-17 RU RU94021641/25A patent/RU94021641A/ru unknown
- 1994-06-20 JP JP13758794A patent/JP3547168B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR950001990A (ko) | 1995-01-04 |
GB2279168A (en) | 1994-12-21 |
TW242192B (de) | 1995-03-01 |
EP0776093A2 (de) | 1997-05-28 |
EP0630115A2 (de) | 1994-12-21 |
EP0776093B1 (de) | 2002-12-04 |
SG64300A1 (en) | 1999-04-27 |
ATE229245T1 (de) | 2002-12-15 |
SG88743A1 (en) | 2002-05-21 |
KR100340310B1 (ko) | 2002-11-23 |
EP0776093A3 (de) | 1997-06-18 |
JPH0758631A (ja) | 1995-03-03 |
GB2279168B (en) | 1998-01-21 |
AU685100B2 (en) | 1998-01-15 |
US5903165A (en) | 1999-05-11 |
RU94021641A (ru) | 1996-06-27 |
EP0630115B1 (de) | 2001-01-10 |
DE69426546D1 (de) | 2001-02-15 |
CA2125307A1 (en) | 1994-12-19 |
DE69426546T2 (de) | 2001-07-12 |
GB9410980D0 (en) | 1994-07-20 |
AU6465494A (en) | 1994-12-22 |
ATE198685T1 (de) | 2001-01-15 |
JP3547168B2 (ja) | 2004-07-28 |
GB9312674D0 (en) | 1993-08-04 |
EP0630115A3 (de) | 1995-03-22 |
DE69431848T2 (de) | 2003-05-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |