DE69333381D1 - Serieller Frequenzumsetzer mit Tolerierung von Jitter an der Nutzlast - Google Patents

Serieller Frequenzumsetzer mit Tolerierung von Jitter an der Nutzlast

Info

Publication number
DE69333381D1
DE69333381D1 DE69333381T DE69333381T DE69333381D1 DE 69333381 D1 DE69333381 D1 DE 69333381D1 DE 69333381 T DE69333381 T DE 69333381T DE 69333381 T DE69333381 T DE 69333381T DE 69333381 D1 DE69333381 D1 DE 69333381D1
Authority
DE
Germany
Prior art keywords
flowrate
serial
high data
stream
rate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69333381T
Other languages
English (en)
Other versions
DE69333381T2 (de
Inventor
Gregory W Boop
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Lucent SAS
Original Assignee
Alcatel SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel SA filed Critical Alcatel SA
Application granted granted Critical
Publication of DE69333381D1 publication Critical patent/DE69333381D1/de
Publication of DE69333381T2 publication Critical patent/DE69333381T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/12Arrangements providing for calling or supervisory signals
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/16Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605Fixed allocated frame structures
    • H04J3/1611Synchronous digital hierarchy [SDH] or SONET
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J2203/00Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0057Operations, administration and maintenance [OAM]
    • H04J2203/0058Network management, e.g. Intelligent nets
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J2203/00Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0089Multiplexing, e.g. coding, scrambling, SONET

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Dc Digital Transmission (AREA)
  • Television Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Optical Communication System (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
DE69333381T 1992-10-16 1993-09-21 Serieller Frequenzumsetzer mit Tolerierung von Jitter an der Nutzlast Expired - Fee Related DE69333381T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US962319 1992-10-16
US07/962,319 US5425062A (en) 1992-10-16 1992-10-16 Serial rate conversion circuit with jitter tolerant payload

Publications (2)

Publication Number Publication Date
DE69333381D1 true DE69333381D1 (de) 2004-02-19
DE69333381T2 DE69333381T2 (de) 2004-10-14

Family

ID=25505702

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69333381T Expired - Fee Related DE69333381T2 (de) 1992-10-16 1993-09-21 Serieller Frequenzumsetzer mit Tolerierung von Jitter an der Nutzlast

Country Status (5)

Country Link
US (1) US5425062A (de)
EP (1) EP0592842B1 (de)
AT (1) ATE257990T1 (de)
DE (1) DE69333381T2 (de)
ES (1) ES2210233T3 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5692159A (en) * 1995-05-19 1997-11-25 Digital Equipment Corporation Configurable digital signal interface using field programmable gate array to reformat data
US6198720B1 (en) * 1996-12-26 2001-03-06 Alcatel Usa Sourcing, L.P. Distributed digital cross-connect system and method
KR100251736B1 (ko) * 1997-12-29 2000-04-15 윤종용 직렬 데이터의 전송속도 변환 장치
US6928573B2 (en) * 2001-11-20 2005-08-09 Broadcom Corporation Communication clocking conversion techniques

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4229815A (en) * 1978-11-20 1980-10-21 Bell Telephone Laboratories, Incorporated Full duplex bit synchronous data rate buffer
US4259738A (en) * 1979-05-18 1981-03-31 Raytheon Company Multiplexer system providing improved bit count integrity
US4839893A (en) * 1987-10-05 1989-06-13 Dallas Semiconductor Corporation Telecommunications FIFO

Also Published As

Publication number Publication date
EP0592842B1 (de) 2004-01-14
DE69333381T2 (de) 2004-10-14
US5425062A (en) 1995-06-13
ATE257990T1 (de) 2004-01-15
ES2210233T3 (es) 2004-07-01
EP0592842A3 (en) 1996-03-06
EP0592842A2 (de) 1994-04-20

Similar Documents

Publication Publication Date Title
AU7106191A (en) Digital clock buffer circuit providing controllable delay
ATE192616T1 (de) Inkrementaler phasenglättungsdesynchronisierer und rechenanordnung
CA2088156A1 (en) Method and means for transferring a data payload from a first sonet signal to a sonet signal of different frequency
MY105780A (en) Digital transmission system, transmitter and receiver for use in the transmission sytstem, and record carrier obtained by means of the treansmitter in the form of a recording device
CA2302370A1 (en) System and method for high-speed, synchronized data communication
AU8353491A (en) Justification decision circuit for an arrangement for bit rate adjustment
EP1043721A3 (de) Verfahren zur Aufnahme von digitalen Daten
JPH04227142A (ja) 2つのディジタル信号のビット速度調整用回路配置
DE69333381D1 (de) Serieller Frequenzumsetzer mit Tolerierung von Jitter an der Nutzlast
CA2105659A1 (en) Optical clock extraction
GB2204467A (en) Method and apparatus for generating a data recovery window
ES2117040T3 (es) Dispositivo de sincronizacion para equipamiento de terminal de una red de telecomunicaciones digital con transferencia en modo asincrono.
EP0709845A3 (de) Digitalsignalaufzeichnungsgerät
CA2063157A1 (en) Repeater station wherein input frame data are accessible
GR3033221T3 (en) Method and arrangement for recovering plesiochrone signals transmitted in tributaries.
EP0374537A3 (de) Demultiplexer mit Schaltung zur Verringerung des Wartezeitjitters
EP0418641A3 (en) Asynchronization device for a digital signal
DE69721183D1 (de) Digitalsignalwiedergabe
EP0559957A3 (de)
CA2063000A1 (en) Method and circuit for demultiplexing digital signals capable of absorbing destuffing jitter
GR3007226T3 (de)
JPS573458A (en) Carrier pickup circuit
EP0212961A3 (de) Rahmeneinteilung für digitale Übertragungskanäle
JPS54157004A (en) Data highway central control unit
KUEHNE et al. Intrinsic jitter of positive zero negative justification systems using digital clock recovery

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: ALCATEL LUCENT, PARIS, FR

8339 Ceased/non-payment of the annual fee