DE69332407T2 - Herstellung von Halbleiteranordnungen auf SOI substraten - Google Patents
Herstellung von Halbleiteranordnungen auf SOI substratenInfo
- Publication number
- DE69332407T2 DE69332407T2 DE69332407T DE69332407T DE69332407T2 DE 69332407 T2 DE69332407 T2 DE 69332407T2 DE 69332407 T DE69332407 T DE 69332407T DE 69332407 T DE69332407 T DE 69332407T DE 69332407 T2 DE69332407 T2 DE 69332407T2
- Authority
- DE
- Germany
- Prior art keywords
- manufacture
- semiconductor devices
- soi substrates
- soi
- substrates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76275—Vertical isolation by bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76286—Lateral isolation by refilling of trenches with polycristalline material
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/012—Bonding, e.g. electrostatic for strain gauges
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/05—Etch and refill
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/938—Lattice strain control or utilization
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US90020292A | 1992-06-17 | 1992-06-17 | |
PCT/US1993/005828 WO1993026041A1 (en) | 1992-06-17 | 1993-06-17 | Bonded wafer processing |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69332407D1 DE69332407D1 (de) | 2002-11-21 |
DE69332407T2 true DE69332407T2 (de) | 2003-06-18 |
Family
ID=25412130
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69332407T Expired - Fee Related DE69332407T2 (de) | 1992-06-17 | 1993-06-17 | Herstellung von Halbleiteranordnungen auf SOI substraten |
Country Status (5)
Country | Link |
---|---|
US (2) | US5780311A (de) |
EP (1) | EP0646286B1 (de) |
JP (1) | JPH08501900A (de) |
DE (1) | DE69332407T2 (de) |
WO (1) | WO1993026041A1 (de) |
Families Citing this family (91)
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---|---|---|---|---|
DE69317800T2 (de) * | 1992-01-28 | 1998-09-03 | Canon Kk | Verfahren zur Herstellung einer Halbleiteranordnung |
US6674562B1 (en) * | 1994-05-05 | 2004-01-06 | Iridigm Display Corporation | Interferometric modulation of radiation |
JP2526786B2 (ja) * | 1993-05-22 | 1996-08-21 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US7550794B2 (en) * | 2002-09-20 | 2009-06-23 | Idc, Llc | Micromechanical systems device comprising a displaceable electrode and a charge-trapping layer |
WO1996020497A1 (en) * | 1994-12-23 | 1996-07-04 | Philips Electronics N.V. | Method of manufacturing semiconductor devices with semiconductor elements formed in a layer of semiconductor material glued on a support wafer |
DE19538005A1 (de) | 1995-10-12 | 1997-04-17 | Fraunhofer Ges Forschung | Verfahren zum Erzeugen einer Grabenisolation in einem Substrat |
JP3378135B2 (ja) * | 1996-02-02 | 2003-02-17 | 三菱電機株式会社 | 半導体装置とその製造方法 |
US5930652A (en) * | 1996-05-28 | 1999-07-27 | Motorola, Inc. | Semiconductor encapsulation method |
JP3139426B2 (ja) * | 1997-10-15 | 2001-02-26 | 日本電気株式会社 | 半導体装置 |
US6303967B1 (en) | 1998-02-05 | 2001-10-16 | Integration Associates, Inc. | Process for producing an isolated planar high speed pin photodiode |
US6027956A (en) * | 1998-02-05 | 2000-02-22 | Integration Associates, Inc. | Process for producing planar dielectrically isolated high speed pin photodiode |
US6548878B1 (en) | 1998-02-05 | 2003-04-15 | Integration Associates, Inc. | Method for producing a thin distributed photodiode structure |
US6458619B1 (en) | 1998-02-05 | 2002-10-01 | Integration Associates, Inc. | Process for producing an isolated planar high speed pin photodiode with improved capacitance |
US6753586B1 (en) | 1998-03-09 | 2004-06-22 | Integration Associates Inc. | Distributed photodiode structure having majority dopant gradient and method for making same |
US8928967B2 (en) | 1998-04-08 | 2015-01-06 | Qualcomm Mems Technologies, Inc. | Method and device for modulating light |
WO1999052006A2 (en) | 1998-04-08 | 1999-10-14 | Etalon, Inc. | Interferometric modulation of radiation |
US6013936A (en) * | 1998-08-06 | 2000-01-11 | International Business Machines Corporation | Double silicon-on-insulator device and method therefor |
US6815774B1 (en) * | 1998-10-29 | 2004-11-09 | Mitsubishi Materials Silicon Corporation | Dielectrically separated wafer and method of the same |
US6362075B1 (en) * | 1999-06-30 | 2002-03-26 | Harris Corporation | Method for making a diffused back-side layer on a bonded-wafer with a thick bond oxide |
US6690078B1 (en) | 1999-08-05 | 2004-02-10 | Integration Associates, Inc. | Shielded planar dielectrically isolated high speed pin photodiode and method for producing same |
EP1089328A1 (de) * | 1999-09-29 | 2001-04-04 | Infineon Technologies AG | Verfahren zur Herstellung eines Halbleiterbauelementes |
US6693033B2 (en) | 2000-02-10 | 2004-02-17 | Motorola, Inc. | Method of removing an amorphous oxide from a monocrystalline surface |
US6399427B1 (en) * | 2000-02-24 | 2002-06-04 | Advanced Micro Devices, Inc. | Formation of ultra-thin active device area on semiconductor on insulator (SOI) substrate |
FR2812451B1 (fr) * | 2000-07-28 | 2003-01-10 | St Microelectronics Sa | Procede de fabrication d'un ensemble silicium sur isolant a ilots minces semi-conducteurs entoures d'un materiau isolant |
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US7123448B1 (en) * | 2000-10-13 | 2006-10-17 | Seagate Technology, Llc | Extended alumina basecoat advanced air bearing slider |
JP2002141253A (ja) * | 2000-10-31 | 2002-05-17 | Disco Abrasive Syst Ltd | 半導体装置 |
EP1217656A1 (de) * | 2000-12-20 | 2002-06-26 | STMicroelectronics S.r.l. | Herstellungverfahren von Komponenten in einer Halbleiterscheibe mit Reduzierung der Anfangsdicke der Scheibe |
US6673646B2 (en) | 2001-02-28 | 2004-01-06 | Motorola, Inc. | Growth of compound semiconductor structures on patterned oxide films and process for fabricating same |
US7238622B2 (en) * | 2001-04-17 | 2007-07-03 | California Institute Of Technology | Wafer bonded virtual substrate and method for forming the same |
US20050026432A1 (en) * | 2001-04-17 | 2005-02-03 | Atwater Harry A. | Wafer bonded epitaxial templates for silicon heterostructures |
US6709989B2 (en) | 2001-06-21 | 2004-03-23 | Motorola, Inc. | Method for fabricating a semiconductor structure including a metal oxide interface with silicon |
US6485992B1 (en) * | 2001-07-03 | 2002-11-26 | Memc Electronic Materials, Inc. | Process for making wafers for ion implantation monitoring |
US6646293B2 (en) | 2001-07-18 | 2003-11-11 | Motorola, Inc. | Structure for fabricating high electron mobility transistors utilizing the formation of complaint substrates |
US6693298B2 (en) | 2001-07-20 | 2004-02-17 | Motorola, Inc. | Structure and method for fabricating epitaxial semiconductor on insulator (SOI) structures and devices utilizing the formation of a compliant substrate for materials used to form same |
US6667196B2 (en) | 2001-07-25 | 2003-12-23 | Motorola, Inc. | Method for real-time monitoring and controlling perovskite oxide film growth and semiconductor structure formed using the method |
US6603916B1 (en) | 2001-07-26 | 2003-08-05 | Lightwave Microsystems Corporation | Lightwave circuit assembly having low deformation balanced sandwich substrate |
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US6639249B2 (en) | 2001-08-06 | 2003-10-28 | Motorola, Inc. | Structure and method for fabrication for a solid-state lighting device |
US6673667B2 (en) | 2001-08-15 | 2004-01-06 | Motorola, Inc. | Method for manufacturing a substantially integral monolithic apparatus including a plurality of semiconductor materials |
EP1302984A1 (de) * | 2001-10-09 | 2003-04-16 | STMicroelectronics S.r.l. | Schutzstruktur gegen elektrostatische Entladungen (ESD) für ein auf einem SOI-Substrat integriertes elektronisches Bauelement und entsprechendes Integrationsverfahren |
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US7262112B2 (en) * | 2005-06-27 | 2007-08-28 | The Regents Of The University Of California | Method for producing dislocation-free strained crystalline films |
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JP5853389B2 (ja) * | 2011-03-28 | 2016-02-09 | ソニー株式会社 | 半導体装置及び半導体装置の製造方法。 |
EP2600389B1 (de) | 2011-11-29 | 2020-01-15 | IMEC vzw | Verfahren zum Bonden von Halbleitersubstraten |
US8927334B2 (en) | 2012-09-25 | 2015-01-06 | International Business Machines Corporation | Overcoming chip warping to enhance wetting of solder bumps and flip chip attaches in a flip chip package |
US9397051B2 (en) | 2013-12-03 | 2016-07-19 | Invensas Corporation | Warpage reduction in structures with electrical circuitry |
US9997348B2 (en) | 2016-09-28 | 2018-06-12 | International Business Machines Corporation | Wafer stress control and topography compensation |
FR3064398B1 (fr) | 2017-03-21 | 2019-06-07 | Soitec | Structure de type semi-conducteur sur isolant, notamment pour un capteur d'image de type face avant, et procede de fabrication d'une telle structure |
CN107731668B (zh) * | 2017-08-31 | 2018-11-13 | 长江存储科技有限责任公司 | 3d nand混合键合工艺中补偿晶圆应力的方法 |
CN108649034B (zh) * | 2018-05-11 | 2019-08-06 | 长江存储科技有限责任公司 | 半导体结构及其形成方法 |
CN220502678U (zh) * | 2019-01-16 | 2024-02-20 | 株式会社村田制作所 | 具有腔体的硅基板以及使用了该硅基板的腔体soi基板 |
TWI734318B (zh) * | 2019-12-25 | 2021-07-21 | 合晶科技股份有限公司 | 絕緣層上覆矽的製造方法 |
CN111276542B (zh) * | 2020-02-17 | 2022-08-09 | 绍兴中芯集成电路制造股份有限公司 | 沟槽型mos器件及其制造方法 |
US11830773B2 (en) * | 2020-02-26 | 2023-11-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with isolation structures |
CN113964024B (zh) * | 2021-12-21 | 2022-06-03 | 广州粤芯半导体技术有限公司 | 半导体器件的制备方法 |
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JPH0394416A (ja) * | 1989-09-07 | 1991-04-19 | Sumitomo Metal Mining Co Ltd | Soi基板の製造方法 |
JPH03129854A (ja) * | 1989-10-16 | 1991-06-03 | Toshiba Corp | 半導体装置の製造方法 |
DE69126153T2 (de) * | 1990-02-28 | 1998-01-08 | Shinetsu Handotai Kk | Verfahren zur Herstellung von verbundenen Halbleiterplättchen |
JP2721265B2 (ja) * | 1990-07-05 | 1998-03-04 | 株式会社東芝 | 半導体基板の製造方法 |
JPH0488657A (ja) * | 1990-07-31 | 1992-03-23 | Toshiba Corp | 半導体装置とその製造方法 |
US5113236A (en) * | 1990-12-14 | 1992-05-12 | North American Philips Corporation | Integrated circuit device particularly adapted for high voltage applications |
JPH07118505B2 (ja) * | 1990-12-28 | 1995-12-18 | 信越半導体株式会社 | 誘電体分離基板の製造方法 |
US5276338A (en) * | 1992-05-15 | 1994-01-04 | International Business Machines Corporation | Bonded wafer structure having a buried insulation layer |
-
1993
- 1993-06-17 DE DE69332407T patent/DE69332407T2/de not_active Expired - Fee Related
- 1993-06-17 EP EP93915402A patent/EP0646286B1/de not_active Expired - Lifetime
- 1993-06-17 JP JP6501822A patent/JPH08501900A/ja active Pending
- 1993-06-17 WO PCT/US1993/005828 patent/WO1993026041A1/en active IP Right Grant
-
1997
- 1997-01-15 US US08/783,792 patent/US5780311A/en not_active Expired - Lifetime
- 1997-04-14 US US08/843,302 patent/US5801084A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US5780311A (en) | 1998-07-14 |
EP0646286B1 (de) | 2002-10-16 |
JPH08501900A (ja) | 1996-02-27 |
WO1993026041A1 (en) | 1993-12-23 |
EP0646286A1 (de) | 1995-04-05 |
US5801084A (en) | 1998-09-01 |
DE69332407D1 (de) | 2002-11-21 |
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