DE69320416T2 - Halbleiter-Speichergerät mit Spannungstressprüfmodus - Google Patents

Halbleiter-Speichergerät mit Spannungstressprüfmodus

Info

Publication number
DE69320416T2
DE69320416T2 DE69320416T DE69320416T DE69320416T2 DE 69320416 T2 DE69320416 T2 DE 69320416T2 DE 69320416 T DE69320416 T DE 69320416T DE 69320416 T DE69320416 T DE 69320416T DE 69320416 T2 DE69320416 T2 DE 69320416T2
Authority
DE
Germany
Prior art keywords
circuit
voltage stress
test mode
stress test
dram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69320416T
Other languages
English (en)
Other versions
DE69320416D1 (de
Inventor
Takashi Ohsawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP04153482A external-priority patent/JP3135681B2/ja
Priority claimed from JP04153485A external-priority patent/JP3105078B2/ja
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69320416D1 publication Critical patent/DE69320416D1/de
Application granted granted Critical
Publication of DE69320416T2 publication Critical patent/DE69320416T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/20—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits using counters or linear-feedback shift registers [LFSR]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/34—Accessing multiple bits simultaneously
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/88—Monitoring involving counting
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004—Voltage

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
DE69320416T 1992-06-12 1993-06-11 Halbleiter-Speichergerät mit Spannungstressprüfmodus Expired - Fee Related DE69320416T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP04153482A JP3135681B2 (ja) 1992-06-12 1992-06-12 半導体記憶装置
JP04153485A JP3105078B2 (ja) 1992-06-12 1992-06-12 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69320416D1 DE69320416D1 (de) 1998-09-24
DE69320416T2 true DE69320416T2 (de) 1999-02-04

Family

ID=26482088

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69320416T Expired - Fee Related DE69320416T2 (de) 1992-06-12 1993-06-11 Halbleiter-Speichergerät mit Spannungstressprüfmodus

Country Status (4)

Country Link
US (1) US5381373A (de)
EP (1) EP0574002B1 (de)
KR (1) KR950014099B1 (de)
DE (1) DE69320416T2 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10014388A1 (de) * 2000-03-23 2001-10-04 Infineon Technologies Ag Verfahren zur Durchführung eines Burn-in-Prozesses eines Speichers

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JP3155879B2 (ja) * 1994-02-25 2001-04-16 株式会社東芝 半導体集積回路装置
KR0122100B1 (ko) * 1994-03-10 1997-11-26 김광호 스트레스회로를 가지는 반도체집적회로 및 그 스트레스전압공급방법
KR0119887B1 (ko) * 1994-06-08 1997-10-30 김광호 반도체 메모리장치의 웨이퍼 번-인 테스트 회로
KR0135108B1 (ko) * 1994-12-13 1998-04-25 김광호 스트레스 테스트 회로를 포함하는 반도체 메모리 장치
US5689466A (en) * 1995-04-07 1997-11-18 National Semiconductor Corporation Built in self test (BIST) for multiple RAMs
US6041426A (en) * 1995-04-07 2000-03-21 National Semiconductor Corporation Built in self test BIST for RAMS using a Johnson counter as a source of data
US5568435A (en) * 1995-04-12 1996-10-22 Micron Technology, Inc. Circuit for SRAM test mode isolated bitline modulation
DE69532376T2 (de) * 1995-05-31 2004-06-09 United Memories, Inc., Colorado Springs Schaltung und Verfahren zum Zugriff auf Speicherzellen einer Speicheranordnung
US5965902A (en) * 1995-09-19 1999-10-12 Micron Technology Method and apparatus for testing of dielectric defects in a packaged semiconductor memory device
US5657284A (en) 1995-09-19 1997-08-12 Micron Technology, Inc. Apparatus and method for testing for defects between memory cells in packaged semiconductor memory devices
US5559739A (en) * 1995-09-28 1996-09-24 International Business Machines Corporation Dynamic random access memory with a simple test arrangement
JPH09147599A (ja) * 1995-11-28 1997-06-06 Mitsubishi Electric Corp 半導体記憶装置
KR100200926B1 (ko) * 1996-08-29 1999-06-15 윤종용 내부전원전압 발생회로
KR100206710B1 (ko) * 1996-09-23 1999-07-01 윤종용 반도체 메모리 장치의 웨이퍼 번인 테스트 회로
KR100220950B1 (ko) * 1996-11-06 1999-09-15 김영환 웨이퍼 번인회로
US6059450A (en) * 1996-12-21 2000-05-09 Stmicroelectronics, Inc. Edge transition detection circuitry for use with test mode operation of an integrated circuit memory device
DE19735406A1 (de) 1997-08-14 1999-02-18 Siemens Ag Halbleiterbauelement und Verfahren zum Testen und Betreiben eines Halbleiterbauelementes
US6079037A (en) 1997-08-20 2000-06-20 Micron Technology, Inc. Method and apparatus for detecting intercell defects in a memory device
US6094734A (en) * 1997-08-22 2000-07-25 Micron Technology, Inc. Test arrangement for memory devices using a dynamic row for creating test data
KR100269322B1 (ko) * 1998-01-16 2000-10-16 윤종용 스트레스용전압을이용하여메모리를테스팅하는기능을갖는집적회로및그의메모리테스트방법
KR100267781B1 (ko) * 1998-03-04 2000-10-16 김영환 테스트 모드를 셋업하기 위한 반도체 소자
US6067261A (en) * 1998-08-03 2000-05-23 International Business Machines Corporation Timing of wordline activation for DC burn-in of a DRAM with the self-refresh
US6122760A (en) * 1998-08-25 2000-09-19 International Business Machines Corporation Burn in technique for chips containing different types of IC circuitry
US6055199A (en) * 1998-10-21 2000-04-25 Mitsubishi Denki Kabushiki Kaisha Test circuit for a semiconductor memory device and method for burn-in test
KR100343283B1 (ko) 1999-07-02 2002-07-15 윤종용 반도체 장치의 테스트 전원 공급 회로
KR100355225B1 (ko) * 1999-07-12 2002-10-11 삼성전자 주식회사 교류 스트레스의 번-인 테스트가 가능한 집적회로 및 이를 이용한 테스트 방법
JP2001067898A (ja) * 1999-08-30 2001-03-16 Mitsubishi Electric Corp 半導体記憶装置
TW432574B (en) * 2000-01-19 2001-05-01 Yang Wen Kun Wafer level burn in device and method
US6535014B2 (en) 2000-01-19 2003-03-18 Lucent Technologies, Inc. Electrical parameter tester having decoupling means
JP2002074991A (ja) * 2000-08-31 2002-03-15 Fujitsu Ltd メモリを有する半導体装置
JP2002124096A (ja) * 2000-10-13 2002-04-26 Nec Corp 半導体記憶装置及びその試験方法
JP2003030999A (ja) * 2001-07-18 2003-01-31 Mitsubishi Electric Corp 半導体記憶装置
US6763314B2 (en) 2001-09-28 2004-07-13 International Business Machines Corporation AC defect detection and failure avoidance power up and diagnostic system
KR100413242B1 (ko) * 2001-12-20 2004-01-03 주식회사 하이닉스반도체 웨이퍼 번인 테스트 모드 회로
KR100442960B1 (ko) * 2001-12-21 2004-08-04 주식회사 하이닉스반도체 반도체 메모리 테스트 장치
US6728156B2 (en) * 2002-03-11 2004-04-27 International Business Machines Corporation Memory array system
US6791348B2 (en) * 2002-07-29 2004-09-14 International Business Machines Corporation Digital overcurrent test
KR100835279B1 (ko) * 2006-09-05 2008-06-05 삼성전자주식회사 수직 채널 구조를 가지는 트랜지스터를 구비하는 반도체메모리 장치
US7742351B2 (en) * 2006-06-30 2010-06-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic device
KR100904962B1 (ko) * 2007-05-31 2009-06-26 삼성전자주식회사 스트레스 검출 회로, 이를 포함하는 반도체 칩 및 스트레스검출 방법
JP5405007B2 (ja) * 2007-07-20 2014-02-05 ピーエスフォー ルクスコ エスエイアールエル 半導体装置
KR100845810B1 (ko) * 2007-08-14 2008-07-14 주식회사 하이닉스반도체 웨이퍼 번인 테스트 회로
US7924633B2 (en) * 2009-02-20 2011-04-12 International Business Machines Corporation Implementing boosted wordline voltage in memories
US8462571B2 (en) * 2011-07-19 2013-06-11 Elite Semiconductor Memory Technology Inc. DRAM and method for testing the same in the wafer level burn-in test mode
US8907687B2 (en) * 2012-05-03 2014-12-09 Globalfoundries Inc. Integrated circuit with stress generator for stressing test devices
US20140032826A1 (en) * 2012-07-25 2014-01-30 Samsung Electronics Co., Ltd. Method of training memory core and memory system
US9183951B2 (en) * 2013-09-11 2015-11-10 Tsuneo Inaba Resistance change memory and test method of the same
JP2015118724A (ja) * 2013-11-13 2015-06-25 株式会社半導体エネルギー研究所 半導体装置及び半導体装置の駆動方法
JP7086795B2 (ja) * 2018-09-03 2022-06-20 ルネサスエレクトロニクス株式会社 半導体装置
US11837313B2 (en) 2021-11-02 2023-12-05 Qualcomm Incorporated Memory with efficient DVS controlled by asynchronous inputs

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JPS61258399A (ja) * 1985-05-11 1986-11-15 Fujitsu Ltd 半導体集積回路装置
US5258954A (en) * 1989-06-30 1993-11-02 Kabushiki Kaisha Toshiba Semiconductor memory including circuitry for driving plural word lines in a test mode
JP2945508B2 (ja) * 1991-06-20 1999-09-06 三菱電機株式会社 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10014388A1 (de) * 2000-03-23 2001-10-04 Infineon Technologies Ag Verfahren zur Durchführung eines Burn-in-Prozesses eines Speichers

Also Published As

Publication number Publication date
US5381373A (en) 1995-01-10
DE69320416D1 (de) 1998-09-24
EP0574002B1 (de) 1998-08-19
EP0574002A2 (de) 1993-12-15
KR940006150A (ko) 1994-03-23
KR950014099B1 (ko) 1995-11-21
EP0574002A3 (de) 1995-03-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee