DE69233314D1 - Verfahren zur Herstellung von Halbleiter-Produkten - Google Patents

Verfahren zur Herstellung von Halbleiter-Produkten

Info

Publication number
DE69233314D1
DE69233314D1 DE69233314T DE69233314T DE69233314D1 DE 69233314 D1 DE69233314 D1 DE 69233314D1 DE 69233314 T DE69233314 T DE 69233314T DE 69233314 T DE69233314 T DE 69233314T DE 69233314 D1 DE69233314 D1 DE 69233314D1
Authority
DE
Germany
Prior art keywords
production
semiconductor products
semiconductor
products
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69233314T
Other languages
English (en)
Other versions
DE69233314T2 (de
Inventor
Takeshi Ichikawa
Takao Yonehara
Masaru Sakamoto
Yasuhiro Naruse
Jun Nakayama
Kenji Yamagata
Kiyofumi Sakaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Application granted granted Critical
Publication of DE69233314D1 publication Critical patent/DE69233314D1/de
Publication of DE69233314T2 publication Critical patent/DE69233314T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76289—Lateral isolation by air gap
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/012—Bonding, e.g. electrostatic for strain gauges
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/96—Porous semiconductor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate
DE69233314T 1991-10-11 1992-10-09 Verfahren zur Herstellung von Halbleiter-Produkten Expired - Lifetime DE69233314T2 (de)

Applications Claiming Priority (12)

Application Number Priority Date Filing Date Title
JP29225691 1991-10-11
JP29225591 1991-10-11
JP29225591 1991-10-11
JP29225691 1991-10-11
JP33457491 1991-11-25
JP33457491 1991-11-25
JP3573292 1992-01-28
JP3573292 1992-01-28
JP4195192 1992-01-31
JP4630192 1992-01-31
JP4630192 1992-01-31
JP4195192 1992-01-31

Publications (2)

Publication Number Publication Date
DE69233314D1 true DE69233314D1 (de) 2004-04-08
DE69233314T2 DE69233314T2 (de) 2005-03-24

Family

ID=27549781

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69233314T Expired - Lifetime DE69233314T2 (de) 1991-10-11 1992-10-09 Verfahren zur Herstellung von Halbleiter-Produkten

Country Status (4)

Country Link
US (1) US5466631A (de)
EP (1) EP0536790B1 (de)
JP (1) JP3112126B2 (de)
DE (1) DE69233314T2 (de)

Families Citing this family (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0499488B9 (de) * 1991-02-15 2004-01-28 Canon Kabushiki Kaisha Ätzlösung für das Ätzen von porösem Silizium, Ätzmethode unter Verwendung der Ätzlösung und Verfahren zur Vorbereitung einer Halbleiteranordnung unter Verwendung der Ätzlösung
JP3237888B2 (ja) * 1992-01-31 2001-12-10 キヤノン株式会社 半導体基体及びその作製方法
JP3191972B2 (ja) * 1992-01-31 2001-07-23 キヤノン株式会社 半導体基板の作製方法及び半導体基板
JP3120200B2 (ja) * 1992-10-12 2000-12-25 セイコーインスツルメンツ株式会社 光弁装置、立体画像表示装置および画像プロジェクタ
US5540810A (en) * 1992-12-11 1996-07-30 Micron Technology Inc. IC mechanical planarization process incorporating two slurry compositions for faster material removal times
US5597738A (en) * 1993-12-03 1997-01-28 Kulite Semiconductor Products, Inc. Method for forming isolated CMOS structures on SOI structures
US7148119B1 (en) 1994-03-10 2006-12-12 Canon Kabushiki Kaisha Process for production of semiconductor substrate
US20030087503A1 (en) * 1994-03-10 2003-05-08 Canon Kabushiki Kaisha Process for production of semiconductor substrate
JP3257580B2 (ja) * 1994-03-10 2002-02-18 キヤノン株式会社 半導体基板の作製方法
KR0175009B1 (ko) * 1995-07-28 1999-04-01 김광호 식각용액 및 이를 이용한 반도체 장치의 식각방법
SE9700215L (sv) * 1997-01-27 1998-02-18 Abb Research Ltd Förfarande för framställning av ett halvledarskikt av SiC av 3C-polytypen ovanpå ett halvledarsubstratskikt utnyttjas wafer-bindningstekniken
JP3647191B2 (ja) * 1997-03-27 2005-05-11 キヤノン株式会社 半導体装置の製造方法
US6191007B1 (en) * 1997-04-28 2001-02-20 Denso Corporation Method for manufacturing a semiconductor substrate
EP0995227A4 (de) * 1997-05-12 2000-07-05 Silicon Genesis Corp Kontrolliertes spaltungsverfahren
JP3501642B2 (ja) * 1997-12-26 2004-03-02 キヤノン株式会社 基板処理方法
DE19802131B4 (de) * 1998-01-21 2007-03-15 Robert Bosch Gmbh Verfahren zur Herstellung einer monokristallinen Schicht aus einem leitenden oder halbleitenden Material
DE19803013B4 (de) * 1998-01-27 2005-02-03 Robert Bosch Gmbh Verfahren zum Ablösen einer Epitaxieschicht oder eines Schichtsystems und nachfolgendem Aufbringen auf einen alternativen Träger
FR2779006B1 (fr) * 1998-05-19 2003-01-24 St Microelectronics Sa Procede de formation de silicium poreux dans un substrat de silicium, en particulier pour l'amelioration des performances d'un circuit inductif
US6040211A (en) * 1998-06-09 2000-03-21 Siemens Aktiengesellschaft Semiconductors having defect denuded zones
DE19838945A1 (de) * 1998-08-27 2000-03-09 Bosch Gmbh Robert Verfahren zur Herstellung einer defektarmen, einkristallinen Silizium-Carbid-Schicht
US6391743B1 (en) 1998-09-22 2002-05-21 Canon Kabushiki Kaisha Method and apparatus for producing photoelectric conversion device
JP2000223682A (ja) * 1999-02-02 2000-08-11 Canon Inc 基体の処理方法及び半導体基板の製造方法
US6410436B2 (en) 1999-03-26 2002-06-25 Canon Kabushiki Kaisha Method of cleaning porous body, and process for producing porous body, non-porous film or bonded substrate
US6326279B1 (en) 1999-03-26 2001-12-04 Canon Kabushiki Kaisha Process for producing semiconductor article
AT409429B (de) * 1999-07-15 2002-08-26 Sez Semiconduct Equip Zubehoer Verfahren zum ätzbehandeln von halbleitersubstraten zwecks freilegen einer metallschicht
TW587332B (en) * 2000-01-07 2004-05-11 Canon Kk Semiconductor substrate and process for its production
US6693033B2 (en) 2000-02-10 2004-02-17 Motorola, Inc. Method of removing an amorphous oxide from a monocrystalline surface
US6501973B1 (en) 2000-06-30 2002-12-31 Motorola, Inc. Apparatus and method for measuring selected physical condition of an animate subject
US6590236B1 (en) 2000-07-24 2003-07-08 Motorola, Inc. Semiconductor structure for use with high-frequency signals
US6555946B1 (en) 2000-07-24 2003-04-29 Motorola, Inc. Acoustic wave device and process for forming the same
US6493497B1 (en) 2000-09-26 2002-12-10 Motorola, Inc. Electro-optic structure and process for fabricating same
US6638838B1 (en) 2000-10-02 2003-10-28 Motorola, Inc. Semiconductor structure including a partially annealed layer and method of forming the same
JP2002134806A (ja) * 2000-10-19 2002-05-10 Canon Inc 圧電膜型アクチュエータおよび液体噴射ヘッドとその製造方法
US6559471B2 (en) 2000-12-08 2003-05-06 Motorola, Inc. Quantum well infrared photodetector and method for fabricating same
US6673646B2 (en) 2001-02-28 2004-01-06 Motorola, Inc. Growth of compound semiconductor structures on patterned oxide films and process for fabricating same
US6699770B2 (en) * 2001-03-01 2004-03-02 John Tarje Torvik Method of making a hybride substrate having a thin silicon carbide membrane layer
US6709989B2 (en) 2001-06-21 2004-03-23 Motorola, Inc. Method for fabricating a semiconductor structure including a metal oxide interface with silicon
US6531740B2 (en) 2001-07-17 2003-03-11 Motorola, Inc. Integrated impedance matching and stability network
US6646293B2 (en) 2001-07-18 2003-11-11 Motorola, Inc. Structure for fabricating high electron mobility transistors utilizing the formation of complaint substrates
US6693298B2 (en) 2001-07-20 2004-02-17 Motorola, Inc. Structure and method for fabricating epitaxial semiconductor on insulator (SOI) structures and devices utilizing the formation of a compliant substrate for materials used to form same
US6667196B2 (en) 2001-07-25 2003-12-23 Motorola, Inc. Method for real-time monitoring and controlling perovskite oxide film growth and semiconductor structure formed using the method
US6589856B2 (en) 2001-08-06 2003-07-08 Motorola, Inc. Method and apparatus for controlling anti-phase domains in semiconductor structures and devices
US6639249B2 (en) 2001-08-06 2003-10-28 Motorola, Inc. Structure and method for fabrication for a solid-state lighting device
US6673667B2 (en) 2001-08-15 2004-01-06 Motorola, Inc. Method for manufacturing a substantially integral monolithic apparatus including a plurality of semiconductor materials
DE10156406A1 (de) * 2001-11-16 2003-06-05 Bosch Gmbh Robert Verfahren zur Herstellung von Verformungssensoren mit einem Dehnungsmessstreifen sowie zur Herstellung von Dehnungsmessstreifen und Verformungssensoren sowie Dehnungsmessstreifen
JP4110390B2 (ja) * 2002-03-19 2008-07-02 セイコーエプソン株式会社 半導体装置の製造方法
JP2004319538A (ja) * 2003-04-10 2004-11-11 Seiko Epson Corp 半導体装置の製造方法、集積回路、電子光学装置及び電子機器
JP4488702B2 (ja) * 2003-07-30 2010-06-23 株式会社沖データ 半導体装置の製造方法
US6913985B2 (en) * 2003-06-20 2005-07-05 Oki Data Corporation Method of manufacturing a semiconductor device
FR2857155B1 (fr) * 2003-07-01 2005-10-21 St Microelectronics Sa Procede de fabrication de couches contraintes de silicium ou d'un alliage de silicium-germanium
JP4380264B2 (ja) * 2003-08-25 2009-12-09 カシオ計算機株式会社 接合基板及び基板の接合方法
US7067387B2 (en) * 2003-08-28 2006-06-27 Taiwan Semiconductor Manufacturing Company Method of manufacturing dielectric isolated silicon structure
JP4326889B2 (ja) * 2003-09-11 2009-09-09 株式会社沖データ 半導体装置、ｌｅｄプリントヘッド、画像形成装置、及び半導体装置の製造方法
JP2005347301A (ja) * 2004-05-31 2005-12-15 Canon Inc 基板の作製方法
DE102004048626B3 (de) * 2004-10-06 2006-04-13 X-Fab Semiconductor Foundries Ag Oxidationsverfahren von Siliziumscheiben zur Reduzierung von mechanischen Spannungen
KR100608386B1 (ko) * 2005-06-30 2006-08-08 주식회사 하이닉스반도체 반도체 소자의 제조방법
US8334155B2 (en) * 2005-09-27 2012-12-18 Philips Lumileds Lighting Company Llc Substrate for growing a III-V light emitting device
WO2007047644A2 (en) * 2005-10-14 2007-04-26 The Regents Of The University Of California Method for microchannel surface modification
KR100736623B1 (ko) 2006-05-08 2007-07-09 엘지전자 주식회사 수직형 발광 소자 및 그 제조방법
WO2009084309A1 (ja) * 2007-12-27 2009-07-09 Sharp Kabushiki Kaisha 半導体装置の製造方法、および当該製造方法によって作製される半導体装置
WO2009084284A1 (ja) 2007-12-27 2009-07-09 Sharp Kabushiki Kaisha 半導体装置用の絶縁基板、半導体装置、及び、半導体装置の製造方法
TW201037436A (en) * 2009-04-10 2010-10-16 Au Optronics Corp Pixel unit and fabricating method thereof
FR2946457B1 (fr) * 2009-06-05 2012-03-09 St Microelectronics Sa Procede de formation d'un niveau d'un circuit integre par integration tridimensionnelle sequentielle.
JP5590837B2 (ja) * 2009-09-15 2014-09-17 キヤノン株式会社 機能性領域の移設方法
JP5454485B2 (ja) * 2011-02-09 2014-03-26 信越半導体株式会社 貼り合わせ基板の製造方法
JP5425122B2 (ja) * 2011-02-21 2014-02-26 キヤノン株式会社 薄膜半導体装置の製造方法
US8946052B2 (en) * 2012-09-26 2015-02-03 Sandia Corporation Processes for multi-layer devices utilizing layer transfer
US9949837B2 (en) 2013-03-07 2018-04-24 Howmedica Osteonics Corp. Partially porous bone implant keel
US9755015B1 (en) 2016-05-10 2017-09-05 Globalfoundries Inc. Air gaps formed by porous silicon removal
KR102204732B1 (ko) * 2019-11-11 2021-01-19 (주)더숨 Soi 기판 제조 방법

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA924026A (en) * 1970-10-05 1973-04-03 Tokyo Shibaura Electric Co. Method for manufacturing a semiconductor integrated circuit isolated by dielectric material
US3909332A (en) * 1973-06-04 1975-09-30 Gen Electric Bonding process for dielectric isolation of single crystal semiconductor structures
US3997381A (en) * 1975-01-10 1976-12-14 Intel Corporation Method of manufacture of an epitaxial semiconductor layer on an insulating substrate
US3962052A (en) * 1975-04-14 1976-06-08 International Business Machines Corporation Process for forming apertures in silicon bodies
US4198263A (en) * 1976-03-30 1980-04-15 Tokyo Shibaura Electric Co., Ltd. Mask for soft X-rays and method of manufacture
SE409553B (sv) * 1976-10-04 1979-08-27 Aga Ab Sett vid fraktionering av en gasblandning under utnyttjande av minst tva beddar
US4171242A (en) * 1976-12-17 1979-10-16 International Business Machines Corporation Neutral pH silicon etchant for etching silicon in the presence of phosphosilicate glass
NL7710164A (nl) * 1977-09-16 1979-03-20 Philips Nv Werkwijze ter behandeling van een eenkristal- lijn lichaam.
US4142925A (en) * 1978-04-13 1979-03-06 The United States Of America As Represented By The Secretary Of The Army Method of making silicon-insulator-polysilicon infrared image device utilizing epitaxial deposition and selective etching
JPS5516464A (en) * 1978-07-21 1980-02-05 Nec Corp Method of forming wafer for semiconductor device
US4380865A (en) * 1981-11-13 1983-04-26 Bell Telephone Laboratories, Incorporated Method of forming dielectrically isolated silicon semiconductor materials utilizing porous silicon formation
JPH0658934B2 (ja) * 1985-02-08 1994-08-03 株式会社東芝 半導体装置の製造方法
NL8501773A (nl) * 1985-06-20 1987-01-16 Philips Nv Werkwijze voor het vervaardigen van halfgeleiderinrichtingen.
US4806996A (en) * 1986-04-10 1989-02-21 American Telephone And Telegraph Company, At&T Bell Laboratories Dislocation-free epitaxial layer on a lattice-mismatched porous or otherwise submicron patterned single crystal substrate
JPS63237408A (ja) * 1987-03-26 1988-10-03 Sumitomo Metal Mining Co Ltd 半導体デバイス用基板
US4771016A (en) * 1987-04-24 1988-09-13 Harris Corporation Using a rapid thermal process for manufacturing a wafer bonded soi semiconductor
US4897362A (en) * 1987-09-02 1990-01-30 Harris Corporation Double epitaxial method of fabricating semiconductor devices on bonded wafers
FR2620571B1 (fr) * 1987-09-11 1990-01-12 France Etat Procede de fabrication d'une structure de silicium sur isolant
JP2685819B2 (ja) * 1988-03-31 1997-12-03 株式会社東芝 誘電体分離半導体基板とその製造方法
US4939101A (en) * 1988-09-06 1990-07-03 General Electric Company Method of making direct bonded wafers having a void free interface
US5204282A (en) * 1988-09-30 1993-04-20 Nippon Soken, Inc. Semiconductor circuit structure and method for making the same
US4962051A (en) * 1988-11-18 1990-10-09 Motorola, Inc. Method of forming a defect-free semiconductor layer on insulator
US4891329A (en) * 1988-11-29 1990-01-02 University Of North Carolina Method of forming a nonsilicon semiconductor on insulator structure
JPH02252265A (ja) * 1989-03-27 1990-10-11 Sony Corp 半導体基板の製法
JPH02267949A (ja) * 1989-04-07 1990-11-01 Sony Corp 半導体基板の製造方法
JPH03109731A (ja) * 1989-09-25 1991-05-09 Seiko Instr Inc 半導体基板の製造方法
US5013681A (en) * 1989-09-29 1991-05-07 The United States Of America As Represented By The Secretary Of The Navy Method of producing a thin silicon-on-insulator layer
GB8927709D0 (en) * 1989-12-07 1990-02-07 Secretary Of The State For Def Silicon quantum wires
JP3253099B2 (ja) * 1990-03-27 2002-02-04 キヤノン株式会社 半導体基板の作製方法
JP2850502B2 (ja) * 1990-07-20 1999-01-27 富士通株式会社 Ｓｏｉ基板の製造方法
EP0688048A3 (de) * 1990-08-03 1996-02-28 Canon Kk Halbleitersubstrat mit SOI Struktur
US5091330A (en) * 1990-12-28 1992-02-25 Motorola, Inc. Method of fabricating a dielectric isolated area
EP0499488B9 (de) * 1991-02-15 2004-01-28 Canon Kabushiki Kaisha Ätzlösung für das Ätzen von porösem Silizium, Ätzmethode unter Verwendung der Ätzlösung und Verfahren zur Vorbereitung einer Halbleiteranordnung unter Verwendung der Ätzlösung
US5110748A (en) * 1991-03-28 1992-05-05 Honeywell Inc. Method for fabricating high mobility thin film transistors as integrated drivers for active matrix display

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JPH05275664A (ja) 1993-10-22
DE69233314T2 (de) 2005-03-24
JP3112126B2 (ja) 2000-11-27
US5466631A (en) 1995-11-14
EP0536790A3 (de) 1995-03-01
EP0536790A2 (de) 1993-04-14
EP0536790B1 (de) 2004-03-03

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