DE69229365T2 - Verfahren und Anordnung zur kostenbezogenen heuristischen Befehlsreihenfolgeplanung - Google Patents

Verfahren und Anordnung zur kostenbezogenen heuristischen Befehlsreihenfolgeplanung

Info

Publication number
DE69229365T2
DE69229365T2 DE69229365T DE69229365T DE69229365T2 DE 69229365 T2 DE69229365 T2 DE 69229365T2 DE 69229365 T DE69229365 T DE 69229365T DE 69229365 T DE69229365 T DE 69229365T DE 69229365 T2 DE69229365 T2 DE 69229365T2
Authority
DE
Germany
Prior art keywords
arrangement
cost
command sequence
sequence planning
related heuristic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69229365T
Other languages
English (en)
Other versions
DE69229365D1 (de
Inventor
Gregory Tarsy
Michael J Woodard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of DE69229365D1 publication Critical patent/DE69229365D1/de
Publication of DE69229365T2 publication Critical patent/DE69229365T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/445—Exploiting fine grain parallelism, i.e. parallelism at instruction level
DE69229365T 1991-02-27 1992-02-18 Verfahren und Anordnung zur kostenbezogenen heuristischen Befehlsreihenfolgeplanung Expired - Fee Related DE69229365T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/661,674 US5202993A (en) 1991-02-27 1991-02-27 Method and apparatus for cost-based heuristic instruction scheduling

Publications (2)

Publication Number Publication Date
DE69229365D1 DE69229365D1 (de) 1999-07-15
DE69229365T2 true DE69229365T2 (de) 2000-04-27

Family

ID=24654616

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69229365T Expired - Fee Related DE69229365T2 (de) 1991-02-27 1992-02-18 Verfahren und Anordnung zur kostenbezogenen heuristischen Befehlsreihenfolgeplanung

Country Status (5)

Country Link
US (1) US5202993A (de)
EP (1) EP0501653B1 (de)
JP (1) JP2720128B2 (de)
KR (1) KR970005456B1 (de)
DE (1) DE69229365T2 (de)

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US5889996A (en) * 1996-12-16 1999-03-30 Novell Inc. Accelerator for interpretive environments
US5983310A (en) 1997-02-13 1999-11-09 Novell, Inc. Pin management of accelerator for interpretive environments
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US6836839B2 (en) 2001-03-22 2004-12-28 Quicksilver Technology, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US7752419B1 (en) 2001-03-22 2010-07-06 Qst Holdings, Llc Method and system for managing hardware resources to implement system functions using an adaptive computing architecture
US7489779B2 (en) 2001-03-22 2009-02-10 Qstholdings, Llc Hardware implementation of the secure hash standard
US7400668B2 (en) 2001-03-22 2008-07-15 Qst Holdings, Llc Method and system for implementing a system acquisition function for use with a communication device
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US7962716B2 (en) 2001-03-22 2011-06-14 Qst Holdings, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US6577678B2 (en) 2001-05-08 2003-06-10 Quicksilver Technology Method and system for reconfigurable channel coding
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US6986021B2 (en) 2001-11-30 2006-01-10 Quick Silver Technology, Inc. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements
US8412915B2 (en) 2001-11-30 2013-04-02 Altera Corporation Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements
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US7215701B2 (en) 2001-12-12 2007-05-08 Sharad Sambhwani Low I/O bandwidth method and system for implementing detection and identification of scrambling codes
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KR101814221B1 (ko) 2010-01-21 2018-01-02 스비랄 인크 스트림 기반 계산을 구현하기 위한 범용 다중 코어 시스템을 위한 방법 및 장치
CN102063288A (zh) * 2011-01-07 2011-05-18 四川九洲电器集团有限责任公司 一种面向dsp芯片的指令调度方法
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JPH04252336A (ja) * 1991-01-29 1992-09-08 Fujitsu Ltd プログラム最適化処理装置

Also Published As

Publication number Publication date
DE69229365D1 (de) 1999-07-15
US5202993A (en) 1993-04-13
EP0501653B1 (de) 1999-06-09
KR970005456B1 (ko) 1997-04-16
EP0501653A2 (de) 1992-09-02
JPH06208462A (ja) 1994-07-26
JP2720128B2 (ja) 1998-02-25
EP0501653A3 (en) 1993-05-26
KR920016940A (ko) 1992-09-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee