DE69223461D1 - Konfigurable Selbstprüfung für integrierte RAMs - Google Patents

Konfigurable Selbstprüfung für integrierte RAMs

Info

Publication number
DE69223461D1
DE69223461D1 DE69223461T DE69223461T DE69223461D1 DE 69223461 D1 DE69223461 D1 DE 69223461D1 DE 69223461 T DE69223461 T DE 69223461T DE 69223461 T DE69223461 T DE 69223461T DE 69223461 D1 DE69223461 D1 DE 69223461D1
Authority
DE
Germany
Prior art keywords
test
ram
address
control circuit
configurable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69223461T
Other languages
English (en)
Other versions
DE69223461T2 (de
Inventor
Harlan Talley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of DE69223461D1 publication Critical patent/DE69223461D1/de
Application granted granted Critical
Publication of DE69223461T2 publication Critical patent/DE69223461T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/20—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits using counters or linear-feedback shift registers [LFSR]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
DE69223461T 1991-07-18 1992-07-15 Konfigurable Selbstprüfung für integrierte RAMs Expired - Fee Related DE69223461T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/732,538 US5301156A (en) 1991-07-18 1991-07-18 Configurable self-test for embedded RAMs

Publications (2)

Publication Number Publication Date
DE69223461D1 true DE69223461D1 (de) 1998-01-22
DE69223461T2 DE69223461T2 (de) 1998-05-14

Family

ID=24943918

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69223461T Expired - Fee Related DE69223461T2 (de) 1991-07-18 1992-07-15 Konfigurable Selbstprüfung für integrierte RAMs

Country Status (4)

Country Link
US (1) US5301156A (de)
EP (1) EP0523973B1 (de)
JP (1) JP3262593B2 (de)
DE (1) DE69223461T2 (de)

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US5428623A (en) * 1993-07-01 1995-06-27 Tandem Computers Incorporated Scannable interface to nonscannable microprocessor
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US5918003A (en) * 1995-06-07 1999-06-29 International Business Machines Corporation Enhanced built-in self-test circuit and method
US5790564A (en) * 1995-06-07 1998-08-04 International Business Machines Corporation Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor
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US5867507A (en) * 1995-12-12 1999-02-02 International Business Machines Corporation Testable programmable gate array and associated LSSD/deterministic test methodology
US5721863A (en) * 1996-01-29 1998-02-24 International Business Machines Corporation Method and structure for accessing semi-associative cache memory using multiple memories to store different components of the address
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US5815510A (en) * 1996-03-28 1998-09-29 Cypress Semiconductor Corp. Serial programming of instruction codes in different numbers of clock cycles
US5835503A (en) * 1996-03-28 1998-11-10 Cypress Semiconductor Corp. Method and apparatus for serially programming a programmable logic device
US5768288A (en) * 1996-03-28 1998-06-16 Cypress Semiconductor Corp. Method and apparatus for programming a programmable logic device having verify logic for comparing verify data read from a memory location with program data
US5870410A (en) * 1996-04-29 1999-02-09 Altera Corporation Diagnostic interface system for programmable logic system development
US5825785A (en) * 1996-05-24 1998-10-20 Internaitonal Business Machines Corporation Serial input shift register built-in self test circuit for embedded circuits
US5796745A (en) * 1996-07-19 1998-08-18 International Business Machines Corporation Memory array built-in self test circuit for testing multi-port memory arrays
US5668815A (en) * 1996-08-14 1997-09-16 Advanced Micro Devices, Inc. Method for testing integrated memory using an integrated DMA controller
US5936976A (en) * 1997-07-25 1999-08-10 Vlsi Technology, Inc. Selecting a test data input bus to supply test data to logical blocks within an integrated circuit
US6061811A (en) * 1997-10-31 2000-05-09 Texas Instruments Incorporated Circuits, systems, and methods for external evaluation of microprocessor built-in self-test
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US6001662A (en) * 1997-12-02 1999-12-14 International Business Machines Corporation Method and system for providing a reusable configurable self-test controller for manufactured integrated circuits
US6173425B1 (en) 1998-04-15 2001-01-09 Integrated Device Technology, Inc. Methods of testing integrated circuits to include data traversal path identification information and related status information in test data streams
KR100308621B1 (ko) * 1998-11-19 2001-12-17 윤종용 반도체 메모리 장치를 위한 프로그램 가능한 내장 자기 테스트 시스템
US6363501B1 (en) * 1998-12-10 2002-03-26 Advanced Micro Devices, Inc. Method and apparatus for saving and loading peripheral device states of a microcontroller via a scan path
US6954879B1 (en) 1998-12-10 2005-10-11 Advanced Micro Devices, Inc. Method and apparatus for communicating configuration data for a peripheral device of a microcontroller via a scan path
US6701484B1 (en) * 2000-08-11 2004-03-02 International Business Machines Corporation Register file with delayed parity check
US7240254B2 (en) * 2000-09-21 2007-07-03 Inapac Technology, Inc Multiple power levels for a chip within a multi-chip semiconductor package
US6812726B1 (en) * 2002-11-27 2004-11-02 Inapac Technology, Inc. Entering test mode and accessing of a packaged semiconductor device
US7444575B2 (en) * 2000-09-21 2008-10-28 Inapac Technology, Inc. Architecture and method for testing of an integrated circuit device
DE10052211A1 (de) * 2000-10-20 2002-05-08 Infineon Technologies Ag Integrierte Schaltung mit Testbetriebsart und Verfahren zum Testen einer Vielzahl solcher integrierter Schaltungen
US6678707B1 (en) 2000-10-30 2004-01-13 Hewlett-Packard Development Company, L.P. Generation of cryptographically strong random numbers using MISRs
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US6766468B2 (en) 2001-07-11 2004-07-20 International Business Machines Corporation Memory BIST and repair
US8286046B2 (en) 2001-09-28 2012-10-09 Rambus Inc. Integrated circuit testing module including signal shaping interface
US8166361B2 (en) * 2001-09-28 2012-04-24 Rambus Inc. Integrated circuit testing module configured for set-up and hold time testing
US7313740B2 (en) * 2002-07-25 2007-12-25 Inapac Technology, Inc. Internally generating patterns for testing in an integrated circuit device
US8001439B2 (en) * 2001-09-28 2011-08-16 Rambus Inc. Integrated circuit testing module including signal shaping interface
US7055075B2 (en) * 2001-12-05 2006-05-30 Avago Techologies General Ip Pte. Ltd. Apparatus for random access memory array self-test
DE10219916A1 (de) * 2002-05-03 2003-12-04 Infineon Technologies Ag Testanordnung mit Testautomat und integriertem Schaltkreis sowie Verfahren zur Ermittlung des Zeitverhaltens eines integrierten Schaltkreises
DE10232178B3 (de) * 2002-07-16 2004-02-26 Infineon Technologies Ag Anordnung und Verfahren zum Überprüfen eines Adress-Generators
US7073100B2 (en) 2002-11-11 2006-07-04 International Business Machines Corporation Method for testing embedded DRAM arrays
US8063650B2 (en) 2002-11-27 2011-11-22 Rambus Inc. Testing fuse configurations in semiconductor devices
US6959256B2 (en) * 2003-05-16 2005-10-25 Analog Devices, Inc. Universally accessible fully programmable memory built-in self-test (MBIST) system and method
US7131043B1 (en) * 2003-09-25 2006-10-31 Altera Corporation Automatic testing for programmable networks of control signals
US7340660B2 (en) 2003-10-07 2008-03-04 International Business Machines Corporation Method and system for using statistical signatures for testing high-speed circuits
US7194670B2 (en) * 2004-02-13 2007-03-20 International Business Machines Corp. Command multiplier for built-in-self-test
US7519875B2 (en) * 2004-08-20 2009-04-14 Avago Technologies General Ip (Singapore) Pte. Ltd. Method and apparatus for enabling a user to determine whether a defective location in a memory device has been remapped to a redundant memory portion
US8621304B2 (en) * 2004-10-07 2013-12-31 Hewlett-Packard Development Company, L.P. Built-in self-test system and method for an integrated circuit
JP4622443B2 (ja) * 2004-10-15 2011-02-02 ソニー株式会社 半導体集積回路
US7917825B2 (en) * 2006-12-15 2011-03-29 Joo-Sang Lee Method and apparatus for selectively utilizing information within a semiconductor device
CN103680639B (zh) * 2013-11-29 2016-08-24 西安空间无线电技术研究所 一种随机存储器的周期性自检错恢复方法
CN104932954B (zh) * 2015-07-01 2017-10-24 西北工业大学 微小卫星fpga关键数据保护方法

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US4601034A (en) * 1984-03-30 1986-07-15 Texas Instruments Incorporated Method and apparatus for testing very large scale integrated memory circuits
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US4879690A (en) * 1987-09-07 1989-11-07 Mitsubishi Denki Kabushiki Kaisha Static random access memory with reduced soft error rate
JPH0820967B2 (ja) * 1987-09-25 1996-03-04 三菱電機株式会社 集積回路
US4918378A (en) * 1989-06-12 1990-04-17 Unisys Corporation Method and circuitry for enabling internal test operations in a VLSI chip
US5006787A (en) * 1989-06-12 1991-04-09 Unisys Corporation Self-testing circuitry for VLSI units

Also Published As

Publication number Publication date
EP0523973A2 (de) 1993-01-20
EP0523973B1 (de) 1997-12-10
DE69223461T2 (de) 1998-05-14
JPH05205499A (ja) 1993-08-13
US5301156A (en) 1994-04-05
EP0523973A3 (en) 1993-11-10
JP3262593B2 (ja) 2002-03-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: AGILENT TECHNOLOGIES, INC. (N.D.GES.D.STAATES DELA

8339 Ceased/non-payment of the annual fee