DE69125658D1 - Segmentierung von Spuren in FPGA Verdrahtungs-Kanälen - Google Patents

Segmentierung von Spuren in FPGA Verdrahtungs-Kanälen

Info

Publication number
DE69125658D1
DE69125658D1 DE69125658T DE69125658T DE69125658D1 DE 69125658 D1 DE69125658 D1 DE 69125658D1 DE 69125658 T DE69125658 T DE 69125658T DE 69125658 T DE69125658 T DE 69125658T DE 69125658 D1 DE69125658 D1 DE 69125658D1
Authority
DE
Germany
Prior art keywords
interior
channel
segments
tracks
track
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69125658T
Other languages
English (en)
Other versions
DE69125658T2 (de
Inventor
Jonathan W Greene
Sinan Kaptanoglu
Gamal Abbas A El
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microsemi SoC Corp
Original Assignee
Actel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Actel Corp filed Critical Actel Corp
Publication of DE69125658D1 publication Critical patent/DE69125658D1/de
Application granted granted Critical
Publication of DE69125658T2 publication Critical patent/DE69125658T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
DE69125658T 1990-06-22 1991-05-31 Segmentierung von Spuren in FPGA Verdrahtungs-Kanälen Expired - Fee Related DE69125658T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/542,722 US5073729A (en) 1990-06-22 1990-06-22 Segmented routing architecture

Publications (2)

Publication Number Publication Date
DE69125658D1 true DE69125658D1 (de) 1997-05-22
DE69125658T2 DE69125658T2 (de) 1997-07-31

Family

ID=24165009

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69125658T Expired - Fee Related DE69125658T2 (de) 1990-06-22 1991-05-31 Segmentierung von Spuren in FPGA Verdrahtungs-Kanälen

Country Status (5)

Country Link
US (1) US5073729A (de)
EP (1) EP0463746B1 (de)
JP (1) JP3278443B2 (de)
AT (1) ATE151898T1 (de)
DE (1) DE69125658T2 (de)

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US6759870B2 (en) 1991-09-03 2004-07-06 Altera Corporation Programmable logic array integrated circuits
US20020130681A1 (en) * 1991-09-03 2002-09-19 Cliff Richard G. Programmable logic array integrated circuits
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EP0650194B1 (de) * 1993-10-21 1999-11-10 Advanced Micro Devices, Inc. Dynamischer Bus von hoher Dichte
US5469078A (en) * 1994-01-06 1995-11-21 Texas Instruments Incorporated Programmable logic device routing architecture
US5689195A (en) 1995-05-17 1997-11-18 Altera Corporation Programmable logic array integrated circuit devices
US5424655A (en) * 1994-05-20 1995-06-13 Quicklogic Corporation Programmable application specific integrated circuit employing antifuses and methods therefor
US5495181A (en) * 1994-12-01 1996-02-27 Quicklogic Corporation Integrated circuit facilitating simultaneous programming of multiple antifuses
US5552720A (en) * 1994-12-01 1996-09-03 Quicklogic Corporation Method for simultaneous programming of multiple antifuses
US5581199A (en) * 1995-01-04 1996-12-03 Xilinx, Inc. Interconnect architecture for field programmable gate array using variable length conductors
US5543732A (en) * 1995-05-17 1996-08-06 Altera Corporation Programmable logic array devices with interconnect lines of various lengths
US5900743A (en) 1995-05-17 1999-05-04 Altera Corporation Programmable logic array devices with interconnect lines of various lengths
US5963049A (en) 1995-05-17 1999-10-05 Altera Corporation Programmable logic array integrated circuit architectures
US5592106A (en) * 1995-05-17 1997-01-07 Altera Corporation Programmable logic array integrated circuits with interconnection conductors of overlapping extent
US5909126A (en) 1995-05-17 1999-06-01 Altera Corporation Programmable logic array integrated circuit devices with interleaved logic array blocks
US5625301A (en) * 1995-05-18 1997-04-29 Actel Corporation Flexible FPGA input/output architecture
US5631578A (en) * 1995-06-02 1997-05-20 International Business Machines Corporation Programmable array interconnect network
US5646546A (en) * 1995-06-02 1997-07-08 International Business Machines Corporation Programmable logic cell having configurable gates and multiplexers
US5671432A (en) * 1995-06-02 1997-09-23 International Business Machines Corporation Programmable array I/O-routing resource
US5652529A (en) * 1995-06-02 1997-07-29 International Business Machines Corporation Programmable array clock/reset resource
US5744980A (en) * 1996-02-16 1998-04-28 Actel Corporation Flexible, high-performance static RAM architecture for field-programmable gate arrays
US5835998A (en) * 1996-04-04 1998-11-10 Altera Corporation Logic cell for programmable logic devices
US5781032A (en) * 1996-09-09 1998-07-14 International Business Machines Corporation Programmable inverter circuit used in a programmable logic cell
US5880597A (en) * 1996-09-18 1999-03-09 Altera Corporation Interleaved interconnect for programmable logic array devices
US6300794B1 (en) 1996-10-10 2001-10-09 Altera Corporation Programmable logic device with hierarchical interconnection resources
US5858817A (en) * 1996-10-10 1999-01-12 Lockheed Martin Corporation Process to personalize master slice wafers and fabricate high density VLSI components with a single masking step
US5999016A (en) * 1996-10-10 1999-12-07 Altera Corporation Architectures for programmable logic devices
US5977793A (en) * 1996-10-10 1999-11-02 Altera Corporation Programmable logic device with hierarchical interconnection resources
US5999015A (en) * 1997-02-20 1999-12-07 Altera Corporation Logic region resources for programmable logic devices
US6127844A (en) 1997-02-20 2000-10-03 Altera Corporation PCI-compatible programmable logic devices
US5982195A (en) * 1997-02-20 1999-11-09 Altera Corporation Programmable logic device architectures
US7148722B1 (en) 1997-02-20 2006-12-12 Altera Corporation PCI-compatible programmable logic devices
US5920202A (en) * 1997-02-26 1999-07-06 Xilinx, Inc. Configurable logic element with ability to evaluate five and six input functions
US5889411A (en) * 1997-02-26 1999-03-30 Xilinx, Inc. FPGA having logic element carry chains capable of generating wide XOR functions
US5914616A (en) * 1997-02-26 1999-06-22 Xilinx, Inc. FPGA repeatable interconnect structure with hierarchical interconnect lines
US6201410B1 (en) 1997-02-26 2001-03-13 Xilinx, Inc. Wide logic gate implemented in an FPGA configurable logic element
US6204689B1 (en) 1997-02-26 2001-03-20 Xilinx, Inc. Input/output interconnect circuit for FPGAs
US5963050A (en) 1997-02-26 1999-10-05 Xilinx, Inc. Configurable logic element with fast feedback paths
US5942913A (en) * 1997-03-20 1999-08-24 Xilinx, Inc. FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines
US6396303B1 (en) 1997-02-26 2002-05-28 Xilinx, Inc. Expandable interconnect structure for FPGAS
US6184710B1 (en) 1997-03-20 2001-02-06 Altera Corporation Programmable logic array devices with enhanced interconnectivity between adjacent logic regions
US6107825A (en) * 1997-10-16 2000-08-22 Altera Corporation Input/output circuitry for programmable logic devices
US6121790A (en) * 1997-10-16 2000-09-19 Altera Corporation Programmable logic device with enhanced multiplexing capabilities in interconnect resources
US6084427A (en) 1998-05-19 2000-07-04 Altera Corporation Programmable logic devices with enhanced multiplexing capabilities
US6107824A (en) * 1997-10-16 2000-08-22 Altera Corporation Circuitry and methods for internal interconnection of programmable logic devices
US6242767B1 (en) 1997-11-10 2001-06-05 Lightspeed Semiconductor Corp. Asic routing architecture
US6185724B1 (en) 1997-12-02 2001-02-06 Xilinx, Inc. Template-based simulated annealing move-set that improves FPGA architectural feature utilization
US6069490A (en) * 1997-12-02 2000-05-30 Xilinx, Inc. Routing architecture using a direct connect routing mesh
US6084429A (en) * 1998-04-24 2000-07-04 Xilinx, Inc. PLD having a window pane architecture with segmented and staggered interconnect wiring between logic block arrays
US7389487B1 (en) 1998-04-28 2008-06-17 Actel Corporation Dedicated interface architecture for a hybrid integrated circuit
EP0978944B1 (de) * 1998-07-06 2002-01-02 Hewlett-Packard Company, A Delaware Corporation Verdrahtung von Zellen in logischen Feldern
US6169416B1 (en) 1998-09-01 2001-01-02 Quicklogic Corporation Programming architecture for field programmable gate array
US6215326B1 (en) 1998-11-18 2001-04-10 Altera Corporation Programmable logic device architecture with super-regions having logic regions and a memory region
US6507216B1 (en) 1998-11-18 2003-01-14 Altera Corporation Efficient arrangement of interconnection resources on programmable logic devices
US6407576B1 (en) 1999-03-04 2002-06-18 Altera Corporation Interconnection and input/output resources for programmable logic integrated circuit devices
US6590419B1 (en) * 1999-10-12 2003-07-08 Altera Toronto Co. Heterogeneous interconnection architecture for programmable logic devices
US6613611B1 (en) 2000-12-22 2003-09-02 Lightspeed Semiconductor Corporation ASIC routing architecture with variable number of custom masks
US6720796B1 (en) 2001-05-06 2004-04-13 Altera Corporation Multiple size memories in a programmable logic device
US6885043B2 (en) * 2002-01-18 2005-04-26 Lightspeed Semiconductor Corporation ASIC routing architecture
US7135888B1 (en) * 2004-07-22 2006-11-14 Altera Corporation Programmable routing structures providing shorter timing delays for input/output signals
WO2012015403A1 (en) 2010-07-29 2012-02-02 Ford Global Technologies, Llc Systems and methods for scheduling driver interface tasks based on driver workload
US9153531B1 (en) 2014-02-27 2015-10-06 Altera Corporation Methods and apparatus for reducing crosstalk and twist region height in routing wires
US9564394B1 (en) 2014-11-18 2017-02-07 Altera Corporation Methods and apparatus for reducing spatial overlap between routing wires

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FR2443185A1 (fr) * 1978-11-30 1980-06-27 Ibm Topologie de circuits integres semi-conducteurs et procede pour l'obtention de cette topologie
JPS58137229A (ja) * 1982-02-09 1983-08-15 Nippon Telegr & Teleph Corp <Ntt> 半導体装置
US4568961A (en) * 1983-03-11 1986-02-04 Rca Corporation Variable geometry automated universal array
NL8401847A (nl) * 1984-06-12 1986-01-02 Philips Nv Niveauverschuivingsschakeling.
JPS6341048A (ja) * 1986-08-06 1988-02-22 Mitsubishi Electric Corp 標準セル方式大規模集積回路
US4758745B1 (en) * 1986-09-19 1994-11-15 Actel Corp User programmable integrated circuit interconnect architecture and test method
US4786904A (en) * 1986-12-15 1988-11-22 Zoran Corporation Electronically programmable gate array having programmable interconnect lines
JPH0254576A (ja) * 1988-08-18 1990-02-23 Mitsubishi Electric Corp ゲートアレイ
US4937475B1 (en) * 1988-09-19 1994-03-29 Massachusetts Inst Technology Laser programmable integrated circuit
JP2723926B2 (ja) * 1988-09-20 1998-03-09 川崎製鉄株式会社 プログラマブル・ロジツク・デバイス
IT1225638B (it) * 1988-12-28 1990-11-22 Sgs Thomson Microelectronics Dispositivo logico integrato come una rete di maglie di memorie distribuite

Also Published As

Publication number Publication date
JPH0529458A (ja) 1993-02-05
EP0463746B1 (de) 1997-04-16
EP0463746A3 (en) 1993-06-16
JP3278443B2 (ja) 2002-04-30
ATE151898T1 (de) 1997-05-15
EP0463746A2 (de) 1992-01-02
US5073729A (en) 1991-12-17
DE69125658T2 (de) 1997-07-31

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee