DE69123324D1 - Halbleiterspeicheranordnung mit verriegelten Zeilenleitungszwischenverstärkern, angesteuert durch ein Speisespannungs Einschalt-Rücksetzsignal - Google Patents

Halbleiterspeicheranordnung mit verriegelten Zeilenleitungszwischenverstärkern, angesteuert durch ein Speisespannungs Einschalt-Rücksetzsignal

Info

Publication number
DE69123324D1
DE69123324D1 DE69123324T DE69123324T DE69123324D1 DE 69123324 D1 DE69123324 D1 DE 69123324D1 DE 69123324 T DE69123324 T DE 69123324T DE 69123324 T DE69123324 T DE 69123324T DE 69123324 D1 DE69123324 D1 DE 69123324D1
Authority
DE
Germany
Prior art keywords
driven
power
memory device
semiconductor memory
reset signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69123324T
Other languages
English (en)
Other versions
DE69123324T2 (de
Inventor
William Carl Slemmer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Publication of DE69123324D1 publication Critical patent/DE69123324D1/de
Application granted granted Critical
Publication of DE69123324T2 publication Critical patent/DE69123324T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
DE69123324T 1990-09-26 1991-09-23 Halbleiterspeicheranordnung mit verriegelten Zeilenleitungszwischenverstärkern, angesteuert durch ein Speisespannungs Einschalt-Rücksetzsignal Expired - Fee Related DE69123324T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/588,609 US5121358A (en) 1990-09-26 1990-09-26 Semiconductor memory with power-on reset controlled latched row line repeaters

Publications (2)

Publication Number Publication Date
DE69123324D1 true DE69123324D1 (de) 1997-01-09
DE69123324T2 DE69123324T2 (de) 1997-03-20

Family

ID=24354570

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69123324T Expired - Fee Related DE69123324T2 (de) 1990-09-26 1991-09-23 Halbleiterspeicheranordnung mit verriegelten Zeilenleitungszwischenverstärkern, angesteuert durch ein Speisespannungs Einschalt-Rücksetzsignal

Country Status (5)

Country Link
US (2) US5121358A (de)
EP (1) EP0478253B1 (de)
JP (1) JPH0652685A (de)
KR (1) KR920006982A (de)
DE (1) DE69123324T2 (de)

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JP2527835B2 (ja) * 1990-07-31 1996-08-28 三菱電機株式会社 半導体装置
US5163025A (en) * 1990-11-16 1992-11-10 Zenith Electronics Corporation Protection circuit for non-volatile memory
US5251178A (en) * 1991-03-06 1993-10-05 Childers Jimmie D Low-power integrated circuit memory
US5285419A (en) * 1991-12-17 1994-02-08 Sgs-Thomson Microelectronics, Inc. Read/write memory with improved test mode data compare
US5424986A (en) * 1991-12-19 1995-06-13 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with power-on reset control of disabled rows
US5479172A (en) * 1994-02-10 1995-12-26 Racom Systems, Inc. Power supply and power enable circuit for an RF/ID transponder
JPH07294961A (ja) * 1994-04-22 1995-11-10 Semiconductor Energy Lab Co Ltd アクティブマトリクス型表示装置の駆動回路および設計方法
US5587866A (en) * 1995-07-27 1996-12-24 Microchip Technology Incorporated Power-on reset circuit
JP2800730B2 (ja) * 1995-08-17 1998-09-21 日本電気株式会社 半導体記憶装置
US5748554A (en) * 1996-12-20 1998-05-05 Rambus, Inc. Memory and method for sensing sub-groups of memory elements
US5892703A (en) * 1997-06-13 1999-04-06 Micron Technology, Inc, Memory architecture and decoder addressing
US5835441A (en) 1997-08-21 1998-11-10 Micron Technology, Inc. Column select latch for SDRAM
US5940345A (en) * 1997-12-12 1999-08-17 Cypress Semiconductor Corp. Combinational logic feedback circuit to ensure correct power-on-reset of a four-bit synchronous shift register
US6075742A (en) * 1997-12-31 2000-06-13 Stmicroelectronics, Inc. Integrated circuit for switching from power supply to battery, integrated latch lock, and associated method for same
US6313663B1 (en) * 1998-03-09 2001-11-06 Infineon Technologies Ag Full swing voltage input/full swing output bi-directional repeaters for high resistance or high capacitance bi-directional signal lines and methods therefor
US6307397B1 (en) * 1998-03-09 2001-10-23 Infineontechnologies Ag Reduced voltage input/reduced voltage output repeaters for high capacitance signal lines and methods therefor
KR100380347B1 (ko) * 2000-11-21 2003-04-11 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 데이터 리드 방법
US7500075B1 (en) 2001-04-17 2009-03-03 Rambus Inc. Mechanism for enabling full data bus utilization without increasing data granularity
US6825841B2 (en) * 2001-09-07 2004-11-30 Rambus Inc. Granularity memory column access
JP4974202B2 (ja) * 2001-09-19 2012-07-11 ルネサスエレクトロニクス株式会社 半導体集積回路
US6690198B2 (en) * 2002-04-02 2004-02-10 Infineon Technologies Ag Repeater with reduced power consumption
US6816994B2 (en) * 2002-06-21 2004-11-09 Micron Technology, Inc. Low power buffer implementation
US7046551B2 (en) * 2003-03-25 2006-05-16 Mosel Vitelic, Inc. Nonvolatile memories with asymmetric transistors, nonvolatile memories with high voltage lines extending in the column direction, and nonvolatile memories with decoding circuits sharing a common area
US6870398B2 (en) * 2003-04-24 2005-03-22 Ami Semiconductor, Inc. Distributed memory and logic circuits
US6930914B2 (en) * 2003-04-29 2005-08-16 Hewlett-Packard Development Company, L.P. Methods for isolating memory elements within an array
US7016251B2 (en) * 2004-07-29 2006-03-21 International Business Machines Corporation Method and apparatus for initializing SRAM device during power-up
US8190808B2 (en) * 2004-08-17 2012-05-29 Rambus Inc. Memory device having staggered memory operations
US7280428B2 (en) 2004-09-30 2007-10-09 Rambus Inc. Multi-column addressing mode memory system including an integrated circuit memory device
KR100613448B1 (ko) * 2004-10-07 2006-08-21 주식회사 하이닉스반도체 데이터 가속회로 및 이를 이용한 데이터 전송회로
US8595459B2 (en) 2004-11-29 2013-11-26 Rambus Inc. Micro-threaded memory
US20070260841A1 (en) 2006-05-02 2007-11-08 Hampel Craig E Memory module with reduced access granularity
US9268719B2 (en) 2011-08-05 2016-02-23 Rambus Inc. Memory signal buffers and modules supporting variable access granularity
US9858144B2 (en) 2015-08-20 2018-01-02 National Technology & Engineering Solutions Of Sandia, Llc Processor-in-memory-and-storage architecture
US9978435B1 (en) * 2017-01-25 2018-05-22 Winbond Electronics Corporation Memory device and operation methods thereof

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US4104734A (en) * 1977-06-30 1978-08-01 Fairchild Camera And Instrument Corporation Low voltage data retention bias circuitry for volatile memories
JPS5567993A (en) * 1978-11-14 1980-05-22 Fujitsu Ltd Semiconductor memory unit
JPS56101687A (en) * 1979-12-27 1981-08-14 Fujitsu Ltd Semiconductor memory circuit
JPS5894187A (ja) * 1981-11-28 1983-06-04 Mitsubishi Electric Corp 半導体記憶装置
US4446381A (en) * 1982-04-22 1984-05-01 Zilog, Inc. Circuit and technique for initializing the state of bistable elements in an integrated electronic circuit
JPS58193501A (ja) * 1982-05-07 1983-11-11 Daikin Ind Ltd 光学材料
JPS5940393A (ja) * 1982-08-31 1984-03-06 Nec Corp メモリ回路
US4654849B1 (en) * 1984-08-31 1999-06-22 Texas Instruments Inc High speed concurrent testing of dynamic read/write memory array
JPS61104394A (ja) * 1984-10-22 1986-05-22 Mitsubishi Electric Corp 半導体記憶装置
JPS62170094A (ja) * 1986-01-21 1987-07-27 Mitsubishi Electric Corp 半導体記憶回路
IT1204808B (it) * 1986-02-18 1989-03-10 Sgs Microelettronica Spa Circuito di reset all'accensione per reti logiche in tecnologia mos,particolarmente per periferiche di microprocessori
JPH0693616B2 (ja) * 1986-07-21 1994-11-16 沖電気工業株式会社 リセツト回路
US4789967A (en) * 1986-09-16 1988-12-06 Advanced Micro Devices, Inc. Random access memory device with block reset
JP2508697B2 (ja) * 1987-03-27 1996-06-19 日本電気株式会社 半導体集積回路
US5115146A (en) * 1990-08-17 1992-05-19 Sgs-Thomson Microelectronics, Inc. Power-on reset circuit for controlling test mode entry

Also Published As

Publication number Publication date
US5121358A (en) 1992-06-09
JPH0652685A (ja) 1994-02-25
EP0478253A3 (en) 1993-06-16
DE69123324T2 (de) 1997-03-20
US5526318A (en) 1996-06-11
EP0478253A2 (de) 1992-04-01
KR920006982A (ko) 1992-04-28
EP0478253B1 (de) 1996-11-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee