DE69113997D1 - Inkrementierende subtrahierschaltungen. - Google Patents

Inkrementierende subtrahierschaltungen.

Info

Publication number
DE69113997D1
DE69113997D1 DE69113997T DE69113997T DE69113997D1 DE 69113997 D1 DE69113997 D1 DE 69113997D1 DE 69113997 T DE69113997 T DE 69113997T DE 69113997 T DE69113997 T DE 69113997T DE 69113997 D1 DE69113997 D1 DE 69113997D1
Authority
DE
Germany
Prior art keywords
subtractors
incrementing
incrementing subtractors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69113997T
Other languages
English (en)
Other versions
DE69113997T2 (de
Inventor
Stewart Smith
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Semiconductors Inc
Original Assignee
VLSI Technology Inc
Philips Semiconductors Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by VLSI Technology Inc, Philips Semiconductors Inc filed Critical VLSI Technology Inc
Publication of DE69113997D1 publication Critical patent/DE69113997D1/de
Application granted granted Critical
Publication of DE69113997T2 publication Critical patent/DE69113997T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/5055—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination in which one operand is a constant, i.e. incrementers or decrementers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/504—Adding; Subtracting in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
DE69113997T 1990-04-05 1991-03-13 Inkrementierende subtrahierschaltungen. Expired - Fee Related DE69113997T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/505,283 US5105379A (en) 1990-04-05 1990-04-05 Incrementing subtractive circuits
PCT/EP1991/000466 WO1991015821A1 (en) 1990-04-05 1991-03-13 Incrementing subtractive circuits

Publications (2)

Publication Number Publication Date
DE69113997D1 true DE69113997D1 (de) 1995-11-23
DE69113997T2 DE69113997T2 (de) 1996-04-11

Family

ID=24009690

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69113997T Expired - Fee Related DE69113997T2 (de) 1990-04-05 1991-03-13 Inkrementierende subtrahierschaltungen.

Country Status (5)

Country Link
US (1) US5105379A (de)
EP (1) EP0523073B1 (de)
JP (1) JP2599857B2 (de)
DE (1) DE69113997T2 (de)
WO (1) WO1991015821A1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6473529B1 (en) 1999-11-03 2002-10-29 Neomagic Corp. Sum-of-absolute-difference calculator for motion estimation using inversion and carry compensation with full and half-adders

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2212952A5 (de) * 1972-12-29 1974-07-26 Cit Alcatel
US3816734A (en) * 1973-03-12 1974-06-11 Bell Telephone Labor Inc Apparatus and method for 2{40 s complement subtraction
US4218751A (en) * 1979-03-07 1980-08-19 International Business Machines Corporation Absolute difference generator for use in display systems

Also Published As

Publication number Publication date
DE69113997T2 (de) 1996-04-11
EP0523073B1 (de) 1995-10-18
US5105379A (en) 1992-04-14
EP0523073A1 (de) 1993-01-20
JPH05507373A (ja) 1993-10-21
JP2599857B2 (ja) 1997-04-16
WO1991015821A1 (en) 1991-10-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee