DE69025232D1 - Verfahren zur Aufrechterhaltung der Cache-Speicherkohärenz in einem Mehrrechnersystem - Google Patents

Verfahren zur Aufrechterhaltung der Cache-Speicherkohärenz in einem Mehrrechnersystem

Info

Publication number
DE69025232D1
DE69025232D1 DE69025232T DE69025232T DE69025232D1 DE 69025232 D1 DE69025232 D1 DE 69025232D1 DE 69025232 T DE69025232 T DE 69025232T DE 69025232 T DE69025232 T DE 69025232T DE 69025232 D1 DE69025232 D1 DE 69025232D1
Authority
DE
Germany
Prior art keywords
computer system
cache coherence
maintaining cache
maintaining
coherence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69025232T
Other languages
English (en)
Other versions
DE69025232T2 (de
Inventor
Fetra Ross V La
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of DE69025232D1 publication Critical patent/DE69025232D1/de
Application granted granted Critical
Publication of DE69025232T2 publication Critical patent/DE69025232T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0824—Distributed directories, e.g. linked lists of caches
DE69025232T 1989-06-21 1990-05-30 Verfahren zur Aufrechterhaltung der Cache-Speicherkohärenz in einem Mehrrechnersystem Expired - Fee Related DE69025232T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/369,152 US5197146A (en) 1989-06-21 1989-06-21 Method for maintaining cache coherence in a multiprocessor computer system

Publications (2)

Publication Number Publication Date
DE69025232D1 true DE69025232D1 (de) 1996-03-21
DE69025232T2 DE69025232T2 (de) 1996-06-20

Family

ID=23454298

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69025232T Expired - Fee Related DE69025232T2 (de) 1989-06-21 1990-05-30 Verfahren zur Aufrechterhaltung der Cache-Speicherkohärenz in einem Mehrrechnersystem

Country Status (4)

Country Link
US (1) US5197146A (de)
EP (1) EP0404369B1 (de)
JP (1) JP3199718B2 (de)
DE (1) DE69025232T2 (de)

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JPH05108473A (ja) * 1991-03-20 1993-04-30 Hitachi Ltd デ−タ処理システム
JPH0546475A (ja) * 1991-08-15 1993-02-26 Fujitsu Ltd バツフア記憶制御方式
US5724549A (en) * 1992-04-06 1998-03-03 Cyrix Corporation Cache coherency without bus master arbitration signals
EP0568231B1 (de) * 1992-04-29 1999-03-10 Sun Microsystems, Inc. Verfahren und Vorrichtung für mehreren ausstehende Operationen in einem cachespeicherkohärenten Multiprozessorsystem
US5511226A (en) * 1992-08-25 1996-04-23 Intel Corporation System for generating snoop addresses and conditionally generating source addresses whenever there is no snoop hit, the source addresses lagging behind the corresponding snoop addresses
JP2746530B2 (ja) * 1993-01-30 1998-05-06 洲 植 全 共有メモリマルチプロセッサ
US5604882A (en) * 1993-08-27 1997-02-18 International Business Machines Corporation System and method for empty notification from peer cache units to global storage control unit in a multiprocessor data processing system
US5604863A (en) * 1993-11-01 1997-02-18 International Business Machines Corporation Method for coordinating executing programs in a data processing system
US5535358A (en) * 1993-12-27 1996-07-09 Matsushita Electric Industrial Co., Ltd. Cache memory control circuit and method for controlling reading and writing requests
EP0681240B1 (de) * 1994-05-03 2001-01-10 Hewlett-Packard Company Anordnung mit Duplikat des Cache-Etikettenspeichers
US5551048A (en) * 1994-06-03 1996-08-27 Digital Equipment Corporation Ring based distributed communication bus for a multiprocessor network
US5680577A (en) * 1995-04-27 1997-10-21 International Business Machines Corporation Method and system for processing multiple requests for data residing at the same memory address
US5634110A (en) * 1995-05-05 1997-05-27 Silicon Graphics, Inc. Cache coherency using flexible directory bit vectors
US6098150A (en) * 1995-11-17 2000-08-01 Sun Microsystems, Inc. Method and apparatus for fetching information from a cache memory
US5805837A (en) * 1996-03-21 1998-09-08 International Business Machines Corporation Method for optimizing reissue commands in master-slave processing systems
US5991819A (en) * 1996-12-03 1999-11-23 Intel Corporation Dual-ported memory controller which maintains cache coherency using a memory line status table
US6122711A (en) 1997-01-07 2000-09-19 Unisys Corporation Method of and apparatus for store-in second level cache flush
US6052761A (en) * 1997-01-31 2000-04-18 Hewlett-Packard Company Increment update in an SCI based system
US6094709A (en) * 1997-07-01 2000-07-25 International Business Machines Corporation Cache coherence for lazy entry consistency in lockup-free caches
US6226714B1 (en) * 1997-07-15 2001-05-01 International Business Machines Corporation Method for invalidating cache lines on a sharing list
US6098156A (en) * 1997-07-22 2000-08-01 International Business Machines Corporation Method and system for rapid line ownership transfer for multiprocessor updates
US6295598B1 (en) * 1998-06-30 2001-09-25 Src Computers, Inc. Split directory-based cache coherency technique for a multi-processor computer system
US7013305B2 (en) 2001-10-01 2006-03-14 International Business Machines Corporation Managing the state of coupling facility structures, detecting by one or more systems coupled to the coupling facility, the suspended state of the duplexed command, detecting being independent of message exchange
US6442597B1 (en) * 1999-07-08 2002-08-27 International Business Machines Corporation Providing global coherence in SMP systems using response combination block coupled to address switch connecting node controllers to memory
US6748498B2 (en) * 2000-06-10 2004-06-08 Hewlett-Packard Development Company, L.P. Scalable multiprocessor system and cache coherence method implementing store-conditional memory transactions while an associated directory entry is encoded as a coarse bit vector
US6738836B1 (en) * 2000-08-31 2004-05-18 Hewlett-Packard Development Company, L.P. Scalable efficient I/O port protocol
US6961825B2 (en) * 2001-01-24 2005-11-01 Hewlett-Packard Development Company, L.P. Cache coherency mechanism using arbitration masks
US7240114B2 (en) * 2001-09-25 2007-07-03 Hewlett-Packard Development Company, L.P. Namespace management in a distributed file system
US7426568B2 (en) * 2002-06-10 2008-09-16 Lsi Corporation Seek minimized recoverable streaming file system
US7096323B1 (en) * 2002-09-27 2006-08-22 Advanced Micro Devices, Inc. Computer system with processor cache that stores remote cache presence information
US6868485B1 (en) * 2002-09-27 2005-03-15 Advanced Micro Devices, Inc. Computer system with integrated directory and processor cache
GB0228110D0 (en) * 2002-12-02 2003-01-08 Goodrich Control Sys Ltd Apparatus for and method of transferring data
US7213244B2 (en) * 2003-03-13 2007-05-01 International Business Machines Corporation Apparatus and method for distribution of work on a doubly linked list among processing threads
US7373466B1 (en) 2004-04-07 2008-05-13 Advanced Micro Devices, Inc. Method and apparatus for filtering memory write snoop activity in a distributed shared memory computer
EP1782244A4 (de) * 2004-07-07 2010-01-20 Emc Corp Systeme und verfahren zur bereitstellung von kohärenz eines verteilten cache
US20060294313A1 (en) * 2005-06-23 2006-12-28 International Business Machines Corporation System and method of remote media cache optimization for use with multiple processing units
US7412567B2 (en) * 2006-04-28 2008-08-12 Sun Microsystems, Inc. Value-based memory coherence support
US7725654B2 (en) * 2006-07-25 2010-05-25 Hewlett-Packard Development Company, L.P. Affecting a caching algorithm used by a cache of storage system
US9852074B2 (en) * 2015-01-12 2017-12-26 Alcatel Lucent Cache-optimized hash table data structure
US10949235B2 (en) * 2016-12-12 2021-03-16 Intel Corporation Network semantics integrated into central processing unit (CPU) chipset
US10795820B2 (en) * 2017-02-08 2020-10-06 Arm Limited Read transaction tracker lifetimes in a coherent interconnect system

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US4571674A (en) * 1982-09-27 1986-02-18 International Business Machines Corporation Peripheral storage system having multiple data transfer rates
ATE62764T1 (de) * 1984-02-10 1991-05-15 Prime Computer Inc Cache-kohaerenz-anordnung.
US4747043A (en) * 1984-02-10 1988-05-24 Prime Computer, Inc. Multiprocessor cache coherence system
US4847804A (en) * 1985-02-05 1989-07-11 Digital Equipment Corporation Apparatus and method for data copy consistency in a multi-cache data processing unit
US4933835A (en) * 1985-02-22 1990-06-12 Intergraph Corporation Apparatus for maintaining consistency of a cache memory with a primary memory
US4713755A (en) * 1985-06-28 1987-12-15 Hewlett-Packard Company Cache memory consistency control with explicit software instructions
US4843542A (en) * 1986-11-12 1989-06-27 Xerox Corporation Virtual memory cache for use in multi-processing systems
GB8728494D0 (en) * 1987-12-05 1988-01-13 Int Computers Ltd Multi-cache data storage system
US5025365A (en) * 1988-11-14 1991-06-18 Unisys Corporation Hardware implemented cache coherency protocol with duplicated distributed directories for high-performance multiprocessors

Also Published As

Publication number Publication date
JPH0331947A (ja) 1991-02-12
EP0404369B1 (de) 1996-02-07
EP0404369A3 (de) 1991-09-25
DE69025232T2 (de) 1996-06-20
JP3199718B2 (ja) 2001-08-20
US5197146A (en) 1993-03-23
EP0404369A2 (de) 1990-12-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD CO. (N.D.GES.D.STAATES DELAWARE),

8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE

8339 Ceased/non-payment of the annual fee