DE68929012T2 - Verfahren zur Herstellung von Mehrschichtschaltungen - Google Patents

Verfahren zur Herstellung von Mehrschichtschaltungen

Info

Publication number
DE68929012T2
DE68929012T2 DE68929012T DE68929012T DE68929012T2 DE 68929012 T2 DE68929012 T2 DE 68929012T2 DE 68929012 T DE68929012 T DE 68929012T DE 68929012 T DE68929012 T DE 68929012T DE 68929012 T2 DE68929012 T2 DE 68929012T2
Authority
DE
Germany
Prior art keywords
production
multilayer circuits
multilayer
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68929012T
Other languages
English (en)
Other versions
DE68929012D1 (de
Inventor
Joseph Richard Rellick
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EIDP Inc
Original Assignee
EI Du Pont de Nemours and Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by EI Du Pont de Nemours and Co filed Critical EI Du Pont de Nemours and Co
Application granted granted Critical
Publication of DE68929012D1 publication Critical patent/DE68929012D1/de
Publication of DE68929012T2 publication Critical patent/DE68929012T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
    • H05K3/4667—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders characterized by using an inorganic intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/068—Features of the lamination press or of the lamination process, e.g. using special separator sheets
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
    • H05K2203/107—Using laser light
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
    • Y10T156/1052—Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing
    • Y10T156/1056—Perforating lamina
    • Y10T156/1057—Subsequent to assembly of laminae
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49163—Manufacturing circuit on or in base with sintering of base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
DE68929012T 1988-03-04 1989-03-02 Verfahren zur Herstellung von Mehrschichtschaltungen Expired - Fee Related DE68929012T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/164,452 US4806188A (en) 1988-03-04 1988-03-04 Method for fabricating multilayer circuits

Publications (2)

Publication Number Publication Date
DE68929012D1 DE68929012D1 (de) 1999-07-08
DE68929012T2 true DE68929012T2 (de) 1999-10-21

Family

ID=22594544

Family Applications (2)

Application Number Title Priority Date Filing Date
DE68929012T Expired - Fee Related DE68929012T2 (de) 1988-03-04 1989-03-02 Verfahren zur Herstellung von Mehrschichtschaltungen
DE68923468T Expired - Fee Related DE68923468T2 (de) 1988-03-04 1989-03-02 Verfahren zur Herstellung von Mehrschichtschaltungen.

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE68923468T Expired - Fee Related DE68923468T2 (de) 1988-03-04 1989-03-02 Verfahren zur Herstellung von Mehrschichtschaltungen.

Country Status (6)

Country Link
US (1) US4806188A (de)
EP (2) EP0631303B1 (de)
JP (1) JPH0634451B2 (de)
KR (1) KR920004039B1 (de)
DE (2) DE68929012T2 (de)
MY (1) MY105814A (de)

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JPH0611018B2 (ja) * 1988-01-07 1994-02-09 株式会社村田製作所 セラミック生シートの積層方法
US4806188A (en) * 1988-03-04 1989-02-21 E. I. Du Pont De Nemours And Company Method for fabricating multilayer circuits
JPH0682926B2 (ja) * 1988-04-22 1994-10-19 日本電気株式会社 多層配線基板の製造方法
EP0396806B1 (de) * 1989-05-12 1994-02-02 Ibm Deutschland Gmbh Glas-Keramik-Gegenstand und Verfahren zu dessen Herstellung
US5072075A (en) * 1989-06-28 1991-12-10 Digital Equipment Corporation Double-sided hybrid high density circuit board and method of making same
US5102720A (en) * 1989-09-22 1992-04-07 Cornell Research Foundation, Inc. Co-fired multilayer ceramic tapes that exhibit constrained sintering
JP2761776B2 (ja) * 1989-10-25 1998-06-04 Ii Ai Deyuhon De Nimoasu Ando Co 多層回路板の製造方法
JPH07120603B2 (ja) * 1989-10-30 1995-12-20 株式会社村田製作所 セラミックグリーンシートの積層方法および装置
US5006182A (en) * 1989-11-17 1991-04-09 E. I. Du Pont De Nemours And Company Method for fabricating multilayer circuits
US5379515A (en) * 1989-12-11 1995-01-10 Canon Kabushiki Kaisha Process for preparing electrical connecting member
JPH03196691A (ja) * 1989-12-26 1991-08-28 Cmk Corp プリント配線板の絶縁層の形成方法
US5210455A (en) * 1990-07-26 1993-05-11 Ngk Insulators, Ltd. Piezoelectric/electrostrictive actuator having ceramic substrate having recess defining thin-walled portion
US5109455A (en) * 1990-08-03 1992-04-28 Cts Corporation Optic interface hybrid
JP2739726B2 (ja) * 1990-09-27 1998-04-15 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン 多層プリント回路板
US5217550A (en) * 1990-09-28 1993-06-08 Dai Nippon Printing Co., Ltd Alignment transfer method
US5254191A (en) * 1990-10-04 1993-10-19 E. I. Du Pont De Nemours And Company Method for reducing shrinkage during firing of ceramic bodies
JP2551224B2 (ja) * 1990-10-17 1996-11-06 日本電気株式会社 多層配線基板および多層配線基板の製造方法
US5296735A (en) * 1991-01-21 1994-03-22 Mitsubishi Denki Kabushiki Kaisha Power semiconductor module with multiple shielding layers
DE69232606T2 (de) * 1991-02-25 2004-08-05 Canon K.K. Elektrischer Verbindungskörper und Herstellungsverfahren dafür
US5293025A (en) * 1991-08-01 1994-03-08 E. I. Du Pont De Nemours And Company Method for forming vias in multilayer circuits
US5209798A (en) * 1991-11-22 1993-05-11 Grunman Aerospace Corporation Method of forming a precisely spaced stack of substrate layers
JP3166251B2 (ja) * 1991-12-18 2001-05-14 株式会社村田製作所 セラミック多層電子部品の製造方法
US5292624A (en) * 1992-09-14 1994-03-08 International Technology Research Institute Method for forming a metallurgical interconnection layer package for a multilayer ceramic substrate
JPH06209068A (ja) * 1992-12-29 1994-07-26 Sumitomo Kinzoku Ceramics:Kk Ｉｃパッケージ
US5294567A (en) * 1993-01-08 1994-03-15 E. I. Du Pont De Nemours And Company Method for forming via holes in multilayer circuits
JP3457348B2 (ja) * 1993-01-15 2003-10-14 株式会社東芝 半導体装置の製造方法
US5454161A (en) * 1993-04-29 1995-10-03 Fujitsu Limited Through hole interconnect substrate fabrication process
US5632942A (en) * 1993-05-24 1997-05-27 Industrial Technoology Research Institute Method for preparing multilayer ceramic/glass substrates with electromagnetic shielding
US5455385A (en) * 1993-06-28 1995-10-03 Harris Corporation Multilayer LTCC tub architecture for hermetically sealing semiconductor die, external electrical access for which is provided by way of sidewall recesses
FR2716037B1 (fr) * 1994-02-10 1996-06-07 Matra Marconi Space France Procédé pour connecter des circuits électoniques dans un module multi-puces à substrat co-cuit, et module multi-puces ainsi obtenu.
JP3570447B2 (ja) * 1994-12-21 2004-09-29 セイコーエプソン株式会社 積層型インクジェット式記録ヘッド、及びその製造方法、及び記録装置
JP3077543B2 (ja) * 1995-01-13 2000-08-14 セイコーエプソン株式会社 被覆導電体およびその製造方法、およびこれを用いた電子部品、電子機器
US5655209A (en) * 1995-03-28 1997-08-05 International Business Machines Corporation Multilayer ceramic substrates having internal capacitor, and process for producing same
US5821846A (en) * 1995-05-22 1998-10-13 Steward, Inc. High current ferrite electromagnetic interference suppressor and associated method
US5855995A (en) * 1997-02-21 1999-01-05 Medtronic, Inc. Ceramic substrate for implantable medical devices
SE510487C2 (sv) 1997-09-17 1999-05-31 Ericsson Telefon Ab L M Flerlagerskretskort
US6245185B1 (en) * 1999-07-15 2001-06-12 International Business Machines Corporation Method of making a multilayer ceramic product with thin layers
US6477031B1 (en) * 2000-03-22 2002-11-05 Tdk Corporation Electronic component for high frequency signals and method for fabricating the same
TW543052B (en) * 2001-03-05 2003-07-21 Nitto Denko Corp Manufacturing method of ceramic green sheet, manufacturing method of multilayer ceramic electronic components, and carrier sheet for ceramic green sheets
JP4770059B2 (ja) * 2001-05-24 2011-09-07 パナソニック株式会社 セラミック多層基板の製造方法
US6930256B1 (en) 2002-05-01 2005-08-16 Amkor Technology, Inc. Integrated circuit substrate having laser-embedded conductive patterns and method therefor
JP3864114B2 (ja) * 2001-08-02 2006-12-27 株式会社日本自動車部品総合研究所 積層型誘電体の製造方法
KR20030048661A (ko) * 2001-12-12 2003-06-25 엘지이노텍 주식회사 반도체 칩의 냉각 장치
US7633765B1 (en) 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
US9691635B1 (en) 2002-05-01 2017-06-27 Amkor Technology, Inc. Buildup dielectric layer having metallization pattern semiconductor package fabrication method
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US7670962B2 (en) * 2002-05-01 2010-03-02 Amkor Technology, Inc. Substrate having stiffener fabrication method
US7303698B2 (en) * 2003-11-19 2007-12-04 E.I. Du Pont De Nemours And Company Thick film conductor case compositions for LTCC tape
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FR2571545B1 (fr) * 1984-10-05 1987-11-27 Thomson Csf Procede de fabrication d'un substrat de circuit hybride de forme non plane, et circuit hybride non plan obtenu par ce procede
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US4654095A (en) * 1985-03-25 1987-03-31 E. I. Du Pont De Nemours And Company Dielectric composition
US4655864A (en) * 1985-03-25 1987-04-07 E. I. Du Pont De Nemours And Company Dielectric compositions and method of forming a multilayer interconnection using same
US4806188A (en) * 1988-03-04 1989-02-21 E. I. Du Pont De Nemours And Company Method for fabricating multilayer circuits

Also Published As

Publication number Publication date
EP0631303A3 (de) 1995-08-16
DE68923468T2 (de) 1996-03-21
EP0631303A2 (de) 1994-12-28
EP0631303B1 (de) 1999-06-02
US4806188A (en) 1989-02-21
KR890015390A (ko) 1989-10-30
MY105814A (en) 1995-01-30
KR920004039B1 (en) 1992-05-22
EP0331161B1 (de) 1995-07-19
JPH01282890A (ja) 1989-11-14
DE68929012D1 (de) 1999-07-08
EP0331161A1 (de) 1989-09-06
DE68923468D1 (de) 1995-08-24
JPH0634451B2 (ja) 1994-05-02

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