DE68924564D1 - Verfahren der Planarisierung von Halbleiterelementen. - Google Patents
Verfahren der Planarisierung von Halbleiterelementen.Info
- Publication number
- DE68924564D1 DE68924564D1 DE68924564T DE68924564T DE68924564D1 DE 68924564 D1 DE68924564 D1 DE 68924564D1 DE 68924564 T DE68924564 T DE 68924564T DE 68924564 T DE68924564 T DE 68924564T DE 68924564 D1 DE68924564 D1 DE 68924564D1
- Authority
- DE
- Germany
- Prior art keywords
- planarization
- semiconductor elements
- semiconductor
- elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02428—Structure
- H01L21/0243—Surface structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/026—Deposition thru hole in mask
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/072—Heterojunctions
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/10—Lift-off masking
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/933—Germanium or silicon or Ge-Si on III-V
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/948—Radiation resist
- Y10S438/951—Lift-off
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/224,965 US4910164A (en) | 1988-07-27 | 1988-07-27 | Method of making planarized heterostructures using selective epitaxial growth |
Publications (2)
Publication Number | Publication Date |
---|---|
DE68924564D1 true DE68924564D1 (de) | 1995-11-23 |
DE68924564T2 DE68924564T2 (de) | 1996-03-21 |
Family
ID=22842969
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE68924564T Expired - Fee Related DE68924564T2 (de) | 1988-07-27 | 1989-06-20 | Verfahren der Planarisierung von Halbleiterelementen. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4910164A (de) |
EP (1) | EP0352471B1 (de) |
JP (1) | JP2686322B2 (de) |
KR (1) | KR0166958B1 (de) |
DE (1) | DE68924564T2 (de) |
Families Citing this family (51)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5013682A (en) * | 1986-10-22 | 1991-05-07 | Texas Instruments Incorporated | Method for selective epitaxy using a WSI mask |
DE68923756T2 (de) * | 1988-10-28 | 1996-03-07 | Texas Instruments Inc | Abgedeckte Wärmebehandlung. |
GB2228617A (en) * | 1989-02-27 | 1990-08-29 | Philips Electronic Associated | A method of manufacturing a semiconductor device having a mesa structure |
US5202284A (en) * | 1989-12-01 | 1993-04-13 | Hewlett-Packard Company | Selective and non-selective deposition of Si1-x Gex on a Si subsrate that is partially masked with SiO2 |
US4971928A (en) * | 1990-01-16 | 1990-11-20 | General Motors Corporation | Method of making a light emitting semiconductor having a rear reflecting surface |
US5084409A (en) * | 1990-06-26 | 1992-01-28 | Texas Instruments Incorporated | Method for patterned heteroepitaxial growth |
US5110410A (en) * | 1990-08-13 | 1992-05-05 | Texas Instruments Incorporated | Zinc sulfide planarization |
EP0496215B1 (de) * | 1991-01-21 | 1995-08-30 | Siemens Aktiengesellschaft | Verfahren zur Herstellung eines strukturierten Aufbaus mit Hochtemperatursupraleitermaterial |
FR2687008B1 (fr) * | 1992-02-05 | 2001-06-22 | Patrick Launay | Procede de fabrication de structures actives et dispositifs semiconducteurs ainsi obtenus. |
US5279974A (en) * | 1992-07-24 | 1994-01-18 | Santa Barbara Research Center | Planar PV HgCdTe DLHJ fabricated by selective cap layer growth |
US5443685A (en) * | 1993-11-01 | 1995-08-22 | At&T Corp. | Composition and method for off-axis growth sites on nonpolar substrates |
JP2970425B2 (ja) * | 1994-09-26 | 1999-11-02 | 日本電気株式会社 | バイポーラトランジスタの製造方法 |
KR0162865B1 (ko) * | 1995-03-09 | 1999-02-01 | 김은영 | 반도체 패턴 측면의 에피성장율 조절방법 |
US5659640A (en) * | 1995-06-27 | 1997-08-19 | Lucent Technologies Inc. | Integrated waveguide having an internal optical grating |
US6316820B1 (en) | 1997-07-25 | 2001-11-13 | Hughes Electronics Corporation | Passivation layer and process for semiconductor devices |
US6392257B1 (en) * | 2000-02-10 | 2002-05-21 | Motorola Inc. | Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same |
US6693033B2 (en) | 2000-02-10 | 2004-02-17 | Motorola, Inc. | Method of removing an amorphous oxide from a monocrystalline surface |
WO2001093336A1 (en) | 2000-05-31 | 2001-12-06 | Motorola, Inc. | Semiconductor device and method for manufacturing the same |
AU2001277001A1 (en) * | 2000-07-24 | 2002-02-05 | Motorola, Inc. | Heterojunction tunneling diodes and process for fabricating same |
US6638838B1 (en) | 2000-10-02 | 2003-10-28 | Motorola, Inc. | Semiconductor structure including a partially annealed layer and method of forming the same |
US20020096683A1 (en) * | 2001-01-19 | 2002-07-25 | Motorola, Inc. | Structure and method for fabricating GaN devices utilizing the formation of a compliant substrate |
US6673646B2 (en) | 2001-02-28 | 2004-01-06 | Motorola, Inc. | Growth of compound semiconductor structures on patterned oxide films and process for fabricating same |
WO2002082551A1 (en) | 2001-04-02 | 2002-10-17 | Motorola, Inc. | A semiconductor structure exhibiting reduced leakage current |
US6709989B2 (en) | 2001-06-21 | 2004-03-23 | Motorola, Inc. | Method for fabricating a semiconductor structure including a metal oxide interface with silicon |
US6992321B2 (en) | 2001-07-13 | 2006-01-31 | Motorola, Inc. | Structure and method for fabricating semiconductor structures and devices utilizing piezoelectric materials |
US20030010992A1 (en) * | 2001-07-16 | 2003-01-16 | Motorola, Inc. | Semiconductor structure and method for implementing cross-point switch functionality |
US6646293B2 (en) | 2001-07-18 | 2003-11-11 | Motorola, Inc. | Structure for fabricating high electron mobility transistors utilizing the formation of complaint substrates |
US6693298B2 (en) | 2001-07-20 | 2004-02-17 | Motorola, Inc. | Structure and method for fabricating epitaxial semiconductor on insulator (SOI) structures and devices utilizing the formation of a compliant substrate for materials used to form same |
US7019332B2 (en) | 2001-07-20 | 2006-03-28 | Freescale Semiconductor, Inc. | Fabrication of a wavelength locker within a semiconductor structure |
US6855992B2 (en) * | 2001-07-24 | 2005-02-15 | Motorola Inc. | Structure and method for fabricating configurable transistor devices utilizing the formation of a compliant substrate for materials used to form the same |
US6667196B2 (en) | 2001-07-25 | 2003-12-23 | Motorola, Inc. | Method for real-time monitoring and controlling perovskite oxide film growth and semiconductor structure formed using the method |
US6589856B2 (en) | 2001-08-06 | 2003-07-08 | Motorola, Inc. | Method and apparatus for controlling anti-phase domains in semiconductor structures and devices |
US6639249B2 (en) | 2001-08-06 | 2003-10-28 | Motorola, Inc. | Structure and method for fabrication for a solid-state lighting device |
US20030034491A1 (en) | 2001-08-14 | 2003-02-20 | Motorola, Inc. | Structure and method for fabricating semiconductor structures and devices for detecting an object |
US6673667B2 (en) | 2001-08-15 | 2004-01-06 | Motorola, Inc. | Method for manufacturing a substantially integral monolithic apparatus including a plurality of semiconductor materials |
US20030036217A1 (en) * | 2001-08-16 | 2003-02-20 | Motorola, Inc. | Microcavity semiconductor laser coupled to a waveguide |
US20030071327A1 (en) * | 2001-10-17 | 2003-04-17 | Motorola, Inc. | Method and apparatus utilizing monocrystalline insulator |
US6916717B2 (en) * | 2002-05-03 | 2005-07-12 | Motorola, Inc. | Method for growing a monocrystalline oxide layer and for fabricating a semiconductor device on a monocrystalline substrate |
US20040012037A1 (en) * | 2002-07-18 | 2004-01-22 | Motorola, Inc. | Hetero-integration of semiconductor materials on silicon |
US20040069991A1 (en) * | 2002-10-10 | 2004-04-15 | Motorola, Inc. | Perovskite cuprate electronic device structure and process |
US20040070312A1 (en) * | 2002-10-10 | 2004-04-15 | Motorola, Inc. | Integrated circuit and process for fabricating the same |
US7169619B2 (en) | 2002-11-19 | 2007-01-30 | Freescale Semiconductor, Inc. | Method for fabricating semiconductor structures on vicinal substrates using a low temperature, low pressure, alkaline earth metal-rich process |
US6885065B2 (en) | 2002-11-20 | 2005-04-26 | Freescale Semiconductor, Inc. | Ferromagnetic semiconductor structure and method for forming the same |
US7020374B2 (en) * | 2003-02-03 | 2006-03-28 | Freescale Semiconductor, Inc. | Optical waveguide structure and method for fabricating the same |
US6965128B2 (en) * | 2003-02-03 | 2005-11-15 | Freescale Semiconductor, Inc. | Structure and method for fabricating semiconductor microresonator devices |
US20040164315A1 (en) * | 2003-02-25 | 2004-08-26 | Motorola, Inc. | Structure and device including a tunneling piezoelectric switch and method of forming same |
US7514328B2 (en) * | 2003-06-26 | 2009-04-07 | Mears Technologies, Inc. | Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween |
KR20130047813A (ko) * | 2011-10-31 | 2013-05-09 | 삼성전자주식회사 | Iii-v족 화합물 반도체층을 포함하는 반도체 소자 및 그 제조방법 |
DE102014107167B4 (de) | 2014-05-21 | 2022-04-21 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Verfahren zur Herstellung eines Halbleiterbauelements mit einer Strukturschicht mit einer Mehrzahl von dreidimensionalen Strukturelementen und strahlungsemittierendes Halbleiterbauelement mit einer Strukturschicht mit einer Mehrzahl von dreidimensionalen Strukturelementen |
US9378950B1 (en) * | 2015-05-22 | 2016-06-28 | Stratio | Methods for removing nuclei formed during epitaxial growth |
DE102020209927A1 (de) | 2020-08-06 | 2022-02-10 | Robert Bosch Gesellschaft mit beschränkter Haftung | Einebnen von Materialerhebungen auf Halbleiterschichten |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3322581A (en) * | 1965-10-24 | 1967-05-30 | Texas Instruments Inc | Fabrication of a metal base transistor |
US3401449A (en) * | 1965-10-24 | 1968-09-17 | Texas Instruments Inc | Method of fabricating a metal base transistor |
US3764409A (en) * | 1969-09-29 | 1973-10-09 | Hitachi Ltd | Method for fabricating a semiconductor component for a semiconductor circuit |
WO1981002948A1 (en) * | 1980-04-10 | 1981-10-15 | Massachusetts Inst Technology | Methods of producing sheets of crystalline material and devices made therefrom |
JPS5893344A (ja) * | 1981-11-30 | 1983-06-03 | Toshiba Corp | 半導体装置及びその製造方法 |
JPS6276645A (ja) * | 1985-09-30 | 1987-04-08 | Toshiba Corp | 複合半導体結晶体構造 |
DE3727517C2 (de) * | 1987-08-18 | 1995-06-01 | Licentia Gmbh | Verfahren zur Herstellung isolierter Halbleiterbereiche in einem Halbleiterkörper und damit hergestellte strukturierte Halbleiterkörper |
-
1988
- 1988-07-27 US US07/224,965 patent/US4910164A/en not_active Expired - Lifetime
-
1989
- 1989-06-20 EP EP89111209A patent/EP0352471B1/de not_active Expired - Lifetime
- 1989-06-20 DE DE68924564T patent/DE68924564T2/de not_active Expired - Fee Related
- 1989-07-27 KR KR1019890010745A patent/KR0166958B1/ko not_active IP Right Cessation
- 1989-07-27 JP JP1195377A patent/JP2686322B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US4910164A (en) | 1990-03-20 |
KR0166958B1 (ko) | 1999-02-01 |
EP0352471A3 (de) | 1991-03-06 |
JP2686322B2 (ja) | 1997-12-08 |
DE68924564T2 (de) | 1996-03-21 |
KR900002405A (ko) | 1990-02-28 |
EP0352471A2 (de) | 1990-01-31 |
JPH02168631A (ja) | 1990-06-28 |
EP0352471B1 (de) | 1995-10-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |