DE639006T1 - Multiplexbetriebene Steueranschlüsse zum Programmieren innerhalb des Systems und zum Boundary-Scan-Testen mittels Automaten bei einer programmierbaren logischen Schaltung hoher Integrationsdichte. - Google Patents
Multiplexbetriebene Steueranschlüsse zum Programmieren innerhalb des Systems und zum Boundary-Scan-Testen mittels Automaten bei einer programmierbaren logischen Schaltung hoher Integrationsdichte.Info
- Publication number
- DE639006T1 DE639006T1 DE0639006T DE94202212T DE639006T1 DE 639006 T1 DE639006 T1 DE 639006T1 DE 0639006 T DE0639006 T DE 0639006T DE 94202212 T DE94202212 T DE 94202212T DE 639006 T1 DE639006 T1 DE 639006T1
- Authority
- DE
- Germany
- Prior art keywords
- automats
- multiplex
- programming
- logic circuit
- programmable logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318555—Control logic
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318558—Addressing or selecting of subparts of the device under test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318572—Input/Output interfaces
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/22—Means for limiting or controlling the pin/gate ratio
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1731—Optimisation thereof
- H03K19/1732—Optimisation thereof by limitation or reduction of the pin/gate ratio
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1737—Controllable logic circuits using multiplexers
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/106,263 US5412260A (en) | 1991-05-03 | 1993-08-13 | Multiplexed control pins for in-system programming and boundary scan state machines in a high density programmable logic device |
Publications (1)
Publication Number | Publication Date |
---|---|
DE639006T1 true DE639006T1 (de) | 1996-02-15 |
Family
ID=22310437
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69433259T Expired - Lifetime DE69433259D1 (de) | 1993-08-13 | 1994-07-28 | Multiplexbetriebene Steueranschlüsse zum Programmieren innerhalb des Systems und zum Boundary-Scan-Testen mittels Automaten bei einer programmierbaren logischen Schaltung hoher Integrationsdichte |
DE0639006T Pending DE639006T1 (de) | 1993-08-13 | 1994-07-28 | Multiplexbetriebene Steueranschlüsse zum Programmieren innerhalb des Systems und zum Boundary-Scan-Testen mittels Automaten bei einer programmierbaren logischen Schaltung hoher Integrationsdichte. |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69433259T Expired - Lifetime DE69433259D1 (de) | 1993-08-13 | 1994-07-28 | Multiplexbetriebene Steueranschlüsse zum Programmieren innerhalb des Systems und zum Boundary-Scan-Testen mittels Automaten bei einer programmierbaren logischen Schaltung hoher Integrationsdichte |
Country Status (4)
Country | Link |
---|---|
US (1) | US5412260A (de) |
EP (1) | EP0639006B1 (de) |
JP (1) | JPH07175677A (de) |
DE (2) | DE69433259D1 (de) |
Families Citing this family (68)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5596734A (en) * | 1993-12-17 | 1997-01-21 | Intel Corporation | Method and apparatus for programming embedded memories of a variety of integrated circuits using the IEEE test access port |
TW253031B (de) * | 1993-12-27 | 1995-08-01 | At & T Corp | |
JPH0991957A (ja) * | 1995-07-14 | 1997-04-04 | Mitsubishi Electric Corp | 半導体装置のモード選定回路 |
US5734868A (en) * | 1995-08-09 | 1998-03-31 | Curd; Derek R. | Efficient in-system programming structure and method for non-volatile programmable logic devices |
US5706297A (en) * | 1995-08-24 | 1998-01-06 | Unisys Corporation | System for adapting maintenance operations to JTAG and non-JTAG modules |
US5629635A (en) * | 1995-09-26 | 1997-05-13 | Ics Technologies, Inc. | Address programming via LED pin |
US5717695A (en) * | 1995-12-04 | 1998-02-10 | Silicon Graphics, Inc. | Output pin for selectively outputting one of a plurality of signals internal to a semiconductor chip according to a programmable register for diagnostics |
US5898701A (en) * | 1995-12-21 | 1999-04-27 | Cypress Semiconductor Corporation | Method and apparatus for testing a device |
US5835503A (en) * | 1996-03-28 | 1998-11-10 | Cypress Semiconductor Corp. | Method and apparatus for serially programming a programmable logic device |
US5768288A (en) * | 1996-03-28 | 1998-06-16 | Cypress Semiconductor Corp. | Method and apparatus for programming a programmable logic device having verify logic for comparing verify data read from a memory location with program data |
US5805794A (en) * | 1996-03-28 | 1998-09-08 | Cypress Semiconductor Corp. | CPLD serial programming with extra read register |
US5815510A (en) * | 1996-03-28 | 1998-09-29 | Cypress Semiconductor Corp. | Serial programming of instruction codes in different numbers of clock cycles |
US5869979A (en) * | 1996-04-05 | 1999-02-09 | Altera Corporation | Technique for preconditioning I/Os during reconfiguration |
US5870410A (en) * | 1996-04-29 | 1999-02-09 | Altera Corporation | Diagnostic interface system for programmable logic system development |
US5864486A (en) * | 1996-05-08 | 1999-01-26 | Lattice Semiconductor Corporation | Method and apparatus for in-system programming of a programmable logic device using a two-wire interface |
US5764076A (en) * | 1996-06-26 | 1998-06-09 | Xilinx, Inc. | Circuit for partially reprogramming an operational programmable logic device |
US6097211A (en) * | 1996-07-18 | 2000-08-01 | Altera Corporation | Configuration memory integrated circuit |
GB2346473B (en) * | 1996-07-18 | 2000-12-27 | Altera Corp | Configuration memory |
US6804725B1 (en) * | 1996-08-30 | 2004-10-12 | Texas Instruments Incorporated | IC with state machine controlled linking module |
US5805607A (en) * | 1996-10-22 | 1998-09-08 | Advanced Micro Devices, Inc. | Method for user-controlled I/O switching during in-circuit programming of CPLDs through the IEEE 1149.1 test access port |
US5867037A (en) * | 1996-10-24 | 1999-02-02 | International Business Machines Corporation | Method and apparatus of programming FPGA devices through ASIC devices |
US5825199A (en) * | 1997-01-30 | 1998-10-20 | Vlsi Technology, Inc. | Reprogrammable state machine and method therefor |
EP0862063A1 (de) * | 1997-02-27 | 1998-09-02 | Siemens Aktiengesellschaft | Schnittstellen-Steuerung einer Test-Schnittstelle |
GB9707364D0 (en) * | 1997-04-11 | 1997-05-28 | Eidos Technologies Limited | A method and a system for processing digital information |
US6421812B1 (en) * | 1997-06-10 | 2002-07-16 | Altera Corporation | Programming mode selection with JTAG circuits |
US6691267B1 (en) * | 1997-06-10 | 2004-02-10 | Altera Corporation | Technique to test an integrated circuit using fewer pins |
US6020760A (en) * | 1997-07-16 | 2000-02-01 | Altera Corporation | I/O buffer circuit with pin multiplexing |
US6011744A (en) * | 1997-07-16 | 2000-01-04 | Altera Corporation | Programmable logic device with multi-port memory |
US6034857A (en) | 1997-07-16 | 2000-03-07 | Altera Corporation | Input/output buffer with overcurrent protection circuit |
US6108807A (en) * | 1997-07-28 | 2000-08-22 | Lucent Technologies Inc. | Apparatus and method for hybrid pin control of boundary scan applications |
US6032279A (en) * | 1997-11-07 | 2000-02-29 | Atmel Corporation | Boundary scan system with address dependent instructions |
US5848026A (en) * | 1997-12-08 | 1998-12-08 | Atmel Corporation | Integrated circuit with flag register for block selection of nonvolatile cells for bulk operations |
US5968196A (en) * | 1998-04-21 | 1999-10-19 | Atmel Corporation | Configuration control in a programmable logic device using non-volatile elements |
US6304099B1 (en) * | 1998-05-21 | 2001-10-16 | Lattice Semiconductor Corporation | Method and structure for dynamic in-system programming |
US6430719B1 (en) | 1998-06-12 | 2002-08-06 | Stmicroelectronics, Inc. | General port capable of implementing the JTAG protocol |
JP2000065899A (ja) * | 1998-08-14 | 2000-03-03 | Sony Corp | 半導体装置およびそのデータ書き換え方法 |
DE19981944D2 (de) | 1998-09-29 | 2002-08-29 | Siemens Ag | Anwendungsspezifischer Baustein mit reduziertem Aufwand bei Überarbeitung |
US6158034A (en) * | 1998-12-03 | 2000-12-05 | Atmel Corporation | Boundary scan method for terminating or modifying integrated circuit operating modes |
US7013415B1 (en) * | 1999-05-26 | 2006-03-14 | Renesas Technology Corp. | IC with internal interface switch for testability |
US6931572B1 (en) | 1999-11-30 | 2005-08-16 | Synplicity, Inc. | Design instrumentation circuitry |
US7072818B1 (en) | 1999-11-30 | 2006-07-04 | Synplicity, Inc. | Method and system for debugging an electronic system |
US6823497B2 (en) | 1999-11-30 | 2004-11-23 | Synplicity, Inc. | Method and user interface for debugging an electronic system |
US7356786B2 (en) * | 1999-11-30 | 2008-04-08 | Synplicity, Inc. | Method and user interface for debugging an electronic system |
US6581191B1 (en) * | 1999-11-30 | 2003-06-17 | Synplicity, Inc. | Hardware debugging in a hardware description language |
US7065481B2 (en) | 1999-11-30 | 2006-06-20 | Synplicity, Inc. | Method and system for debugging an electronic system using instrumentation circuitry and a logic analyzer |
US6803785B1 (en) | 2000-06-12 | 2004-10-12 | Altera Corporation | I/O circuitry shared between processor and programmable logic portions of an integrated circuit |
US6961884B1 (en) | 2000-06-12 | 2005-11-01 | Altera Corporation | JTAG mirroring circuitry and methods |
US7340596B1 (en) | 2000-06-12 | 2008-03-04 | Altera Corporation | Embedded processor with watchdog timer for programmable logic |
US7222315B2 (en) * | 2000-11-28 | 2007-05-22 | Synplicity, Inc. | Hardware-based HDL code coverage and design analysis |
GB2379524A (en) * | 2001-09-06 | 2003-03-12 | Nec Technologies | Multiplexing pins on an ASIC |
US6898750B2 (en) | 2002-01-16 | 2005-05-24 | Microtune (San Diego), Inc. | In-chip monitoring system to monitor input/output of functional blocks |
US7249298B2 (en) * | 2002-04-30 | 2007-07-24 | Samsung Electronics Co., Ltd. | Multiple scan chains with pin sharing |
US7424658B1 (en) | 2002-07-01 | 2008-09-09 | Altera Corporation | Method and apparatus for testing integrated circuits |
TW569221B (en) * | 2002-09-11 | 2004-01-01 | Elan Microelectronics Corp | Chip having on-system programmable nonvolatile memory and off-system programmable nonvolatile memory, and forming method and programming method of the same |
US7010733B2 (en) * | 2002-10-09 | 2006-03-07 | International Business Machines Corporation | Parametric testing for high pin count ASIC |
US7191265B1 (en) | 2003-04-29 | 2007-03-13 | Cisco Technology, Inc. | JTAG and boundary scan automatic chain selection |
CN100351638C (zh) * | 2003-05-01 | 2007-11-28 | 中兴通讯股份有限公司 | 一种集成电路边界扫描测试装置 |
CN100348992C (zh) * | 2003-11-19 | 2007-11-14 | 华为技术有限公司 | 一种外围互连线的测试方法 |
US7332928B2 (en) * | 2004-03-05 | 2008-02-19 | Finisar Corporation | Use of a third state applied to a digital input terminal of a circuit to initiate non-standard operational modes of the circuit |
US8205186B1 (en) | 2005-04-11 | 2012-06-19 | Synopsys, Inc. | Incremental modification of instrumentation logic |
US7518397B2 (en) * | 2007-01-03 | 2009-04-14 | International Rectifier Corporation | Chip with in-circuit programability |
TWI343773B (en) * | 2007-10-19 | 2011-06-11 | Realtek Semiconductor Corp | Microelectronic device and pin arrangement method thereof |
WO2009063359A1 (en) * | 2007-11-14 | 2009-05-22 | Koninklijke Philips Electronics N.V. | General purpose serial communication using jtag interface |
JP5167904B2 (ja) * | 2008-03-28 | 2013-03-21 | 富士通株式会社 | スキャン制御方法、スキャン制御回路及び装置 |
US10162000B2 (en) * | 2012-02-16 | 2018-12-25 | Nxp B.V. | Testing an integrated circuit device with multiple testing protocols |
US9742847B2 (en) * | 2013-08-30 | 2017-08-22 | Texas Instruments Incorporated | Network node physical/communication pins, state machines, interpreter and executor circuitry |
US9817066B1 (en) * | 2014-08-26 | 2017-11-14 | Xilinx, Inc. | Configurable JTAG-to-serial bus translator |
CN111665432B (zh) * | 2020-05-22 | 2022-10-25 | 中国人民解放军国防科技大学 | 芯片引脚复用模块的验证方法、装置、设备及存储介质 |
Family Cites Families (23)
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US4870302A (en) * | 1984-03-12 | 1989-09-26 | Xilinx, Inc. | Configurable electrical circuit having configurable logic elements and configurable interconnects |
US4852044A (en) * | 1985-03-04 | 1989-07-25 | Lattice Semiconductor Corporation | Programmable data security circuit for programmable logic device |
US4833646A (en) * | 1985-03-04 | 1989-05-23 | Lattice Semiconductor Corp. | Programmable logic device with limited sense currents and noise reduction |
US4879688A (en) * | 1985-03-04 | 1989-11-07 | Lattice Semiconductor Corporation | In-system programmable logic device |
US4855954A (en) * | 1985-03-04 | 1989-08-08 | Lattice Semiconductor Corporation | In-system programmable logic device with four dedicated terminals |
US4766569A (en) * | 1985-03-04 | 1988-08-23 | Lattice Semiconductor Corporation | Programmable logic array |
US4896296A (en) * | 1985-03-04 | 1990-01-23 | Lattice Semiconductor Corporation | Programmable logic device configurable input/output cell |
US4887239A (en) * | 1985-03-04 | 1989-12-12 | Lattice Semiconductor Corporation | One-time programmable data security system for programmable logic device |
US4761768A (en) * | 1985-03-04 | 1988-08-02 | Lattice Semiconductor Corporation | Programmable logic device |
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US4918641A (en) * | 1987-08-26 | 1990-04-17 | Ict International Cmos Technology, Inc. | High-performance programmable logic device |
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JP2541248B2 (ja) * | 1987-11-20 | 1996-10-09 | 三菱電機株式会社 | プログラマブル・ロジック・アレイ |
US5023606A (en) * | 1988-01-13 | 1991-06-11 | Plus Logic, Inc. | Programmable logic device with ganged output pins |
KR910005615B1 (ko) * | 1988-07-18 | 1991-07-31 | 삼성전자 주식회사 | 프로그래머블 순차코오드 인식회로 |
US5023484A (en) * | 1988-09-02 | 1991-06-11 | Cypress Semiconductor Corporation | Architecture of high speed synchronous state machine |
JP2518039B2 (ja) * | 1989-03-06 | 1996-07-24 | 日本電気株式会社 | デ―タ処理装置の制御記憶ロ―ド方法 |
JP2650124B2 (ja) * | 1989-07-11 | 1997-09-03 | 三菱電機株式会社 | 半導体集積回路 |
JPH0756749B2 (ja) * | 1989-09-29 | 1995-06-14 | 株式会社東芝 | 機能選択回路 |
US5027011A (en) * | 1989-10-31 | 1991-06-25 | Sgs-Thomson Microelectronics, Inc. | Input row drivers for programmable logic devices |
US5072138A (en) * | 1990-08-17 | 1991-12-10 | Sgs-Thomson Microelectronics, Inc. | Semiconductor memory with sequential clocked access codes for test mode entry |
IT1246301B (it) * | 1990-10-22 | 1994-11-17 | St Microelectronics Srl | Dispositivo di analisi operativa di tipo scan path a singolo clock di scansione e singola fase di uscita per circuito integrato. |
US5237218A (en) * | 1991-05-03 | 1993-08-17 | Lattice Semiconductor Corporation | Structure and method for multiplexing pins for in-system programming |
-
1993
- 1993-08-13 US US08/106,263 patent/US5412260A/en not_active Expired - Lifetime
-
1994
- 1994-07-28 DE DE69433259T patent/DE69433259D1/de not_active Expired - Lifetime
- 1994-07-28 DE DE0639006T patent/DE639006T1/de active Pending
- 1994-07-28 EP EP94202212A patent/EP0639006B1/de not_active Expired - Lifetime
- 1994-08-12 JP JP21192294A patent/JPH07175677A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
US5412260A (en) | 1995-05-02 |
JPH07175677A (ja) | 1995-07-14 |
DE69433259D1 (de) | 2003-11-27 |
EP0639006A1 (de) | 1995-02-15 |
EP0639006B1 (de) | 2003-10-22 |
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