DE60218685D1 - Herstellungsverfahren für Zellenanordnung mit bipolaren Auswahltransistoren und zugehörige Zellenanordnung - Google Patents

Herstellungsverfahren für Zellenanordnung mit bipolaren Auswahltransistoren und zugehörige Zellenanordnung

Info

Publication number
DE60218685D1
DE60218685D1 DE60218685T DE60218685T DE60218685D1 DE 60218685 D1 DE60218685 D1 DE 60218685D1 DE 60218685 T DE60218685 T DE 60218685T DE 60218685 T DE60218685 T DE 60218685T DE 60218685 D1 DE60218685 D1 DE 60218685D1
Authority
DE
Germany
Prior art keywords
cell array
fabrication process
select transistors
bipolar select
associated cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60218685T
Other languages
English (en)
Other versions
DE60218685T2 (de
Inventor
Fabio Pellizzer
Giulio Casagrande
Roberto Gastaldi
Loris Vendrame
Augusto Benvenuti
Tyler Lowrey
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Ovonyx Inc
Original Assignee
STMicroelectronics SRL
Ovonyx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL, Ovonyx Inc filed Critical STMicroelectronics SRL
Publication of DE60218685D1 publication Critical patent/DE60218685D1/de
Application granted granted Critical
Publication of DE60218685T2 publication Critical patent/DE60218685T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/685—Hi-Lo semiconductor devices, e.g. memory devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
DE60218685T 2002-10-08 2002-10-08 Herstellungsverfahren für Zellenanordnung mit bipolaren Auswahltransistoren und zugehörige Zellenanordnung Expired - Lifetime DE60218685T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP02425604A EP1408549B1 (de) 2002-10-08 2002-10-08 Herstellungsverfahren für Zellenanordnung mit bipolaren Auswahltransistoren und zugehörige Zellenanordnung

Publications (2)

Publication Number Publication Date
DE60218685D1 true DE60218685D1 (de) 2007-04-19
DE60218685T2 DE60218685T2 (de) 2007-11-15

Family

ID=32011064

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60218685T Expired - Lifetime DE60218685T2 (de) 2002-10-08 2002-10-08 Herstellungsverfahren für Zellenanordnung mit bipolaren Auswahltransistoren und zugehörige Zellenanordnung

Country Status (3)

Country Link
US (2) US6989580B2 (de)
EP (1) EP1408549B1 (de)
DE (1) DE60218685T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1408550B1 (de) * 2002-10-08 2006-12-27 STMicroelectronics S.r.l. Zellenanordnung mit Bipolar-Auswahl-Transistor und Herstellungsverfahren
JP4670458B2 (ja) * 2005-04-27 2011-04-13 株式会社日立製作所 半導体装置
US7800143B2 (en) * 2006-07-13 2010-09-21 Globalfoundries Inc. Dynamic random access memory with an amplified capacitor
US7679955B2 (en) 2006-08-02 2010-03-16 Advanced Micro Devices, Inc. Semiconductor switching device
US7847374B1 (en) * 2007-07-06 2010-12-07 Chih-Hsin Wang Non-volatile memory cell array and logic
EP2015357A1 (de) * 2007-07-09 2009-01-14 STMicroelectronics S.r.l. Herstellungsverfahren für ein Zellenfeld mit bipolaren Auswahltransistoren mit hervorstehenden leitfähigen Bereichen
JP2009135290A (ja) * 2007-11-30 2009-06-18 Sanyo Electric Co Ltd 半導体メモリ装置
US8138574B2 (en) * 2008-05-16 2012-03-20 International Business Machines Corporation PCM with poly-emitter BJT access devices
US7932582B2 (en) * 2008-06-18 2011-04-26 National Semiconductor Corporation Compact dual direction BJT clamps
US7847373B2 (en) * 2008-12-22 2010-12-07 Agostino Pirovano Fabricating bipolar junction select transistors for semiconductor memories
FR3079965A1 (fr) 2018-04-06 2019-10-11 Stmicroelectronics (Rousset) Sas Circuit integre a transistors a base commune
FR3079964A1 (fr) 2018-04-06 2019-10-11 Stmicroelectronics (Crolles 2) Sas Circuit integre a transistors bipolaires
US11715520B2 (en) 2021-04-05 2023-08-01 Micron Technology, Inc. Socket structure for spike current suppression in a memory array
US11348640B1 (en) * 2021-04-05 2022-05-31 Micron Technology, Inc. Charge screening structure for spike current suppression in a memory array
US11514985B2 (en) 2021-04-05 2022-11-29 Micron Technology, Inc. Spike current suppression in a memory array
US11862215B2 (en) 2021-08-27 2024-01-02 Micron Technology, Inc. Access line having a resistive layer for memory cell access

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Publication number Priority date Publication date Assignee Title
US4180866A (en) * 1977-08-01 1979-12-25 Burroughs Corporation Single transistor memory cell employing an amorphous semiconductor threshold device
US4981807A (en) 1988-10-31 1991-01-01 International Business Machines Corporation Process for fabricating complementary vertical transistor memory cell
KR940001425B1 (ko) * 1990-11-06 1994-02-23 재단법인 한국전자통신연구소 수직구조를 갖는 바이폴라형 다이내믹 램을 제조하는 방법 및 그 다이내믹 램의 구조
US5276638A (en) 1991-07-31 1994-01-04 International Business Machines Corporation Bipolar memory cell with isolated PNP load
KR0171128B1 (ko) * 1995-04-21 1999-02-01 김우중 수직형 바이폴라 트랜지스터
US5789758A (en) * 1995-06-07 1998-08-04 Micron Technology, Inc. Chalcogenide memory cell with a plurality of chalcogenide electrodes
US6653733B1 (en) * 1996-02-23 2003-11-25 Micron Technology, Inc. Conductors in semiconductor devices
US6043527A (en) * 1998-04-14 2000-03-28 Micron Technology, Inc. Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device
JP2001035926A (ja) * 1999-07-19 2001-02-09 Nec Corp 半導体装置及びその製造方法
US6649928B2 (en) * 2000-12-13 2003-11-18 Intel Corporation Method to selectively remove one side of a conductive bottom electrode of a phase-change memory cell and structure obtained thereby
US6437383B1 (en) * 2000-12-21 2002-08-20 Intel Corporation Dual trench isolation for a phase-change memory cell and method of making same
US6534781B2 (en) * 2000-12-26 2003-03-18 Ovonyx, Inc. Phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact
US6531373B2 (en) * 2000-12-27 2003-03-11 Ovonyx, Inc. Method of forming a phase-change memory cell using silicon on insulator low electrode in charcogenide elements
JP3869682B2 (ja) * 2001-06-12 2007-01-17 株式会社ルネサステクノロジ 半導体装置
US6838723B2 (en) * 2002-08-29 2005-01-04 Micron Technology, Inc. Merged MOS-bipolar capacitor memory cell
EP1408550B1 (de) * 2002-10-08 2006-12-27 STMicroelectronics S.r.l. Zellenanordnung mit Bipolar-Auswahl-Transistor und Herstellungsverfahren

Also Published As

Publication number Publication date
US7563684B2 (en) 2009-07-21
EP1408549A1 (de) 2004-04-14
US20040130000A1 (en) 2004-07-08
DE60218685T2 (de) 2007-11-15
US20060049392A1 (en) 2006-03-09
US6989580B2 (en) 2006-01-24
EP1408549B1 (de) 2007-03-07

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