DE602007014413D1 - Datentransfernetzwerk und steuervorrichtung für ein system mit einem array von verarbeitungselementen, die jeweils entweder selbst- oder gemeinsam gesteuert sind - Google Patents

Datentransfernetzwerk und steuervorrichtung für ein system mit einem array von verarbeitungselementen, die jeweils entweder selbst- oder gemeinsam gesteuert sind

Info

Publication number
DE602007014413D1
DE602007014413D1 DE602007014413T DE602007014413T DE602007014413D1 DE 602007014413 D1 DE602007014413 D1 DE 602007014413D1 DE 602007014413 T DE602007014413 T DE 602007014413T DE 602007014413 T DE602007014413 T DE 602007014413T DE 602007014413 D1 DE602007014413 D1 DE 602007014413D1
Authority
DE
Germany
Prior art keywords
self
processing elements
controlled
array
control device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602007014413T
Other languages
English (en)
Inventor
Hanno Lieske
Shorin Kyo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE602007014413D1 publication Critical patent/DE602007014413D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Multi Processors (AREA)
  • Advance Control (AREA)
DE602007014413T 2007-03-06 2007-03-06 Datentransfernetzwerk und steuervorrichtung für ein system mit einem array von verarbeitungselementen, die jeweils entweder selbst- oder gemeinsam gesteuert sind Active DE602007014413D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/054756 WO2008108005A1 (en) 2007-03-06 2007-03-06 A data transfer network and control apparatus for a system with an array of processing elements each either self- or common controlled

Publications (1)

Publication Number Publication Date
DE602007014413D1 true DE602007014413D1 (de) 2011-06-16

Family

ID=38616413

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602007014413T Active DE602007014413D1 (de) 2007-03-06 2007-03-06 Datentransfernetzwerk und steuervorrichtung für ein system mit einem array von verarbeitungselementen, die jeweils entweder selbst- oder gemeinsam gesteuert sind

Country Status (6)

Country Link
US (1) US8190856B2 (de)
EP (1) EP2132645B1 (de)
JP (1) JP5158091B2 (de)
AT (1) ATE508415T1 (de)
DE (1) DE602007014413D1 (de)
WO (1) WO2008108005A1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5488609B2 (ja) * 2009-03-30 2014-05-14 日本電気株式会社 リングバスによって相互接続された複数の処理要素を有する単一命令多重データ（ｓｉｍｄ）プロセッサ
WO2010113340A1 (en) * 2009-03-30 2010-10-07 Nec Corporation Single instruction multiple data (simd) processor having a plurality of processing elements interconnected by a ring bus
WO2011064898A1 (en) 2009-11-26 2011-06-03 Nec Corporation Apparatus to enable time and area efficient access to square matrices and its transposes distributed stored in internal memory of processing elements working in simd mode and method therefore
JP5829331B2 (ja) * 2011-09-27 2015-12-09 ルネサスエレクトロニクス株式会社 Ｓｉｍｄプロセッサシステムにおいて複数の対象領域（ｒｏｉ）を同時並列的にデータ転送するための装置
ES2391733B2 (es) * 2011-12-30 2013-05-10 Universidade De Santiago De Compostela Arquitectura híbrida simd/mimd dinámicamente reconfigurable de un coprocesador para sistemas de visión
US20140189298A1 (en) * 2012-12-27 2014-07-03 Teresa Morrison Configurable ring network
WO2016051435A1 (en) * 2014-10-01 2016-04-07 Renesas Electronics Corporation Data transfer apparatus and microcomputer

Family Cites Families (13)

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Publication number Priority date Publication date Assignee Title
US3537074A (en) 1967-12-20 1970-10-27 Burroughs Corp Parallel operating array computer
US4837676A (en) 1984-11-05 1989-06-06 Hughes Aircraft Company MIMD instruction flow computer architecture
FR2622989B1 (fr) 1987-11-06 1992-11-27 Thomson Csf Machine multiprocesseur reconfigurable pour traitement du signal
US5212777A (en) 1989-11-17 1993-05-18 Texas Instruments Incorporated Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD) modes and method of operation
US5239654A (en) 1989-11-17 1993-08-24 Texas Instruments Incorporated Dual mode SIMD/MIMD processor providing reuse of MIMD instruction memories as data memories when operating in SIMD mode
US5522083A (en) * 1989-11-17 1996-05-28 Texas Instruments Incorporated Reconfigurable multi-processor operating in SIMD mode with one processor fetching instructions for use by remaining processors
WO1991017507A1 (en) 1990-05-07 1991-11-14 Mitsubishi Denki Kabushiki Kaisha Parallel data processing system
JPH07122866B1 (de) * 1990-05-07 1995-12-25 Mitsubishi Electric Corp
JPH0668053A (ja) * 1992-08-20 1994-03-11 Toshiba Corp 並列計算機
JPH10508714A (ja) * 1994-11-07 1998-08-25 テンプル ユニヴァーシティ − オブ ザ カモン ウェルス システム オブ ハイヤー エデュケイション マルチコンピュータ・システムおよび方法
US5903771A (en) 1996-01-16 1999-05-11 Alacron, Inc. Scalable multi-processor architecture for SIMD and MIMD operations
WO2001031475A1 (en) 1999-10-26 2001-05-03 Arthur D. Little, Inc. Dual aspect ratio pe array with no connection switching
AU2002233500A1 (en) * 2001-02-14 2002-08-28 Clearspeed Technology Limited An interconnection system

Also Published As

Publication number Publication date
ATE508415T1 (de) 2011-05-15
US8190856B2 (en) 2012-05-29
EP2132645A1 (de) 2009-12-16
JP2010520519A (ja) 2010-06-10
US20100088489A1 (en) 2010-04-08
WO2008108005A1 (en) 2008-09-12
EP2132645B1 (de) 2011-05-04
JP5158091B2 (ja) 2013-03-06

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